lib/Target/Blackfin/BlackfinRegisterInfo.cpp

   1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Blackfin implementation of the TargetRegisterInfo
  11 // class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "Blackfin.h"
  16 #include "BlackfinRegisterInfo.h"
  17 #include "BlackfinSubtarget.h"
  18 #include "llvm/Support/Debug.h"
  19 #include "llvm/Support/ErrorHandling.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineLocation.h"
  24 #include "llvm/CodeGen/RegisterScavenging.h"
  25 #include "llvm/Target/TargetFrameInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Target/TargetOptions.h"
  28 #include "llvm/Target/TargetInstrInfo.h"
  29 #include "llvm/Type.h"
  30 #include "llvm/ADT/BitVector.h"
  31 #include "llvm/ADT/STLExtras.h"
  32 using namespace llvm;
  33
  34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
  35                                            const TargetInstrInfo &tii)
  36   : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
  37     Subtarget(st),
  38     TII(tii) {}
  39
  40 const unsigned*
  41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  42   using namespace BF;
  43   static const unsigned CalleeSavedRegs[] = {
  44     FP,
  45     R4, R5, R6, R7,
  46     P3, P4, P5,
  47     0 };
  48   return  CalleeSavedRegs;
  49 }
  50
  51 const TargetRegisterClass* const *BlackfinRegisterInfo::
  52 getCalleeSavedRegClasses(const MachineFunction *MF) const {
  53   using namespace BF;
  54   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
  55     &PRegClass,
  56     &DRegClass, &DRegClass, &DRegClass, &DRegClass,
  57     &PRegClass, &PRegClass, &PRegClass,
  58     0 };
  59   return CalleeSavedRegClasses;
  60 }
  61
  62 BitVector
  63 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  64   using namespace BF;
  65   BitVector Reserved(getNumRegs());
  66   Reserved.set(AZ);
  67   Reserved.set(AN);
  68   Reserved.set(AQ);
  69   Reserved.set(AC0);
  70   Reserved.set(AC1);
  71   Reserved.set(AV0);
  72   Reserved.set(AV0S);
  73   Reserved.set(AV1);
  74   Reserved.set(AV1S);
  75   Reserved.set(V);
  76   Reserved.set(VS);
  77   Reserved.set(CYCLES).set(CYCLES2);
  78   Reserved.set(L0);
  79   Reserved.set(L1);
  80   Reserved.set(L2);
  81   Reserved.set(L3);
  82   Reserved.set(SP);
  83   Reserved.set(RETS);
  84   if (hasFP(MF))
  85     Reserved.set(FP);
  86   return Reserved;
  87 }
  88
  89 const TargetRegisterClass*
  90 BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
  91   assert(isPhysicalRegister(reg) && "reg must be a physical register");
  92
  93   // Pick the smallest register class of the right type that contains
  94   // this physreg.
  95   const TargetRegisterClass* BestRC = 0;
  96   for (regclass_iterator I = regclass_begin(), E = regclass_end();
  97        I != E; ++I) {
  98     const TargetRegisterClass* RC = *I;
  99     if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
 100         (!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
 101       BestRC = RC;
 102   }
 103
 104   assert(BestRC && "Couldn't find the register class");
 105   return BestRC;
 106 }
 107
 108 // hasFP - Return true if the specified function should have a dedicated frame
 109 // pointer register.  This is true if the function has variable sized allocas or
 110 // if frame pointer elimination is disabled.
 111 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
 112   const MachineFrameInfo *MFI = MF.getFrameInfo();
 113   return NoFramePointerElim || MFI->hasCalls() || MFI->hasVarSizedObjects();
 114 }
 115
 116 bool BlackfinRegisterInfo::
 117 requiresRegisterScavenging(const MachineFunction &MF) const {
 118   return true;
 119 }
 120
 121 // Emit instructions to add delta to D/P register. ScratchReg must be of the
 122 // same class as Reg (P).
 123 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
 124                                           MachineBasicBlock::iterator I,
 125                                           DebugLoc DL,
 126                                           unsigned Reg,
 127                                           unsigned ScratchReg,
 128                                           int delta) const {
 129   if (!delta)
 130     return;
 131   if (isInt<7>(delta)) {
 132     BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
 133       .addReg(Reg)              // No kill on two-addr operand
 134       .addImm(delta);
 135     return;
 136   }
 137
 138   // We must load delta into ScratchReg and add that.
 139   loadConstant(MBB, I, DL, ScratchReg, delta);
 140   if (BF::PRegClass.contains(Reg)) {
 141     assert(BF::PRegClass.contains(ScratchReg) &&
 142            "ScratchReg must be a P register");
 143     BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
 144       .addReg(Reg, RegState::Kill)
 145       .addReg(ScratchReg, RegState::Kill);
 146   } else {
 147     assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
 148     assert(BF::DRegClass.contains(ScratchReg) &&
 149            "ScratchReg must be a D register");
 150     BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
 151       .addReg(Reg, RegState::Kill)
 152       .addReg(ScratchReg, RegState::Kill);
 153   }
 154 }
 155
 156 // Emit instructions to load a constant into D/P register
 157 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
 158                                         MachineBasicBlock::iterator I,
 159                                         DebugLoc DL,
 160                                         unsigned Reg,
 161                                         int value) const {
 162   if (isInt<7>(value)) {
 163     BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
 164     return;
 165   }
 166
 167   if (isUint<16>(value)) {
 168     BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
 169     return;
 170   }
 171
 172   if (isInt<16>(value)) {
 173     BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
 174     return;
 175   }
 176
 177   // We must split into halves
 178   BuildMI(MBB, I, DL,
 179           TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_hi16))
 180     .addImm((value >> 16) & 0xffff)
 181     .addReg(Reg, RegState::ImplicitDefine);
 182   BuildMI(MBB, I, DL,
 183           TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_lo16))
 184     .addImm(value & 0xffff)
 185     .addReg(Reg, RegState::ImplicitKill)
 186     .addReg(Reg, RegState::ImplicitDefine);
 187 }
 188
 189 void BlackfinRegisterInfo::
 190 eliminateCallFramePseudoInstr(MachineFunction &MF,
 191                               MachineBasicBlock &MBB,
 192                               MachineBasicBlock::iterator I) const {
 193   if (!hasReservedCallFrame(MF)) {
 194     int64_t Amount = I->getOperand(0).getImm();
 195     if (Amount != 0) {
 196       assert(Amount%4 == 0 && "Unaligned call frame size");
 197       if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
 198         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
 199       } else {
 200         assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
 201                "Unknown call frame pseudo instruction");
 202         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
 203       }
 204     }
 205   }
 206   MBB.erase(I);
 207 }
 208
 209 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
 210 /// register first and then a spilled callee-saved register if that fails.
 211 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
 212                                     RegScavenger *RS,
 213                                     const TargetRegisterClass *RC,
 214                                     int SPAdj) {
 215   assert(RS && "Register scavenging must be on");
 216   unsigned Reg = RS->FindUnusedReg(RC);
 217   if (Reg == 0)
 218     Reg = RS->scavengeRegister(RC, II, SPAdj);
 219   return Reg;
 220 }
 221
 222 void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 223                                                int SPAdj,
 224                                                RegScavenger *RS) const {
 225   MachineInstr &MI = *II;
 226   MachineBasicBlock &MBB = *MI.getParent();
 227   MachineFunction &MF = *MBB.getParent();
 228   DebugLoc DL = MI.getDebugLoc();
 229
 230   unsigned FIPos;
 231   for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
 232     assert(FIPos < MI.getNumOperands() &&
 233            "Instr doesn't have FrameIndex operand!");
 234   }
 235   int FrameIndex = MI.getOperand(FIPos).getIndex();
 236   assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
 237   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
 238     + MI.getOperand(FIPos+1).getImm();
 239   unsigned BaseReg = BF::FP;
 240   if (hasFP(MF)) {
 241     assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
 242   } else {
 243     BaseReg = BF::SP;
 244     Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
 245   }
 246
 247   bool isStore = false;
 248
 249   switch (MI.getOpcode()) {
 250   case BF::STORE32fi:
 251     isStore = true;
 252   case BF::LOAD32fi: {
 253     assert(Offset%4 == 0 && "Unaligned i32 stack access");
 254     assert(FIPos==1 && "Bad frame index operand");
 255     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 256     MI.getOperand(FIPos+1).setImm(Offset);
 257     if (isUint<6>(Offset)) {
 258       MI.setDesc(TII.get(isStore
 259                          ? BF::STORE32p_uimm6m4
 260                          : BF::LOAD32p_uimm6m4));
 261       return;
 262     }
 263     if (BaseReg == BF::FP && isUint<7>(-Offset)) {
 264       MI.setDesc(TII.get(isStore
 265                          ? BF::STORE32fp_nimm7m4
 266                          : BF::LOAD32fp_nimm7m4));
 267       MI.getOperand(FIPos+1).setImm(-Offset);
 268       return;
 269     }
 270     if (isInt<18>(Offset)) {
 271       MI.setDesc(TII.get(isStore
 272                          ? BF::STORE32p_imm18m4
 273                          : BF::LOAD32p_imm18m4));
 274       return;
 275     }
 276     // Use RegScavenger to calculate proper offset...
 277     MI.dump();
 278     llvm_unreachable("Stack frame offset too big");
 279     break;
 280   }
 281   case BF::ADDpp: {
 282     assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
 283     unsigned DestReg = MI.getOperand(0).getReg();
 284     // We need to produce a stack offset in a P register. We emit:
 285     // P0 = offset;
 286     // P0 = BR + P0;
 287     assert(FIPos==1 && "Bad frame index operand");
 288     loadConstant(MBB, II, DL, DestReg, Offset);
 289     MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
 290     MI.getOperand(2).ChangeToRegister(BaseReg, false);
 291     break;
 292   }
 293   case BF::STORE16fi:
 294     isStore = true;
 295   case BF::LOAD16fi: {
 296     assert(Offset%2 == 0 && "Unaligned i16 stack access");
 297     assert(FIPos==1 && "Bad frame index operand");
 298     // We need a P register to use as an address
 299     unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
 300     assert(ScratchReg && "Could not scavenge register");
 301     loadConstant(MBB, II, DL, ScratchReg, Offset);
 302     BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
 303       .addReg(ScratchReg, RegState::Kill)
 304       .addReg(BaseReg);
 305     MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
 306     MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
 307     MI.RemoveOperand(2);
 308     break;
 309   }
 310   case BF::STORE8fi: {
 311     // This is an AnyCC spill, we need a scratch register.
 312     assert(FIPos==1 && "Bad frame index operand");
 313     MachineOperand SpillReg = MI.getOperand(0);
 314     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 315     assert(ScratchReg && "Could not scavenge register");
 316     if (SpillReg.getReg()==BF::NCC) {
 317       BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
 318         .addOperand(SpillReg);
 319       BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
 320         .addReg(ScratchReg).addImm(0);
 321     } else {
 322       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
 323         .addOperand(SpillReg);
 324     }
 325     // STORE D
 326     MI.setDesc(TII.get(BF::STORE8p_imm16));
 327     MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
 328     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 329     MI.getOperand(FIPos+1).setImm(Offset);
 330     break;
 331   }
 332   case BF::LOAD8fi: {
 333     // This is an restore, we need a scratch register.
 334     assert(FIPos==1 && "Bad frame index operand");
 335     MachineOperand SpillReg = MI.getOperand(0);
 336     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 337     assert(ScratchReg && "Could not scavenge register");
 338     MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
 339     MI.getOperand(0).ChangeToRegister(ScratchReg, true);
 340     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 341     MI.getOperand(FIPos+1).setImm(Offset);
 342     ++II;
 343     if (SpillReg.getReg()==BF::CC) {
 344       // CC = D
 345       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
 346         .addReg(ScratchReg, RegState::Kill);
 347     } else {
 348       // Restore NCC (CC = D==0)
 349       BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
 350         .addReg(ScratchReg, RegState::Kill)
 351         .addImm(0);
 352     }
 353     break;
 354   }
 355   default:
 356     llvm_unreachable("Cannot eliminate frame index");
 357     break;
 358   }
 359 }
 360
 361 void BlackfinRegisterInfo::
 362 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 363                                      RegScavenger *RS) const {
 364   MachineFrameInfo *MFI = MF.getFrameInfo();
 365   const TargetRegisterClass *RC = BF::DPRegisterClass;
 366   if (requiresRegisterScavenging(MF)) {
 367     // Reserve a slot close to SP or frame pointer.
 368     RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
 369                                                        RC->getAlignment()));
 370   }
 371 }
 372
 373 void BlackfinRegisterInfo::
 374 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
 375 }
 376
 377 // Emit a prologue that sets up a stack frame.
 378 // On function entry, R0-R2 and P0 may hold arguments.
 379 // R3, P1, and P2 may be used as scratch registers
 380 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
 381   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 382   MachineBasicBlock::iterator MBBI = MBB.begin();
 383   MachineFrameInfo *MFI = MF.getFrameInfo();
 384   DebugLoc dl = (MBBI != MBB.end()
 385                  ? MBBI->getDebugLoc()
 386                  : DebugLoc::getUnknownLoc());
 387
 388   int FrameSize = MFI->getStackSize();
 389   if (FrameSize%4) {
 390     FrameSize = (FrameSize+3) & ~3;
 391     MFI->setStackSize(FrameSize);
 392   }
 393
 394   if (!hasFP(MF)) {
 395     assert(!MFI->hasCalls() &&
 396            "FP elimination on a non-leaf function is not supported");
 397     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
 398     return;
 399   }
 400
 401   // emit a LINK instruction
 402   if (FrameSize <= 0x3ffff) {
 403     BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
 404     return;
 405   }
 406
 407   // Frame is too big, do a manual LINK:
 408   // [--SP] = RETS;
 409   // [--SP] = FP;
 410   // FP = SP;
 411   // P1 = -FrameSize;
 412   // SP = SP + P1;
 413   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 414     .addReg(BF::RETS, RegState::Kill);
 415   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 416     .addReg(BF::FP, RegState::Kill);
 417   BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
 418     .addReg(BF::SP);
 419   loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
 420   BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
 421     .addReg(BF::SP, RegState::Kill)
 422     .addReg(BF::P1, RegState::Kill);
 423
 424 }
 425
 426 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
 427                                         MachineBasicBlock &MBB) const {
 428   MachineFrameInfo *MFI = MF.getFrameInfo();
 429   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 430   DebugLoc dl = MBBI->getDebugLoc();
 431
 432   int FrameSize = MFI->getStackSize();
 433   assert(FrameSize%4 == 0 && "Misaligned frame size");
 434
 435   if (!hasFP(MF)) {
 436     assert(!MFI->hasCalls() &&
 437            "FP elimination on a non-leaf function is not supported");
 438     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
 439     return;
 440   }
 441
 442   // emit an UNLINK instruction
 443   BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
 444 }
 445
 446 unsigned BlackfinRegisterInfo::getRARegister() const {
 447   return BF::RETS;
 448 }
 449
 450 unsigned BlackfinRegisterInfo::getFrameRegister(MachineFunction &MF) const {
 451   return hasFP(MF) ? BF::FP : BF::SP;
 452 }
 453
 454 int
 455 BlackfinRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
 456   const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
 457   MachineFrameInfo *MFI = MF.getFrameInfo();
 458   return MFI->getObjectOffset(FI) + MFI->getStackSize() -
 459     TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
 460 }
 461
 462 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
 463   llvm_unreachable("What is the exception register");
 464   return 0;
 465 }
 466
 467 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
 468   llvm_unreachable("What is the exception handler register");
 469   return 0;
 470 }
 471
 472 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 473   llvm_unreachable("What is the dwarf register number");
 474   return -1;
 475 }
 476
 477 #include "BlackfinGenRegisterInfo.inc"
 478