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this is failing on linux hosts, force a triple.
[llvm/avr.git] / lib / Target / PIC16 / PIC16ISelLowering.cpp
bloba779f1587cf28529604ebe8b55d70c291287fe38
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "pic16-lower"
15 #include "PIC16ISelLowering.h"
16 #include "PIC16TargetObjectFile.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27
28
29 using namespace llvm;
30
31 static const char *getIntrinsicName(unsigned opcode) {
32 std::string Basename;
33 switch(opcode) {
34 default: llvm_unreachable("do not know intrinsic name");
35 // Arithmetic Right shift for integer types.
36 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
37 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
38 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
39
40 // Left shift for integer types.
41 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
42 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
43 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
44
45 // Logical Right Shift for integer types.
46 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
47 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
48 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
49
50 // Multiply for integer types.
51 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
52 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
53 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
54
55 // Signed division for integers.
56 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
57 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
58
59 // Unsigned division for integers.
60 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
61 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
62
63 // Signed Modulas for integers.
64 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
65 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
66
67 // Unsigned Modulas for integers.
68 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
69 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
70
71 //////////////////////
72 // LIBCALLS FOR FLOATS
73 //////////////////////
74
75 // Float to signed integrals
76 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
78 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
79
80 // Signed integrals to float. char and int are first sign extended to i32
81 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
82 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
83
84 // Float to Unsigned conversions.
85 // Signed conversion can be used for unsigned conversion as well.
86 // In signed and unsigned versions only the interpretation of the
87 // MSB is different. Bit representation remains the same.
88 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
90 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
91
92 // Unsigned to Float conversions. char and int are first zero extended
93 // before being converted to float.
94 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
95
96 // Floating point add, sub, mul, div.
97 case RTLIB::ADD_F32: Basename = "add.f32"; break;
98 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
99 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
100 case RTLIB::DIV_F32: Basename = "div.f32"; break;
101
102 // Floating point comparison
103 case RTLIB::O_F32: Basename = "unordered.f32"; break;
104 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
105 case RTLIB::OLE_F32: Basename = "le.f32"; break;
106 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
107 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
108 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
109 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
110 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
111 }
112
113 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
114 std::string tagname = PAN::getTagName(PAN::LIBCALL);
115 std::string Fullname = prefix + tagname + Basename;
116
117 // The name has to live through program life.
118 return createESName(Fullname);
119 }
120
121 // getStdLibCallName - Get the name for the standard library function.
122 static const char *getStdLibCallName(unsigned opcode) {
123 std::string BaseName;
124 switch(opcode) {
125 case RTLIB::COS_F32: BaseName = "cos";
126 break;
127 case RTLIB::SIN_F32: BaseName = "sin";
128 break;
129 case RTLIB::MEMCPY: BaseName = "memcpy";
130 break;
131 case RTLIB::MEMSET: BaseName = "memset";
132 break;
133 case RTLIB::MEMMOVE: BaseName = "memmove";
134 break;
135 default: llvm_unreachable("do not know std lib call name");
136 }
137 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
138 std::string LibCallName = prefix + BaseName;
139
140 // The name has to live through program life.
141 return createESName(LibCallName);
142 }
143
144 // PIC16TargetLowering Constructor.
145 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
146 : TargetLowering(TM, new PIC16TargetObjectFile()), TmpSize(0) {
147
148 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
149
150 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
151
152 setShiftAmountType(MVT::i8);
153
154 // Std lib call names
155 setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
156 setLibcallName(RTLIB::SIN_F32, getStdLibCallName(RTLIB::SIN_F32));
157 setLibcallName(RTLIB::MEMCPY, getStdLibCallName(RTLIB::MEMCPY));
158 setLibcallName(RTLIB::MEMSET, getStdLibCallName(RTLIB::MEMSET));
159 setLibcallName(RTLIB::MEMMOVE, getStdLibCallName(RTLIB::MEMMOVE));
160
161 // SRA library call names
162 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
163 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
164 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
165
166 // SHL library call names
167 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
168 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
169 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
170
171 // SRL library call names
172 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
173 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
174 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
175
176 // MUL Library call names
177 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
178 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
179 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
180
181 // Signed division lib call names
182 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
183 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
184
185 // Unsigned division lib call names
186 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
187 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
188
189 // Signed remainder lib call names
190 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
191 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
192
193 // Unsigned remainder lib call names
194 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
195 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
196
197 // Floating point to signed int conversions.
198 setLibcallName(RTLIB::FPTOSINT_F32_I8,
199 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
200 setLibcallName(RTLIB::FPTOSINT_F32_I16,
201 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
202 setLibcallName(RTLIB::FPTOSINT_F32_I32,
203 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
204
205 // Signed int to floats.
206 setLibcallName(RTLIB::SINTTOFP_I32_F32,
207 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
208
209 // Floating points to unsigned ints.
210 setLibcallName(RTLIB::FPTOUINT_F32_I8,
211 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
212 setLibcallName(RTLIB::FPTOUINT_F32_I16,
213 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
214 setLibcallName(RTLIB::FPTOUINT_F32_I32,
215 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
216
217 // Unsigned int to floats.
218 setLibcallName(RTLIB::UINTTOFP_I32_F32,
219 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
220
221 // Floating point add, sub, mul ,div.
222 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
223 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
224 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
225 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
226
227 // Floationg point comparison
228 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
229 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
230 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
231 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
232 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
233 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
234 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
235
236 // Return value comparisons of floating point calls.
237 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
238 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
239 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
240 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
241 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
242 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
243 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
244 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
245
246 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
247 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
248
249 setOperationAction(ISD::LOAD, MVT::i8, Legal);
250 setOperationAction(ISD::LOAD, MVT::i16, Custom);
251 setOperationAction(ISD::LOAD, MVT::i32, Custom);
252
253 setOperationAction(ISD::STORE, MVT::i8, Legal);
254 setOperationAction(ISD::STORE, MVT::i16, Custom);
255 setOperationAction(ISD::STORE, MVT::i32, Custom);
256 setOperationAction(ISD::STORE, MVT::i64, Custom);
257
258 setOperationAction(ISD::ADDE, MVT::i8, Custom);
259 setOperationAction(ISD::ADDC, MVT::i8, Custom);
260 setOperationAction(ISD::SUBE, MVT::i8, Custom);
261 setOperationAction(ISD::SUBC, MVT::i8, Custom);
262 setOperationAction(ISD::SUB, MVT::i8, Custom);
263 setOperationAction(ISD::ADD, MVT::i8, Custom);
264 setOperationAction(ISD::ADD, MVT::i16, Custom);
265
266 setOperationAction(ISD::OR, MVT::i8, Custom);
267 setOperationAction(ISD::AND, MVT::i8, Custom);
268 setOperationAction(ISD::XOR, MVT::i8, Custom);
269
270 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
271
272 setOperationAction(ISD::MUL, MVT::i8, Custom);
273
274 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
275 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
276 setOperationAction(ISD::MULHU, MVT::i8, Expand);
277 setOperationAction(ISD::MULHS, MVT::i8, Expand);
278
279 setOperationAction(ISD::SRA, MVT::i8, Custom);
280 setOperationAction(ISD::SHL, MVT::i8, Custom);
281 setOperationAction(ISD::SRL, MVT::i8, Custom);
282
283 setOperationAction(ISD::ROTL, MVT::i8, Expand);
284 setOperationAction(ISD::ROTR, MVT::i8, Expand);
285
286 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
287
288 // PIC16 does not support shift parts
289 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
290 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
291 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
292
293
294 // PIC16 does not have a SETCC, expand it to SELECT_CC.
295 setOperationAction(ISD::SETCC, MVT::i8, Expand);
296 setOperationAction(ISD::SELECT, MVT::i8, Expand);
297 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
298 setOperationAction(ISD::BRIND, MVT::Other, Expand);
299
300 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
301 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
302
303 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
304 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
305
306 // Now deduce the information based on the above mentioned
307 // actions
308 computeRegisterProperties();
309 }
310
311 // getOutFlag - Extract the flag result if the Op has it.
312 static SDValue getOutFlag(SDValue &Op) {
313 // Flag is the last value of the node.
314 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
315
316 assert (Flag.getValueType() == MVT::Flag
317 && "Node does not have an out Flag");
318
319 return Flag;
320 }
321 // Get the TmpOffset for FrameIndex
322 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
323 std::map<unsigned, unsigned>::iterator
324 MapIt = FiTmpOffsetMap.find(FI);
325 if (MapIt != FiTmpOffsetMap.end())
326 return MapIt->second;
327
328 // This FI (FrameIndex) is not yet mapped, so map it
329 FiTmpOffsetMap[FI] = TmpSize;
330 TmpSize += size;
331 return FiTmpOffsetMap[FI];
332 }
333
334 // To extract chain value from the SDValue Nodes
335 // This function will help to maintain the chain extracting
336 // code at one place. In case of any change in future it will
337 // help maintain the code.
338 static SDValue getChain(SDValue &Op) {
339 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
340
341 // If the last value returned in Flag then the chain is
342 // second last value returned.
343 if (Chain.getValueType() == MVT::Flag)
344 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
345
346 // All nodes may not produce a chain. Therefore following assert
347 // verifies that the node is returning a chain only.
348 assert (Chain.getValueType() == MVT::Other
349 && "Node does not have a chain");
350
351 return Chain;
352 }
353
354 /// PopulateResults - Helper function to LowerOperation.
355 /// If a node wants to return multiple results after lowering,
356 /// it stuffs them into an array of SDValue called Results.
357
358 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
359 if (N.getOpcode() == ISD::MERGE_VALUES) {
360 int NumResults = N.getNumOperands();
361 for( int i = 0; i < NumResults; i++)
362 Results.push_back(N.getOperand(i));
363 }
364 else
365 Results.push_back(N);
366 }
367
368 MVT::SimpleValueType
369 PIC16TargetLowering::getSetCCResultType(EVT ValType) const {
370 return MVT::i8;
371 }
372
373 /// The type legalizer framework of generating legalizer can generate libcalls
374 /// only when the operand/result types are illegal.
375 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
376 /// For example an arithmetic right shift. These functions are used to lower
377 /// such operations that generate libcall for legal types.
378
379 void
380 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
381 const char *Name) {
382 PIC16LibcallNames[Call] = Name;
383 }
384
385 const char *
386 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
387 return PIC16LibcallNames[Call];
388 }
389
390 SDValue
391 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
392 EVT RetVT, const SDValue *Ops,
393 unsigned NumOps, bool isSigned,
394 SelectionDAG &DAG, DebugLoc dl) {
395
396 TargetLowering::ArgListTy Args;
397 Args.reserve(NumOps);
398
399 TargetLowering::ArgListEntry Entry;
400 for (unsigned i = 0; i != NumOps; ++i) {
401 Entry.Node = Ops[i];
402 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
403 Entry.isSExt = isSigned;
404 Entry.isZExt = !isSigned;
405 Args.push_back(Entry);
406 }
407
408 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
409
410 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
411 std::pair<SDValue,SDValue> CallInfo =
412 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
413 false, 0, CallingConv::C, false,
414 /*isReturnValueUsed=*/true,
415 Callee, Args, DAG, dl);
416
417 return CallInfo.first;
418 }
419
420 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
421 switch (Opcode) {
422 default: return NULL;
423 case PIC16ISD::Lo: return "PIC16ISD::Lo";
424 case PIC16ISD::Hi: return "PIC16ISD::Hi";
425 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
426 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
427 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
428 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
429 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
430 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
431 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
432 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
433 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
434 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
435 case PIC16ISD::BCF: return "PIC16ISD::BCF";
436 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
437 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
438 case PIC16ISD::RLF: return "PIC16ISD::RLF";
439 case PIC16ISD::RRF: return "PIC16ISD::RRF";
440 case PIC16ISD::CALL: return "PIC16ISD::CALL";
441 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
442 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
443 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
444 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
445 case PIC16ISD::RET: return "PIC16ISD::RET";
446 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
447 }
448 }
449
450 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
451 SmallVectorImpl<SDValue>&Results,
452 SelectionDAG &DAG) {
453
454 switch (N->getOpcode()) {
455 case ISD::GlobalAddress:
456 Results.push_back(ExpandGlobalAddress(N, DAG));
457 return;
458 case ISD::ExternalSymbol:
459 Results.push_back(ExpandExternalSymbol(N, DAG));
460 return;
461 case ISD::STORE:
462 Results.push_back(ExpandStore(N, DAG));
463 return;
464 case ISD::LOAD:
465 PopulateResults(ExpandLoad(N, DAG), Results);
466 return;
467 case ISD::ADD:
468 // Results.push_back(ExpandAdd(N, DAG));
469 return;
470 case ISD::FrameIndex:
471 Results.push_back(ExpandFrameIndex(N, DAG));
472 return;
473 default:
474 assert (0 && "not implemented");
475 return;
476 }
477 }
478
479 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
480
481 // Currently handling FrameIndex of size MVT::i16 only
482 // One example of this scenario is when return value is written on
483 // FrameIndex#0
484
485 if (N->getValueType(0) != MVT::i16)
486 return SDValue();
487
488 // Expand the FrameIndex into ExternalSymbol and a Constant node
489 // The constant will represent the frame index number
490 // Get the current function frame
491 MachineFunction &MF = DAG.getMachineFunction();
492 const Function *Func = MF.getFunction();
493 const std::string Name = Func->getName();
494
495 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
496 // FIXME there isn't really debug info here
497 DebugLoc dl = FR->getDebugLoc();
498
499 // Expand FrameIndex like GlobalAddress and ExternalSymbol
500 // Also use Offset field for lo and hi parts. The default
501 // offset is zero.
502
503 SDValue ES;
504 int FrameOffset;
505 SDValue FI = SDValue(N,0);
506 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
507 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
508 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
509 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
510 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
511 }
512
513
514 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
515 StoreSDNode *St = cast<StoreSDNode>(N);
516 SDValue Chain = St->getChain();
517 SDValue Src = St->getValue();
518 SDValue Ptr = St->getBasePtr();
519 EVT ValueType = Src.getValueType();
520 unsigned StoreOffset = 0;
521 DebugLoc dl = N->getDebugLoc();
522
523 SDValue PtrLo, PtrHi;
524 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
525
526 if (ValueType == MVT::i8) {
527 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
528 PtrLo, PtrHi,
529 DAG.getConstant (0 + StoreOffset, MVT::i8));
530 }
531 else if (ValueType == MVT::i16) {
532 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
533 SDValue SrcLo, SrcHi;
534 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
535 SDValue ChainLo = Chain, ChainHi = Chain;
536 // FIXME: This makes unsafe assumptions. The Chain may be a TokenFactor
537 // created for an unrelated purpose, in which case it may not have
538 // exactly two operands. Also, even if it does have two operands, they
539 // may not be the low and high parts of an aligned load that was split.
540 if (Chain.getOpcode() == ISD::TokenFactor) {
541 ChainLo = Chain.getOperand(0);
542 ChainHi = Chain.getOperand(1);
543 }
544 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
545 ChainLo,
546 SrcLo, PtrLo, PtrHi,
547 DAG.getConstant (0 + StoreOffset, MVT::i8));
548
549 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
550 SrcHi, PtrLo, PtrHi,
551 DAG.getConstant (1 + StoreOffset, MVT::i8));
552
553 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
554 getChain(Store2));
555 }
556 else if (ValueType == MVT::i32) {
557 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
558 SDValue SrcLo, SrcHi;
559 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
560
561 // Get the expanded parts of each of SrcLo and SrcHi.
562 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
563 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
564 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
565
566 SDValue ChainLo = Chain, ChainHi = Chain;
567 // FIXME: This makes unsafe assumptions; see the FIXME above.
568 if (Chain.getOpcode() == ISD::TokenFactor) {
569 ChainLo = Chain.getOperand(0);
570 ChainHi = Chain.getOperand(1);
571 }
572 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
573 ChainHi2 = ChainHi;
574 // FIXME: This makes unsafe assumptions; see the FIXME above.
575 if (ChainLo.getOpcode() == ISD::TokenFactor) {
576 ChainLo1 = ChainLo.getOperand(0);
577 ChainLo2 = ChainLo.getOperand(1);
578 }
579 // FIXME: This makes unsafe assumptions; see the FIXME above.
580 if (ChainHi.getOpcode() == ISD::TokenFactor) {
581 ChainHi1 = ChainHi.getOperand(0);
582 ChainHi2 = ChainHi.getOperand(1);
583 }
584 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
585 ChainLo1,
586 SrcLo1, PtrLo, PtrHi,
587 DAG.getConstant (0 + StoreOffset, MVT::i8));
588
589 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
590 SrcLo2, PtrLo, PtrHi,
591 DAG.getConstant (1 + StoreOffset, MVT::i8));
592
593 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
594 SrcHi1, PtrLo, PtrHi,
595 DAG.getConstant (2 + StoreOffset, MVT::i8));
596
597 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
598 SrcHi2, PtrLo, PtrHi,
599 DAG.getConstant (3 + StoreOffset, MVT::i8));
600
601 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
602 getChain(Store1), getChain(Store2));
603 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
604 getChain(Store3), getChain(Store4));
605 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
606
607 } else if (ValueType == MVT::i64) {
608 SDValue SrcLo, SrcHi;
609 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
610 SDValue ChainLo = Chain, ChainHi = Chain;
611 // FIXME: This makes unsafe assumptions; see the FIXME above.
612 if (Chain.getOpcode() == ISD::TokenFactor) {
613 ChainLo = Chain.getOperand(0);
614 ChainHi = Chain.getOperand(1);
615 }
616 SDValue Store1 = DAG.getStore(ChainLo, dl, SrcLo, Ptr, NULL,
617 0 + StoreOffset);
618
619 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
620 DAG.getConstant(4, Ptr.getValueType()));
621 SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
622 1 + StoreOffset);
623
624 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
625 Store2);
626 } else {
627 assert (0 && "value type not supported");
628 return SDValue();
629 }
630 }
631
632 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
633 {
634 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
635 // FIXME there isn't really debug info here
636 DebugLoc dl = ES->getDebugLoc();
637
638 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
639 SDValue Offset = DAG.getConstant(0, MVT::i8);
640 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
641 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
642
643 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
644 }
645
646 // ExpandGlobalAddress -
647 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
648 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
649 // FIXME there isn't really debug info here
650 DebugLoc dl = G->getDebugLoc();
651
652 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
653 G->getOffset());
654
655 SDValue Offset = DAG.getConstant(0, MVT::i8);
656 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
657 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
658
659 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
660 }
661
662 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
663 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
664
665 if (Op.getOpcode() == ISD::BUILD_PAIR) {
666 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
667 return true;
668 }
669 return false;
670 }
671
672 // Return true if DirectAddress is in ROM_SPACE
673 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
674
675 // RomAddress is a GlobalAddress in ROM_SPACE_
676 // If the Op is not a GlobalAddress return NULL without checking
677 // anything further.
678 if (!isDirectAddress(Op))
679 return false;
680
681 // Its a GlobalAddress.
682 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
683 SDValue TGA = Op.getOperand(0).getOperand(0);
684 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
685
686 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
687 return true;
688
689 // Any other address space return it false
690 return false;
691 }
692
693
694 // GetExpandedParts - This function is on the similiar lines as
695 // the GetExpandedInteger in type legalizer is. This returns expanded
696 // parts of Op in Lo and Hi.
697
698 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
699 SDValue &Lo, SDValue &Hi) {
700 SDNode *N = Op.getNode();
701 DebugLoc dl = N->getDebugLoc();
702 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
703
704 // Extract the lo component.
705 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
706 DAG.getConstant(0, MVT::i8));
707
708 // extract the hi component
709 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
710 DAG.getConstant(1, MVT::i8));
711 }
712
713 // Legalize FrameIndex into ExternalSymbol and offset.
714 void
715 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
716 SDValue &ES, int &Offset) {
717
718 MachineFunction &MF = DAG.getMachineFunction();
719 const Function *Func = MF.getFunction();
720 MachineFrameInfo *MFI = MF.getFrameInfo();
721 const std::string Name = Func->getName();
722
723 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
724
725 // FrameIndices are not stack offsets. But they represent the request
726 // for space on stack. That space requested may be more than one byte.
727 // Therefore, to calculate the stack offset that a FrameIndex aligns
728 // with, we need to traverse all the FrameIndices available earlier in
729 // the list and add their requested size.
730 unsigned FIndex = FR->getIndex();
731 const char *tmpName;
732 if (FIndex < ReservedFrameCount) {
733 tmpName = createESName(PAN::getFrameLabel(Name));
734 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
735 Offset = 0;
736 for (unsigned i=0; i<FIndex ; ++i) {
737 Offset += MFI->getObjectSize(i);
738 }
739 } else {
740 // FrameIndex has been made for some temporary storage
741 tmpName = createESName(PAN::getTempdataLabel(Name));
742 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
743 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
744 }
745
746 return;
747 }
748
749 // This function legalizes the PIC16 Addresses. If the Pointer is
750 // -- Direct address variable residing
751 // --> then a Banksel for that variable will be created.
752 // -- Rom variable
753 // --> then it will be treated as an indirect address.
754 // -- Indirect address
755 // --> then the address will be loaded into FSR
756 // -- ADD with constant operand
757 // --> then constant operand of ADD will be returned as Offset
758 // and non-constant operand of ADD will be treated as pointer.
759 // Returns the high and lo part of the address, and the offset(in case of ADD).
760
761 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
762 SDValue &Lo, SDValue &Hi,
763 unsigned &Offset, DebugLoc dl) {
764
765 // Offset, by default, should be 0
766 Offset = 0;
767
768 // If the pointer is ADD with constant,
769 // return the constant value as the offset
770 if (Ptr.getOpcode() == ISD::ADD) {
771 SDValue OperLeft = Ptr.getOperand(0);
772 SDValue OperRight = Ptr.getOperand(1);
773 if ((OperLeft.getOpcode() == ISD::Constant) &&
774 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
775 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
776 Ptr = OperRight;
777 } else if ((OperRight.getOpcode() == ISD::Constant) &&
778 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
779 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
780 Ptr = OperLeft;
781 }
782 }
783
784 // If the pointer is Type i8 and an external symbol
785 // then treat it as direct address.
786 // One example for such case is storing and loading
787 // from function frame during a call
788 if (Ptr.getValueType() == MVT::i8) {
789 switch (Ptr.getOpcode()) {
790 case ISD::TargetExternalSymbol:
791 Lo = Ptr;
792 Hi = DAG.getConstant(1, MVT::i8);
793 return;
794 }
795 }
796
797 // Expansion of FrameIndex has Lo/Hi parts
798 if (isDirectAddress(Ptr)) {
799 SDValue TFI = Ptr.getOperand(0).getOperand(0);
800 int FrameOffset;
801 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
802 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
803 Hi = DAG.getConstant(1, MVT::i8);
804 Offset += FrameOffset;
805 return;
806 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
807 // FrameIndex has already been expanded.
808 // Now just make use of its expansion
809 Lo = TFI;
810 Hi = DAG.getConstant(1, MVT::i8);
811 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
812 assert (FOffset.getOpcode() == ISD::Constant &&
813 "Invalid operand of PIC16ISD::Lo");
814 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
815 return;
816 }
817 }
818
819 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
820 // Direct addressing case for RAM variables. The Hi part is constant
821 // and the Lo part is the TGA itself.
822 Lo = Ptr.getOperand(0).getOperand(0);
823
824 // For direct addresses Hi is a constant. Value 1 for the constant
825 // signifies that banksel needs to generated for it. Value 0 for
826 // the constant signifies that banksel does not need to be generated
827 // for it. Mark it as 1 now and optimize later.
828 Hi = DAG.getConstant(1, MVT::i8);
829 return;
830 }
831
832 // Indirect addresses. Get the hi and lo parts of ptr.
833 GetExpandedParts(Ptr, DAG, Lo, Hi);
834
835 // Put the hi and lo parts into FSR.
836 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
837 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
838
839 return;
840 }
841
842 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
843 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
844 SDValue Chain = LD->getChain();
845 SDValue Ptr = LD->getBasePtr();
846 DebugLoc dl = LD->getDebugLoc();
847
848 SDValue Load, Offset;
849 SDVTList Tys;
850 EVT VT, NewVT;
851 SDValue PtrLo, PtrHi;
852 unsigned LoadOffset;
853
854 // Legalize direct/indirect addresses. This will give the lo and hi parts
855 // of the address and the offset.
856 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
857
858 // Load from the pointer (direct address or FSR)
859 VT = N->getValueType(0);
860 unsigned NumLoads = VT.getSizeInBits() / 8;
861 std::vector<SDValue> PICLoads;
862 unsigned iter;
863 EVT MemVT = LD->getMemoryVT();
864 if(ISD::isNON_EXTLoad(N)) {
865 for (iter=0; iter<NumLoads ; ++iter) {
866 // Add the pointer offset if any
867 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
868 Tys = DAG.getVTList(MVT::i8, MVT::Other);
869 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
870 Offset);
871 PICLoads.push_back(Load);
872 }
873 } else {
874 // If it is extended load then use PIC16Load for Memory Bytes
875 // and for all extended bytes perform action based on type of
876 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
877
878
879 // For extended loads this is the memory value type
880 // i.e. without any extension
881 EVT MemVT = LD->getMemoryVT();
882 unsigned MemBytes = MemVT.getSizeInBits() / 8;
883 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
884 // So set it to one
885 if (MemBytes == 0) MemBytes = 1;
886
887 unsigned ExtdBytes = VT.getSizeInBits() / 8;
888 Offset = DAG.getConstant(LoadOffset, MVT::i8);
889
890 Tys = DAG.getVTList(MVT::i8, MVT::Other);
891 // For MemBytes generate PIC16Load with proper offset
892 for (iter=0; iter < MemBytes; ++iter) {
893 // Add the pointer offset if any
894 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
895 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
896 Offset);
897 PICLoads.push_back(Load);
898 }
899
900 // For SignExtendedLoad
901 if (ISD::isSEXTLoad(N)) {
902 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
903 // highest MemByte
904 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
905 DAG.getConstant(7, MVT::i8));
906 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
907 PICLoads.push_back(SRA);
908 }
909 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
910 //} else if (ISD::isZEXTLoad(N)) {
911 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
912 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
913 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
914 PICLoads.push_back(ConstZero);
915 }
916 }
917 }
918 SDValue BP;
919
920 if (VT == MVT::i8) {
921 // Operand of Load is illegal -- Load itself is legal
922 return PICLoads[0];
923 }
924 else if (VT == MVT::i16) {
925 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
926 if (MemVT == MVT::i8)
927 Chain = getChain(PICLoads[0]);
928 else
929 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
930 getChain(PICLoads[0]), getChain(PICLoads[1]));
931 } else if (VT == MVT::i32) {
932 SDValue BPs[2];
933 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
934 PICLoads[0], PICLoads[1]);
935 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
936 PICLoads[2], PICLoads[3]);
937 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
938 if (MemVT == MVT::i8)
939 Chain = getChain(PICLoads[0]);
940 else if (MemVT == MVT::i16)
941 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
942 getChain(PICLoads[0]), getChain(PICLoads[1]));
943 else {
944 SDValue Chains[2];
945 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
946 getChain(PICLoads[0]), getChain(PICLoads[1]));
947 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
948 getChain(PICLoads[2]), getChain(PICLoads[3]));
949 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
950 Chains[0], Chains[1]);
951 }
952 }
953 Tys = DAG.getVTList(VT, MVT::Other);
954 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
955 }
956
957 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
958 // We should have handled larger operands in type legalizer itself.
959 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
960
961 SDNode *N = Op.getNode();
962 SDValue Value = N->getOperand(0);
963 SDValue Amt = N->getOperand(1);
964 PIC16ISD::PIC16Libcall CallCode;
965 switch (N->getOpcode()) {
966 case ISD::SRA:
967 CallCode = PIC16ISD::SRA_I8;
968 break;
969 case ISD::SHL:
970 CallCode = PIC16ISD::SLL_I8;
971 break;
972 case ISD::SRL:
973 CallCode = PIC16ISD::SRL_I8;
974 break;
975 default:
976 assert ( 0 && "This shift is not implemented yet.");
977 return SDValue();
978 }
979 SmallVector<SDValue, 2> Ops(2);
980 Ops[0] = Value;
981 Ops[1] = Amt;
982 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
983 true, DAG, N->getDebugLoc());
984 return Call;
985 }
986
987 SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
988 // We should have handled larger operands in type legalizer itself.
989 assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
990
991 SDNode *N = Op.getNode();
992 SmallVector<SDValue, 2> Ops(2);
993 Ops[0] = N->getOperand(0);
994 Ops[1] = N->getOperand(1);
995 SDValue Call = MakePIC16Libcall(PIC16ISD::MUL_I8, N->getValueType(0),
996 &Ops[0], 2, true, DAG, N->getDebugLoc());
997 return Call;
998 }
999
1000 void
1001 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
1002 SmallVectorImpl<SDValue>&Results,
1003 SelectionDAG &DAG) {
1004 SDValue Op = SDValue(N, 0);
1005 SDValue Res;
1006 unsigned i;
1007 switch (Op.getOpcode()) {
1008 case ISD::LOAD:
1009 Res = ExpandLoad(Op.getNode(), DAG); break;
1010 default: {
1011 // All other operations are handled in LowerOperation.
1012 Res = LowerOperation(Op, DAG);
1013 if (Res.getNode())
1014 Results.push_back(Res);
1015
1016 return;
1017 }
1018 }
1019
1020 N = Res.getNode();
1021 unsigned NumValues = N->getNumValues();
1022 for (i = 0; i < NumValues ; i++) {
1023 Results.push_back(SDValue(N, i));
1024 }
1025 }
1026
1027 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1028 switch (Op.getOpcode()) {
1029 case ISD::ADD:
1030 case ISD::ADDC:
1031 case ISD::ADDE:
1032 return LowerADD(Op, DAG);
1033 case ISD::SUB:
1034 case ISD::SUBC:
1035 case ISD::SUBE:
1036 return LowerSUB(Op, DAG);
1037 case ISD::LOAD:
1038 return ExpandLoad(Op.getNode(), DAG);
1039 case ISD::STORE:
1040 return ExpandStore(Op.getNode(), DAG);
1041 case ISD::MUL:
1042 return LowerMUL(Op, DAG);
1043 case ISD::SHL:
1044 case ISD::SRA:
1045 case ISD::SRL:
1046 return LowerShift(Op, DAG);
1047 case ISD::OR:
1048 case ISD::AND:
1049 case ISD::XOR:
1050 return LowerBinOp(Op, DAG);
1051 case ISD::BR_CC:
1052 return LowerBR_CC(Op, DAG);
1053 case ISD::SELECT_CC:
1054 return LowerSELECT_CC(Op, DAG);
1055 }
1056 return SDValue();
1057 }
1058
1059 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1060 SelectionDAG &DAG,
1061 DebugLoc dl) {
1062 assert (Op.getValueType() == MVT::i8
1063 && "illegal value type to store on stack.");
1064
1065 MachineFunction &MF = DAG.getMachineFunction();
1066 const Function *Func = MF.getFunction();
1067 const std::string FuncName = Func->getName();
1068
1069
1070 // Put the value on stack.
1071 // Get a stack slot index and convert to es.
1072 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
1073 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1074 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1075
1076 // Store the value to ES.
1077 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1078 DAG.getEntryNode(),
1079 Op, ES,
1080 DAG.getConstant (1, MVT::i8), // Banksel.
1081 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1082 MVT::i8));
1083
1084 // Load the value from ES.
1085 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1086 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1087 ES, DAG.getConstant (1, MVT::i8),
1088 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1089 MVT::i8));
1090
1091 return Load.getValue(0);
1092 }
1093
1094 SDValue PIC16TargetLowering::
1095 LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
1096 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1097 const SmallVectorImpl<ISD::OutputArg> &Outs,
1098 const SmallVectorImpl<ISD::InputArg> &Ins,
1099 DebugLoc dl, SelectionDAG &DAG) {
1100 unsigned NumOps = Outs.size();
1101
1102 // If call has no arguments then do nothing and return.
1103 if (NumOps == 0)
1104 return Chain;
1105
1106 std::vector<SDValue> Ops;
1107 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1108 SDValue Arg, StoreRet;
1109
1110 // For PIC16 ABI the arguments come after the return value.
1111 unsigned RetVals = Ins.size();
1112 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1113 // Get the arguments
1114 Arg = Outs[i].Val;
1115
1116 Ops.clear();
1117 Ops.push_back(Chain);
1118 Ops.push_back(Arg);
1119 Ops.push_back(DataAddr_Lo);
1120 Ops.push_back(DataAddr_Hi);
1121 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1122 Ops.push_back(InFlag);
1123
1124 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1125
1126 Chain = getChain(StoreRet);
1127 InFlag = getOutFlag(StoreRet);
1128 ArgOffset++;
1129 }
1130 return Chain;
1131 }
1132
1133 SDValue PIC16TargetLowering::
1134 LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
1135 const SmallVectorImpl<ISD::OutputArg> &Outs,
1136 DebugLoc dl, SelectionDAG &DAG) {
1137 unsigned NumOps = Outs.size();
1138 std::string Name;
1139 SDValue Arg, StoreAt;
1140 EVT ArgVT;
1141 unsigned Size=0;
1142
1143 // If call has no arguments then do nothing and return.
1144 if (NumOps == 0)
1145 return Chain;
1146
1147 // FIXME: This portion of code currently assumes only
1148 // primitive types being passed as arguments.
1149
1150 // Legalize the address before use
1151 SDValue PtrLo, PtrHi;
1152 unsigned AddressOffset;
1153 int StoreOffset = 0;
1154 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1155 SDValue StoreRet;
1156
1157 std::vector<SDValue> Ops;
1158 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1159 for (unsigned i=0, Offset = 0; i<NumOps; i++) {
1160 // Get the argument
1161 Arg = Outs[i].Val;
1162 StoreOffset = (Offset + AddressOffset);
1163
1164 // Store the argument on frame
1165
1166 Ops.clear();
1167 Ops.push_back(Chain);
1168 Ops.push_back(Arg);
1169 Ops.push_back(PtrLo);
1170 Ops.push_back(PtrHi);
1171 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1172 Ops.push_back(InFlag);
1173
1174 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1175
1176 Chain = getChain(StoreRet);
1177 InFlag = getOutFlag(StoreRet);
1178
1179 // Update the frame offset to be used for next argument
1180 ArgVT = Arg.getValueType();
1181 Size = ArgVT.getSizeInBits();
1182 Size = Size/8; // Calculate size in bytes
1183 Offset += Size; // Increase the frame offset
1184 }
1185 return Chain;
1186 }
1187
1188 SDValue PIC16TargetLowering::
1189 LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
1190 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1191 const SmallVectorImpl<ISD::InputArg> &Ins,
1192 DebugLoc dl, SelectionDAG &DAG,
1193 SmallVectorImpl<SDValue> &InVals) {
1194 unsigned RetVals = Ins.size();
1195
1196 // If call does not have anything to return
1197 // then do nothing and go back.
1198 if (RetVals == 0)
1199 return Chain;
1200
1201 // Call has something to return
1202 SDValue LoadRet;
1203
1204 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1205 for(unsigned i=0;i<RetVals;i++) {
1206 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1207 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1208 InFlag);
1209 InFlag = getOutFlag(LoadRet);
1210 Chain = getChain(LoadRet);
1211 InVals.push_back(LoadRet);
1212 }
1213 return Chain;
1214 }
1215
1216 SDValue PIC16TargetLowering::
1217 LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
1218 const SmallVectorImpl<ISD::InputArg> &Ins,
1219 DebugLoc dl, SelectionDAG &DAG,
1220 SmallVectorImpl<SDValue> &InVals) {
1221
1222 // Currently handling primitive types only. They will come in
1223 // i8 parts
1224 unsigned RetVals = Ins.size();
1225
1226 // Return immediately if the return type is void
1227 if (RetVals == 0)
1228 return Chain;
1229
1230 // Call has something to return
1231
1232 // Legalize the address before use
1233 SDValue LdLo, LdHi;
1234 unsigned LdOffset;
1235 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1236
1237 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1238 SDValue LoadRet;
1239
1240 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1241
1242 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1243 DAG.getConstant(LdOffset + Offset, MVT::i8),
1244 InFlag);
1245
1246 InFlag = getOutFlag(LoadRet);
1247
1248 Chain = getChain(LoadRet);
1249 Offset++;
1250 InVals.push_back(LoadRet);
1251 }
1252
1253 return Chain;
1254 }
1255
1256 SDValue
1257 PIC16TargetLowering::LowerReturn(SDValue Chain,
1258 CallingConv::ID CallConv, bool isVarArg,
1259 const SmallVectorImpl<ISD::OutputArg> &Outs,
1260 DebugLoc dl, SelectionDAG &DAG) {
1261
1262 // Number of values to return
1263 unsigned NumRet = Outs.size();
1264
1265 // Function returns value always on stack with the offset starting
1266 // from 0
1267 MachineFunction &MF = DAG.getMachineFunction();
1268 const Function *F = MF.getFunction();
1269 std::string FuncName = F->getName();
1270
1271 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1272 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1273 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1274 SDValue BS = DAG.getConstant(1, MVT::i8);
1275 SDValue RetVal;
1276 for(unsigned i=0;i<NumRet; ++i) {
1277 RetVal = Outs[i].Val;
1278 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1279 ES, BS,
1280 DAG.getConstant (i, MVT::i8));
1281
1282 }
1283 return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain);
1284 }
1285
1286 void PIC16TargetLowering::
1287 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1288 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1289 SelectionDAG &DAG) {
1290 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1291 && "Don't know what to do of such callee!!");
1292 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1293 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1294 Chain = getChain(SeqStart);
1295 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1296
1297 // Get the Lo and Hi part of code address
1298 SDValue Lo = Callee.getOperand(0);
1299 SDValue Hi = Callee.getOperand(1);
1300
1301 SDValue Data_Lo, Data_Hi;
1302 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1303 // Subtract 2 from Address to get the Lower part of DataAddress.
1304 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1305 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1306 DAG.getConstant(2, MVT::i8));
1307 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1308 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1309 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1310 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1311 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1312 OperFlag);
1313 Chain = getChain(Call);
1314 OperFlag = getOutFlag(Call);
1315 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1316 OperFlag);
1317 Chain = getChain(SeqEnd);
1318 OperFlag = getOutFlag(SeqEnd);
1319
1320 // Low part of Data Address
1321 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1322
1323 // Make the second call.
1324 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1325 Chain = getChain(SeqStart);
1326 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1327
1328 // Subtract 1 from Address to get high part of data address.
1329 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1330 DAG.getConstant(1, MVT::i8));
1331 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1332 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1333 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1334
1335 // Use new Lo to make another CALLW
1336 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1337 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1338 Chain = getChain(Call);
1339 OperFlag = getOutFlag(Call);
1340 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1341 OperFlag);
1342 Chain = getChain(SeqEnd);
1343 OperFlag = getOutFlag(SeqEnd);
1344 // Hi part of Data Address
1345 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1346 }
1347
1348 SDValue
1349 PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1350 CallingConv::ID CallConv, bool isVarArg,
1351 bool isTailCall,
1352 const SmallVectorImpl<ISD::OutputArg> &Outs,
1353 const SmallVectorImpl<ISD::InputArg> &Ins,
1354 DebugLoc dl, SelectionDAG &DAG,
1355 SmallVectorImpl<SDValue> &InVals) {
1356
1357 assert(Callee.getValueType() == MVT::i16 &&
1358 "Don't know how to legalize this call node!!!");
1359
1360 // The flag to track if this is a direct or indirect call.
1361 bool IsDirectCall = true;
1362 unsigned RetVals = Ins.size();
1363 unsigned NumArgs = Outs.size();
1364
1365 SDValue DataAddr_Lo, DataAddr_Hi;
1366 if (!isa<GlobalAddressSDNode>(Callee) &&
1367 !isa<ExternalSymbolSDNode>(Callee)) {
1368 IsDirectCall = false; // This is indirect call
1369
1370 // If this is an indirect call then to pass the arguments
1371 // and read the return value back, we need the data address
1372 // of the function being called.
1373 // To get the data address two more calls need to be made.
1374
1375 // Come here for indirect calls
1376 SDValue Lo, Hi;
1377 // Indirect addresses. Get the hi and lo parts of ptr.
1378 GetExpandedParts(Callee, DAG, Lo, Hi);
1379 // Connect Lo and Hi parts of the callee with the PIC16Connect
1380 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1381
1382 // Read DataAddress only if we have to pass arguments or
1383 // read return value.
1384 if ((RetVals > 0) || (NumArgs > 0))
1385 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1386 }
1387
1388 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1389
1390 // Start the call sequence.
1391 // Carring the Constant 0 along the CALLSEQSTART
1392 // because there is nothing else to carry.
1393 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1394 Chain = getChain(SeqStart);
1395 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1396 std::string Name;
1397
1398 // For any direct call - callee will be GlobalAddressNode or
1399 // ExternalSymbol
1400 SDValue ArgLabel, RetLabel;
1401 if (IsDirectCall) {
1402 // Considering the GlobalAddressNode case here.
1403 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1404 GlobalValue *GV = G->getGlobal();
1405 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1406 Name = G->getGlobal()->getName();
1407 } else {// Considering the ExternalSymbol case here
1408 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1409 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1410 Name = ES->getSymbol();
1411 }
1412
1413 // Label for argument passing
1414 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1415 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1416
1417 // Label for reading return value
1418 const char *retName = createESName(PAN::getRetvalLabel(Name));
1419 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1420 } else {
1421 // if indirect call
1422 SDValue CodeAddr_Lo = Callee.getOperand(0);
1423 SDValue CodeAddr_Hi = Callee.getOperand(1);
1424
1425 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1426 DAG.getConstant(2, MVT::i8));*/
1427
1428 // move Hi part in PCLATH
1429 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1430 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1431 CodeAddr_Hi);
1432 }
1433
1434 // Pass the argument to function before making the call.
1435 SDValue CallArgs;
1436 if (IsDirectCall) {
1437 CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
1438 Outs, dl, DAG);
1439 Chain = getChain(CallArgs);
1440 OperFlag = getOutFlag(CallArgs);
1441 } else {
1442 CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
1443 DataAddr_Hi, Outs, Ins, dl, DAG);
1444 Chain = getChain(CallArgs);
1445 OperFlag = getOutFlag(CallArgs);
1446 }
1447
1448 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1449 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1450 OperFlag);
1451 Chain = getChain(PICCall);
1452 OperFlag = getOutFlag(PICCall);
1453
1454
1455 // Carrying the Constant 0 along the CALLSEQSTART
1456 // because there is nothing else to carry.
1457 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1458 OperFlag);
1459 Chain = getChain(SeqEnd);
1460 OperFlag = getOutFlag(SeqEnd);
1461
1462 // Lower the return value reading after the call.
1463 if (IsDirectCall)
1464 return LowerDirectCallReturn(RetLabel, Chain, OperFlag,
1465 Ins, dl, DAG, InVals);
1466 else
1467 return LowerIndirectCallReturn(Chain, OperFlag, DataAddr_Lo,
1468 DataAddr_Hi, Ins, dl, DAG, InVals);
1469 }
1470
1471 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1472 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1473 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1474 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1475 return true;
1476 return false;
1477 }
1478
1479 // NeedToConvertToMemOp - Returns true if one of the operands of the
1480 // operation 'Op' needs to be put into memory. Also returns the
1481 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1482 // no instruction that can operation on two registers. Most insns take
1483 // one register and one memory operand (addwf) / Constant (addlw).
1484 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1485 // If one of the operand is a constant, return false.
1486 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1487 Op.getOperand(1).getOpcode() == ISD::Constant)
1488 return false;
1489
1490 // Return false if one of the operands is already a direct
1491 // load and that operand has only one use.
1492 if (isDirectLoad(Op.getOperand(0))) {
1493 if (Op.getOperand(0).hasOneUse())
1494 return false;
1495 else
1496 MemOp = 0;
1497 }
1498 if (isDirectLoad(Op.getOperand(1))) {
1499 if (Op.getOperand(1).hasOneUse())
1500 return false;
1501 else
1502 MemOp = 1;
1503 }
1504 return true;
1505 }
1506
1507 // LowerBinOp - Lower a commutative binary operation that does not
1508 // affect status flag carry.
1509 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1510 DebugLoc dl = Op.getDebugLoc();
1511
1512 // We should have handled larger operands in type legalizer itself.
1513 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1514
1515 unsigned MemOp = 1;
1516 if (NeedToConvertToMemOp(Op, MemOp)) {
1517 // Put one value on stack.
1518 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1519
1520 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1521 NewVal);
1522 }
1523 else {
1524 return Op;
1525 }
1526 }
1527
1528 // LowerADD - Lower all types of ADD operations including the ones
1529 // that affects carry.
1530 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1531 // We should have handled larger operands in type legalizer itself.
1532 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1533 DebugLoc dl = Op.getDebugLoc();
1534 unsigned MemOp = 1;
1535 if (NeedToConvertToMemOp(Op, MemOp)) {
1536 // Put one value on stack.
1537 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1538
1539 // ADDC and ADDE produce two results.
1540 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1541
1542 // ADDE has three operands, the last one is the carry bit.
1543 if (Op.getOpcode() == ISD::ADDE)
1544 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1545 NewVal, Op.getOperand(2));
1546 // ADDC has two operands.
1547 else if (Op.getOpcode() == ISD::ADDC)
1548 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1549 NewVal);
1550 // ADD it is. It produces only one result.
1551 else
1552 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1553 NewVal);
1554 }
1555 else
1556 return Op;
1557 }
1558
1559 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1560 DebugLoc dl = Op.getDebugLoc();
1561 // We should have handled larger operands in type legalizer itself.
1562 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1563
1564 // Nothing to do if the first operand is already a direct load and it has
1565 // only one use.
1566 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1567 return Op;
1568
1569 // Put first operand on stack.
1570 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1571
1572 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1573 switch (Op.getOpcode()) {
1574 default:
1575 assert (0 && "Opcode unknown.");
1576 case ISD::SUBE:
1577 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1578 Op.getOperand(2));
1579 break;
1580 case ISD::SUBC:
1581 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1582 break;
1583 case ISD::SUB:
1584 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
1585 break;
1586 }
1587 }
1588
1589 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1590 unsigned NumArgs = F->arg_size();
1591
1592 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1593
1594 if (isVoidFunc)
1595 ReservedFrameCount = NumArgs;
1596 else
1597 ReservedFrameCount = NumArgs + 1;
1598 }
1599
1600 // LowerFormalArguments - Argument values are loaded from the
1601 // <fname>.args + offset. All arguments are already broken to leaglized
1602 // types, so the offset just runs from 0 to NumArgVals - 1.
1603
1604 SDValue
1605 PIC16TargetLowering::LowerFormalArguments(SDValue Chain,
1606 CallingConv::ID CallConv,
1607 bool isVarArg,
1608 const SmallVectorImpl<ISD::InputArg> &Ins,
1609 DebugLoc dl,
1610 SelectionDAG &DAG,
1611 SmallVectorImpl<SDValue> &InVals) {
1612 unsigned NumArgVals = Ins.size();
1613
1614 // Get the callee's name to create the <fname>.args label to pass args.
1615 MachineFunction &MF = DAG.getMachineFunction();
1616 const Function *F = MF.getFunction();
1617 std::string FuncName = F->getName();
1618
1619 // Reset the map of FI and TmpOffset
1620 ResetTmpOffsetMap();
1621 // Initialize the ReserveFrameCount
1622 InitReservedFrameCount(F);
1623
1624 // Create the <fname>.args external symbol.
1625 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1626 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1627
1628 // Load arg values from the label + offset.
1629 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1630 SDValue BS = DAG.getConstant(1, MVT::i8);
1631 for (unsigned i = 0; i < NumArgVals ; ++i) {
1632 SDValue Offset = DAG.getConstant(i, MVT::i8);
1633 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1634 Offset);
1635 Chain = getChain(PICLoad);
1636 InVals.push_back(PICLoad);
1637 }
1638
1639 return Chain;
1640 }
1641
1642 // Perform DAGCombine of PIC16Load.
1643 // FIXME - Need a more elaborate comment here.
1644 SDValue PIC16TargetLowering::
1645 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1646 SelectionDAG &DAG = DCI.DAG;
1647 SDValue Chain = N->getOperand(0);
1648 if (N->hasNUsesOfValue(0, 0)) {
1649 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1650 }
1651 return SDValue();
1652 }
1653
1654 // For all the functions with arguments some STORE nodes are generated
1655 // that store the argument on the frameindex. However in PIC16 the arguments
1656 // are passed on stack only. Therefore these STORE nodes are redundant.
1657 // To remove these STORE nodes will be removed in PerformStoreCombine
1658 //
1659 // Currently this function is doint nothing and will be updated for removing
1660 // unwanted store operations
1661 SDValue PIC16TargetLowering::
1662 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1663 return SDValue(N, 0);
1664 /*
1665 // Storing an undef value is of no use, so remove it
1666 if (isStoringUndef(N, Chain, DAG)) {
1667 return Chain; // remove the store and return the chain
1668 }
1669 //else everything is ok.
1670 return SDValue(N, 0);
1671 */
1672 }
1673
1674 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1675 DAGCombinerInfo &DCI) const {
1676 switch (N->getOpcode()) {
1677 case ISD::STORE:
1678 return PerformStoreCombine(N, DCI);
1679 case PIC16ISD::PIC16Load:
1680 return PerformPIC16LoadCombine(N, DCI);
1681 }
1682 return SDValue();
1683 }
1684
1685 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1686 switch (CC) {
1687 default: llvm_unreachable("Unknown condition code!");
1688 case ISD::SETNE: return PIC16CC::NE;
1689 case ISD::SETEQ: return PIC16CC::EQ;
1690 case ISD::SETGT: return PIC16CC::GT;
1691 case ISD::SETGE: return PIC16CC::GE;
1692 case ISD::SETLT: return PIC16CC::LT;
1693 case ISD::SETLE: return PIC16CC::LE;
1694 case ISD::SETULT: return PIC16CC::ULT;
1695 case ISD::SETULE: return PIC16CC::ULE;
1696 case ISD::SETUGE: return PIC16CC::UGE;
1697 case ISD::SETUGT: return PIC16CC::UGT;
1698 }
1699 }
1700
1701 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1702 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1703 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1704 ISD::CondCode CC, unsigned &SPCC) {
1705 if (isa<ConstantSDNode>(RHS) &&
1706 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1707 CC == ISD::SETNE &&
1708 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1709 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1710 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1711 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1712 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1713 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1714 SDValue CMPCC = LHS.getOperand(3);
1715 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1716 LHS = CMPCC.getOperand(0);
1717 RHS = CMPCC.getOperand(1);
1718 }
1719 }
1720
1721 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1722 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1723 unsigned CC, SDValue &PIC16CC,
1724 SelectionDAG &DAG, DebugLoc dl) {
1725 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1726
1727 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1728 // i.e. a < 12 can be rewritten as 12 > a.
1729 if (RHS.getOpcode() == ISD::Constant) {
1730
1731 SDValue Tmp = LHS;
1732 LHS = RHS;
1733 RHS = Tmp;
1734
1735 switch (CondCode) {
1736 default: break;
1737 case PIC16CC::LT:
1738 CondCode = PIC16CC::GT;
1739 break;
1740 case PIC16CC::GT:
1741 CondCode = PIC16CC::LT;
1742 break;
1743 case PIC16CC::ULT:
1744 CondCode = PIC16CC::UGT;
1745 break;
1746 case PIC16CC::UGT:
1747 CondCode = PIC16CC::ULT;
1748 break;
1749 case PIC16CC::GE:
1750 CondCode = PIC16CC::LE;
1751 break;
1752 case PIC16CC::LE:
1753 CondCode = PIC16CC::GE;
1754 break;
1755 case PIC16CC::ULE:
1756 CondCode = PIC16CC::UGE;
1757 break;
1758 case PIC16CC::UGE:
1759 CondCode = PIC16CC::ULE;
1760 break;
1761 }
1762 }
1763
1764 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1765
1766 // These are signed comparisons.
1767 SDValue Mask = DAG.getConstant(128, MVT::i8);
1768 if (isSignedComparison(CondCode)) {
1769 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1770 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1771 }
1772
1773 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1774 // We can use a subtract operation to set the condition codes. But
1775 // we need to put one operand in memory if required.
1776 // Nothing to do if the first operand is already a valid type (direct load
1777 // for subwf and literal for sublw) and it is used by this operation only.
1778 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1779 && LHS.hasOneUse())
1780 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1781
1782 // else convert the first operand to mem.
1783 LHS = ConvertToMemOperand (LHS, DAG, dl);
1784 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1785 }
1786
1787
1788 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1789 SDValue LHS = Op.getOperand(0);
1790 SDValue RHS = Op.getOperand(1);
1791 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1792 SDValue TrueVal = Op.getOperand(2);
1793 SDValue FalseVal = Op.getOperand(3);
1794 unsigned ORIGCC = ~0;
1795 DebugLoc dl = Op.getDebugLoc();
1796
1797 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1798 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1799 // i.e.
1800 // A setcc: lhs, rhs, cc is expanded by llvm to
1801 // select_cc: result of setcc, 0, 1, 0, setne
1802 // We can think of it as:
1803 // select_cc: lhs, rhs, 1, 0, cc
1804 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1805 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1806
1807 SDValue PIC16CC;
1808 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1809
1810 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1811 FalseVal, PIC16CC, Cmp.getValue(1));
1812 }
1813
1814 MachineBasicBlock *
1815 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1816 MachineBasicBlock *BB) const {
1817 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1818 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1819 DebugLoc dl = MI->getDebugLoc();
1820
1821 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1822 // control-flow pattern. The incoming instruction knows the destination vreg
1823 // to set, the condition code register to branch on, the true/false values to
1824 // select between, and a branch opcode to use.
1825 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1826 MachineFunction::iterator It = BB;
1827 ++It;
1828
1829 // thisMBB:
1830 // ...
1831 // TrueVal = ...
1832 // [f]bCC copy1MBB
1833 // fallthrough --> copy0MBB
1834 MachineBasicBlock *thisMBB = BB;
1835 MachineFunction *F = BB->getParent();
1836 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1837 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1838 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1839 F->insert(It, copy0MBB);
1840 F->insert(It, sinkMBB);
1841
1842 // Update machine-CFG edges by transferring all successors of the current
1843 // block to the new block which will contain the Phi node for the select.
1844 sinkMBB->transferSuccessors(BB);
1845 // Next, add the true and fallthrough blocks as its successors.
1846 BB->addSuccessor(copy0MBB);
1847 BB->addSuccessor(sinkMBB);
1848
1849 // copy0MBB:
1850 // %FalseValue = ...
1851 // # fallthrough to sinkMBB
1852 BB = copy0MBB;
1853
1854 // Update machine-CFG edges
1855 BB->addSuccessor(sinkMBB);
1856
1857 // sinkMBB:
1858 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1859 // ...
1860 BB = sinkMBB;
1861 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1862 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1863 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1864
1865 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1866 return BB;
1867 }
1868
1869
1870 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1871 SDValue Chain = Op.getOperand(0);
1872 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1873 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1874 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1875 SDValue Dest = Op.getOperand(4); // BB to jump to
1876 unsigned ORIGCC = ~0;
1877 DebugLoc dl = Op.getDebugLoc();
1878
1879 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1880 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1881 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1882 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1883
1884 // Get the Compare insn and condition code.
1885 SDValue PIC16CC;
1886 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1887
1888 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,
1889 Cmp.getValue(1));
1890 }
1891
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