this is failing on linux hosts, force a triple.
[llvm/avr.git] / lib / Target / PowerPC / PPCISelDAGToDAG.cpp
blob356ca32830e7b0cc8b8fa9443264b43cab6bbb80
1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
16 #include "PPC.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 using namespace llvm;
39 namespace {
40 //===--------------------------------------------------------------------===//
41 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
42 /// instructions for SelectionDAG operations.
43 ///
44 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
45 PPCTargetMachine &TM;
46 PPCTargetLowering &PPCLowering;
47 const PPCSubtarget &PPCSubTarget;
48 unsigned GlobalBaseReg;
49 public:
50 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
51 : SelectionDAGISel(tm), TM(tm),
52 PPCLowering(*TM.getTargetLowering()),
53 PPCSubTarget(*TM.getSubtargetImpl()) {}
55 virtual bool runOnMachineFunction(MachineFunction &MF) {
56 // Make sure we re-emit a set of the global base reg if necessary
57 GlobalBaseReg = 0;
58 SelectionDAGISel::runOnMachineFunction(MF);
60 InsertVRSaveCode(MF);
61 return true;
64 /// getI32Imm - Return a target constant with the specified value, of type
65 /// i32.
66 inline SDValue getI32Imm(unsigned Imm) {
67 return CurDAG->getTargetConstant(Imm, MVT::i32);
70 /// getI64Imm - Return a target constant with the specified value, of type
71 /// i64.
72 inline SDValue getI64Imm(uint64_t Imm) {
73 return CurDAG->getTargetConstant(Imm, MVT::i64);
76 /// getSmallIPtrImm - Return a target constant of pointer type.
77 inline SDValue getSmallIPtrImm(unsigned Imm) {
78 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
81 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
82 /// with any number of 0s on either side. The 1s are allowed to wrap from
83 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
84 /// 0x0F0F0000 is not, since all 1s are not contiguous.
85 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
88 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
89 /// rotate and mask opcode and mask operation.
90 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
91 unsigned &SH, unsigned &MB, unsigned &ME);
93 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
94 /// base register. Return the virtual register that holds this value.
95 SDNode *getGlobalBaseReg();
97 // Select - Convert the specified operand from a target-independent to a
98 // target-specific node if it hasn't already been changed.
99 SDNode *Select(SDValue Op);
101 SDNode *SelectBitfieldInsert(SDNode *N);
103 /// SelectCC - Select a comparison of the specified values with the
104 /// specified condition code, returning the CR# of the expression.
105 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
107 /// SelectAddrImm - Returns true if the address N can be represented by
108 /// a base register plus a signed 16-bit displacement [r+imm].
109 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
110 SDValue &Base) {
111 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
114 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
115 /// immediate field. Because preinc imms have already been validated, just
116 /// accept it.
117 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
118 Out = N;
119 return true;
122 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
123 /// represented as an indexed [r+r] operation. Returns false if it can
124 /// be represented by [r+imm], which are preferred.
125 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
126 SDValue &Index) {
127 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
130 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
131 /// represented as an indexed [r+r] operation.
132 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
133 SDValue &Index) {
134 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
137 /// SelectAddrImmShift - Returns true if the address N can be represented by
138 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
139 /// for use by STD and friends.
140 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
141 SDValue &Base) {
142 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
145 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
146 /// inline asm expressions. It is always correct to compute the value into
147 /// a register. The case of adding a (possibly relocatable) constant to a
148 /// register can be improved, but it is wrong to substitute Reg+Reg for
149 /// Reg in an asm, because the load or store opcode would have to change.
150 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
151 char ConstraintCode,
152 std::vector<SDValue> &OutOps) {
153 OutOps.push_back(Op);
154 return false;
157 SDValue BuildSDIVSequence(SDNode *N);
158 SDValue BuildUDIVSequence(SDNode *N);
160 /// InstructionSelect - This callback is invoked by
161 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
162 virtual void InstructionSelect();
164 void InsertVRSaveCode(MachineFunction &MF);
166 virtual const char *getPassName() const {
167 return "PowerPC DAG->DAG Pattern Instruction Selection";
170 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
171 /// this target when scheduling the DAG.
172 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
173 // Should use subtarget info to pick the right hazard recognizer. For
174 // now, always return a PPC970 recognizer.
175 const TargetInstrInfo *II = TM.getInstrInfo();
176 assert(II && "No InstrInfo?");
177 return new PPCHazardRecognizer970(*II);
180 // Include the pieces autogenerated from the target description.
181 #include "PPCGenDAGISel.inc"
183 private:
184 SDNode *SelectSETCC(SDValue Op);
188 /// InstructionSelect - This callback is invoked by
189 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
190 void PPCDAGToDAGISel::InstructionSelect() {
191 DEBUG(BB->dump());
193 // Select target instructions for the DAG.
194 SelectRoot(*CurDAG);
195 CurDAG->RemoveDeadNodes();
198 /// InsertVRSaveCode - Once the entire function has been instruction selected,
199 /// all virtual registers are created and all machine instructions are built,
200 /// check to see if we need to save/restore VRSAVE. If so, do it.
201 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
202 // Check to see if this function uses vector registers, which means we have to
203 // save and restore the VRSAVE register and update it with the regs we use.
205 // In this case, there will be virtual registers of vector type type created
206 // by the scheduler. Detect them now.
207 bool HasVectorVReg = false;
208 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
209 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
210 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
211 HasVectorVReg = true;
212 break;
214 if (!HasVectorVReg) return; // nothing to do.
216 // If we have a vector register, we want to emit code into the entry and exit
217 // blocks to save and restore the VRSAVE register. We do this here (instead
218 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
220 // 1. This (trivially) reduces the load on the register allocator, by not
221 // having to represent the live range of the VRSAVE register.
222 // 2. This (more significantly) allows us to create a temporary virtual
223 // register to hold the saved VRSAVE value, allowing this temporary to be
224 // register allocated, instead of forcing it to be spilled to the stack.
226 // Create two vregs - one to hold the VRSAVE register that is live-in to the
227 // function and one for the value after having bits or'd into it.
228 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
229 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
231 const TargetInstrInfo &TII = *TM.getInstrInfo();
232 MachineBasicBlock &EntryBB = *Fn.begin();
233 DebugLoc dl = DebugLoc::getUnknownLoc();
234 // Emit the following code into the entry block:
235 // InVRSAVE = MFVRSAVE
236 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
237 // MTVRSAVE UpdatedVRSAVE
238 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
239 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
240 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
241 UpdatedVRSAVE).addReg(InVRSAVE);
242 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
244 // Find all return blocks, outputting a restore in each epilog.
245 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
246 if (!BB->empty() && BB->back().getDesc().isReturn()) {
247 IP = BB->end(); --IP;
249 // Skip over all terminator instructions, which are part of the return
250 // sequence.
251 MachineBasicBlock::iterator I2 = IP;
252 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
253 IP = I2;
255 // Emit: MTVRSAVE InVRSave
256 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
262 /// getGlobalBaseReg - Output the instructions required to put the
263 /// base address to use for accessing globals into a register.
265 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
266 if (!GlobalBaseReg) {
267 const TargetInstrInfo &TII = *TM.getInstrInfo();
268 // Insert the set of GlobalBaseReg into the first MBB of the function
269 MachineBasicBlock &FirstMBB = MF->front();
270 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
271 DebugLoc dl = DebugLoc::getUnknownLoc();
273 if (PPCLowering.getPointerTy() == MVT::i32) {
274 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
275 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
276 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
277 } else {
278 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
279 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
280 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
283 return CurDAG->getRegister(GlobalBaseReg,
284 PPCLowering.getPointerTy()).getNode();
287 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
288 /// or 64-bit immediate, and if the value can be accurately represented as a
289 /// sign extension from a 16-bit value. If so, this returns true and the
290 /// immediate.
291 static bool isIntS16Immediate(SDNode *N, short &Imm) {
292 if (N->getOpcode() != ISD::Constant)
293 return false;
295 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
296 if (N->getValueType(0) == MVT::i32)
297 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
298 else
299 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
302 static bool isIntS16Immediate(SDValue Op, short &Imm) {
303 return isIntS16Immediate(Op.getNode(), Imm);
307 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
308 /// operand. If so Imm will receive the 32-bit value.
309 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
311 Imm = cast<ConstantSDNode>(N)->getZExtValue();
312 return true;
314 return false;
317 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
318 /// operand. If so Imm will receive the 64-bit value.
319 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
320 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
321 Imm = cast<ConstantSDNode>(N)->getZExtValue();
322 return true;
324 return false;
327 // isInt32Immediate - This method tests to see if a constant operand.
328 // If so Imm will receive the 32 bit value.
329 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
330 return isInt32Immediate(N.getNode(), Imm);
334 // isOpcWithIntImmediate - This method tests to see if the node is a specific
335 // opcode and that it has a immediate integer right operand.
336 // If so Imm will receive the 32 bit value.
337 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
338 return N->getOpcode() == Opc
339 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
342 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
343 if (isShiftedMask_32(Val)) {
344 // look for the first non-zero bit
345 MB = CountLeadingZeros_32(Val);
346 // look for the first zero bit after the run of ones
347 ME = CountLeadingZeros_32((Val - 1) ^ Val);
348 return true;
349 } else {
350 Val = ~Val; // invert mask
351 if (isShiftedMask_32(Val)) {
352 // effectively look for the first zero bit
353 ME = CountLeadingZeros_32(Val) - 1;
354 // effectively look for the first one bit after the run of zeros
355 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
356 return true;
359 // no run present
360 return false;
363 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
364 bool IsShiftMask, unsigned &SH,
365 unsigned &MB, unsigned &ME) {
366 // Don't even go down this path for i64, since different logic will be
367 // necessary for rldicl/rldicr/rldimi.
368 if (N->getValueType(0) != MVT::i32)
369 return false;
371 unsigned Shift = 32;
372 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
373 unsigned Opcode = N->getOpcode();
374 if (N->getNumOperands() != 2 ||
375 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
376 return false;
378 if (Opcode == ISD::SHL) {
379 // apply shift left to mask if it comes first
380 if (IsShiftMask) Mask = Mask << Shift;
381 // determine which bits are made indeterminant by shift
382 Indeterminant = ~(0xFFFFFFFFu << Shift);
383 } else if (Opcode == ISD::SRL) {
384 // apply shift right to mask if it comes first
385 if (IsShiftMask) Mask = Mask >> Shift;
386 // determine which bits are made indeterminant by shift
387 Indeterminant = ~(0xFFFFFFFFu >> Shift);
388 // adjust for the left rotate
389 Shift = 32 - Shift;
390 } else if (Opcode == ISD::ROTL) {
391 Indeterminant = 0;
392 } else {
393 return false;
396 // if the mask doesn't intersect any Indeterminant bits
397 if (Mask && !(Mask & Indeterminant)) {
398 SH = Shift & 31;
399 // make sure the mask is still a mask (wrap arounds may not be)
400 return isRunOfOnes(Mask, MB, ME);
402 return false;
405 /// SelectBitfieldInsert - turn an or of two masked values into
406 /// the rotate left word immediate then mask insert (rlwimi) instruction.
407 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
408 SDValue Op0 = N->getOperand(0);
409 SDValue Op1 = N->getOperand(1);
410 DebugLoc dl = N->getDebugLoc();
412 APInt LKZ, LKO, RKZ, RKO;
413 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
414 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
416 unsigned TargetMask = LKZ.getZExtValue();
417 unsigned InsertMask = RKZ.getZExtValue();
419 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
420 unsigned Op0Opc = Op0.getOpcode();
421 unsigned Op1Opc = Op1.getOpcode();
422 unsigned Value, SH = 0;
423 TargetMask = ~TargetMask;
424 InsertMask = ~InsertMask;
426 // If the LHS has a foldable shift and the RHS does not, then swap it to the
427 // RHS so that we can fold the shift into the insert.
428 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
429 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
430 Op0.getOperand(0).getOpcode() == ISD::SRL) {
431 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
432 Op1.getOperand(0).getOpcode() != ISD::SRL) {
433 std::swap(Op0, Op1);
434 std::swap(Op0Opc, Op1Opc);
435 std::swap(TargetMask, InsertMask);
438 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
439 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
440 Op1.getOperand(0).getOpcode() != ISD::SRL) {
441 std::swap(Op0, Op1);
442 std::swap(Op0Opc, Op1Opc);
443 std::swap(TargetMask, InsertMask);
447 unsigned MB, ME;
448 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
449 SDValue Tmp1, Tmp2, Tmp3;
450 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
452 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
453 isInt32Immediate(Op1.getOperand(1), Value)) {
454 Op1 = Op1.getOperand(0);
455 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
457 if (Op1Opc == ISD::AND) {
458 unsigned SHOpc = Op1.getOperand(0).getOpcode();
459 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
460 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
461 Op1 = Op1.getOperand(0).getOperand(0);
462 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
463 } else {
464 Op1 = Op1.getOperand(0);
468 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
469 SH &= 31;
470 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
471 getI32Imm(ME) };
472 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
475 return 0;
478 /// SelectCC - Select a comparison of the specified values with the specified
479 /// condition code, returning the CR# of the expression.
480 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
481 ISD::CondCode CC, DebugLoc dl) {
482 // Always select the LHS.
483 unsigned Opc;
485 if (LHS.getValueType() == MVT::i32) {
486 unsigned Imm;
487 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
488 if (isInt32Immediate(RHS, Imm)) {
489 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
490 if (isUInt16(Imm))
491 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
492 getI32Imm(Imm & 0xFFFF)), 0);
493 // If this is a 16-bit signed immediate, fold it.
494 if (isInt16((int)Imm))
495 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
496 getI32Imm(Imm & 0xFFFF)), 0);
498 // For non-equality comparisons, the default code would materialize the
499 // constant, then compare against it, like this:
500 // lis r2, 4660
501 // ori r2, r2, 22136
502 // cmpw cr0, r3, r2
503 // Since we are just comparing for equality, we can emit this instead:
504 // xoris r0,r3,0x1234
505 // cmplwi cr0,r0,0x5678
506 // beq cr0,L6
507 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
508 getI32Imm(Imm >> 16)), 0);
509 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
510 getI32Imm(Imm & 0xFFFF)), 0);
512 Opc = PPC::CMPLW;
513 } else if (ISD::isUnsignedIntSetCC(CC)) {
514 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
515 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
516 getI32Imm(Imm & 0xFFFF)), 0);
517 Opc = PPC::CMPLW;
518 } else {
519 short SImm;
520 if (isIntS16Immediate(RHS, SImm))
521 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
522 getI32Imm((int)SImm & 0xFFFF)),
524 Opc = PPC::CMPW;
526 } else if (LHS.getValueType() == MVT::i64) {
527 uint64_t Imm;
528 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
529 if (isInt64Immediate(RHS.getNode(), Imm)) {
530 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
531 if (isUInt16(Imm))
532 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
533 getI32Imm(Imm & 0xFFFF)), 0);
534 // If this is a 16-bit signed immediate, fold it.
535 if (isInt16(Imm))
536 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
537 getI32Imm(Imm & 0xFFFF)), 0);
539 // For non-equality comparisons, the default code would materialize the
540 // constant, then compare against it, like this:
541 // lis r2, 4660
542 // ori r2, r2, 22136
543 // cmpd cr0, r3, r2
544 // Since we are just comparing for equality, we can emit this instead:
545 // xoris r0,r3,0x1234
546 // cmpldi cr0,r0,0x5678
547 // beq cr0,L6
548 if (isUInt32(Imm)) {
549 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
550 getI64Imm(Imm >> 16)), 0);
551 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
552 getI64Imm(Imm & 0xFFFF)), 0);
555 Opc = PPC::CMPLD;
556 } else if (ISD::isUnsignedIntSetCC(CC)) {
557 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
558 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
559 getI64Imm(Imm & 0xFFFF)), 0);
560 Opc = PPC::CMPLD;
561 } else {
562 short SImm;
563 if (isIntS16Immediate(RHS, SImm))
564 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
565 getI64Imm(SImm & 0xFFFF)),
567 Opc = PPC::CMPD;
569 } else if (LHS.getValueType() == MVT::f32) {
570 Opc = PPC::FCMPUS;
571 } else {
572 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
573 Opc = PPC::FCMPUD;
575 return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
578 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
579 switch (CC) {
580 case ISD::SETUEQ:
581 case ISD::SETONE:
582 case ISD::SETOLE:
583 case ISD::SETOGE:
584 llvm_unreachable("Should be lowered by legalize!");
585 default: llvm_unreachable("Unknown condition!");
586 case ISD::SETOEQ:
587 case ISD::SETEQ: return PPC::PRED_EQ;
588 case ISD::SETUNE:
589 case ISD::SETNE: return PPC::PRED_NE;
590 case ISD::SETOLT:
591 case ISD::SETLT: return PPC::PRED_LT;
592 case ISD::SETULE:
593 case ISD::SETLE: return PPC::PRED_LE;
594 case ISD::SETOGT:
595 case ISD::SETGT: return PPC::PRED_GT;
596 case ISD::SETUGE:
597 case ISD::SETGE: return PPC::PRED_GE;
598 case ISD::SETO: return PPC::PRED_NU;
599 case ISD::SETUO: return PPC::PRED_UN;
600 // These two are invalid for floating point. Assume we have int.
601 case ISD::SETULT: return PPC::PRED_LT;
602 case ISD::SETUGT: return PPC::PRED_GT;
606 /// getCRIdxForSetCC - Return the index of the condition register field
607 /// associated with the SetCC condition, and whether or not the field is
608 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
610 /// If this returns with Other != -1, then the returned comparison is an or of
611 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
612 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
613 Invert = false;
614 Other = -1;
615 switch (CC) {
616 default: llvm_unreachable("Unknown condition!");
617 case ISD::SETOLT:
618 case ISD::SETLT: return 0; // Bit #0 = SETOLT
619 case ISD::SETOGT:
620 case ISD::SETGT: return 1; // Bit #1 = SETOGT
621 case ISD::SETOEQ:
622 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
623 case ISD::SETUO: return 3; // Bit #3 = SETUO
624 case ISD::SETUGE:
625 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
626 case ISD::SETULE:
627 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
628 case ISD::SETUNE:
629 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
630 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
631 case ISD::SETUEQ:
632 case ISD::SETOGE:
633 case ISD::SETOLE:
634 case ISD::SETONE:
635 llvm_unreachable("Invalid branch code: should be expanded by legalize");
636 // These are invalid for floating point. Assume integer.
637 case ISD::SETULT: return 0;
638 case ISD::SETUGT: return 1;
640 return 0;
643 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
644 SDNode *N = Op.getNode();
645 DebugLoc dl = N->getDebugLoc();
646 unsigned Imm;
647 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
648 if (isInt32Immediate(N->getOperand(1), Imm)) {
649 // We can codegen setcc op, imm very efficiently compared to a brcond.
650 // Check for those cases here.
651 // setcc op, 0
652 if (Imm == 0) {
653 SDValue Op = N->getOperand(0);
654 switch (CC) {
655 default: break;
656 case ISD::SETEQ: {
657 Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
658 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
659 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
661 case ISD::SETNE: {
662 SDValue AD =
663 SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
664 Op, getI32Imm(~0U)), 0);
665 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
666 AD.getValue(1));
668 case ISD::SETLT: {
669 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
670 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
672 case ISD::SETGT: {
673 SDValue T =
674 SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
675 T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
676 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
677 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
680 } else if (Imm == ~0U) { // setcc op, -1
681 SDValue Op = N->getOperand(0);
682 switch (CC) {
683 default: break;
684 case ISD::SETEQ:
685 Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
686 Op, getI32Imm(1)), 0);
687 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
688 SDValue(CurDAG->getTargetNode(PPC::LI, dl,
689 MVT::i32,
690 getI32Imm(0)), 0),
691 Op.getValue(1));
692 case ISD::SETNE: {
693 Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
694 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
695 Op, getI32Imm(~0U));
696 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
697 Op, SDValue(AD, 1));
699 case ISD::SETLT: {
700 SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
701 getI32Imm(1)), 0);
702 SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
703 Op), 0);
704 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
705 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
707 case ISD::SETGT: {
708 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
709 Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
711 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
712 getI32Imm(1));
718 bool Inv;
719 int OtherCondIdx;
720 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
721 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
722 SDValue IntCR;
724 // Force the ccreg into CR7.
725 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
727 SDValue InFlag(0, 0); // Null incoming flag value.
728 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
729 InFlag).getValue(1);
731 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
732 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
733 CCReg), 0);
734 else
735 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
737 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
738 getI32Imm(31), getI32Imm(31) };
739 if (OtherCondIdx == -1 && !Inv)
740 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
742 // Get the specified bit.
743 SDValue Tmp =
744 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
745 if (Inv) {
746 assert(OtherCondIdx == -1 && "Can't have split plus negation");
747 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
750 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
751 // We already got the bit for the first part of the comparison (e.g. SETULE).
753 // Get the other bit of the comparison.
754 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
755 SDValue OtherCond =
756 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
758 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
762 // Select - Convert the specified operand from a target-independent to a
763 // target-specific node if it hasn't already been changed.
764 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
765 SDNode *N = Op.getNode();
766 DebugLoc dl = Op.getDebugLoc();
767 if (N->isMachineOpcode())
768 return NULL; // Already selected.
770 switch (N->getOpcode()) {
771 default: break;
773 case ISD::Constant: {
774 if (N->getValueType(0) == MVT::i64) {
775 // Get 64 bit value.
776 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
777 // Assume no remaining bits.
778 unsigned Remainder = 0;
779 // Assume no shift required.
780 unsigned Shift = 0;
782 // If it can't be represented as a 32 bit value.
783 if (!isInt32(Imm)) {
784 Shift = CountTrailingZeros_64(Imm);
785 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
787 // If the shifted value fits 32 bits.
788 if (isInt32(ImmSh)) {
789 // Go with the shifted value.
790 Imm = ImmSh;
791 } else {
792 // Still stuck with a 64 bit value.
793 Remainder = Imm;
794 Shift = 32;
795 Imm >>= 32;
799 // Intermediate operand.
800 SDNode *Result;
802 // Handle first 32 bits.
803 unsigned Lo = Imm & 0xFFFF;
804 unsigned Hi = (Imm >> 16) & 0xFFFF;
806 // Simple value.
807 if (isInt16(Imm)) {
808 // Just the Lo bits.
809 Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
810 } else if (Lo) {
811 // Handle the Hi bits.
812 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
813 Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
814 // And Lo bits.
815 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
816 SDValue(Result, 0), getI32Imm(Lo));
817 } else {
818 // Just the Hi bits.
819 Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
822 // If no shift, we're done.
823 if (!Shift) return Result;
825 // Shift for next step if the upper 32-bits were not zero.
826 if (Imm) {
827 Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
828 SDValue(Result, 0),
829 getI32Imm(Shift), getI32Imm(63 - Shift));
832 // Add in the last bits as required.
833 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
834 Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
835 SDValue(Result, 0), getI32Imm(Hi));
837 if ((Lo = Remainder & 0xFFFF)) {
838 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
839 SDValue(Result, 0), getI32Imm(Lo));
842 return Result;
844 break;
847 case ISD::SETCC:
848 return SelectSETCC(Op);
849 case PPCISD::GlobalBaseReg:
850 return getGlobalBaseReg();
852 case ISD::FrameIndex: {
853 int FI = cast<FrameIndexSDNode>(N)->getIndex();
854 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
855 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
856 if (N->hasOneUse())
857 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
858 getSmallIPtrImm(0));
859 return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI,
860 getSmallIPtrImm(0));
863 case PPCISD::MFCR: {
864 SDValue InFlag = N->getOperand(1);
865 // Use MFOCRF if supported.
866 if (PPCSubTarget.isGigaProcessor())
867 return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
868 N->getOperand(0), InFlag);
869 else
870 return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
873 case ISD::SDIV: {
874 // FIXME: since this depends on the setting of the carry flag from the srawi
875 // we should really be making notes about that for the scheduler.
876 // FIXME: It sure would be nice if we could cheaply recognize the
877 // srl/add/sra pattern the dag combiner will generate for this as
878 // sra/addze rather than having to handle sdiv ourselves. oh well.
879 unsigned Imm;
880 if (isInt32Immediate(N->getOperand(1), Imm)) {
881 SDValue N0 = N->getOperand(0);
882 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
883 SDNode *Op =
884 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
885 N0, getI32Imm(Log2_32(Imm)));
886 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
887 SDValue(Op, 0), SDValue(Op, 1));
888 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
889 SDNode *Op =
890 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
891 N0, getI32Imm(Log2_32(-Imm)));
892 SDValue PT =
893 SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
894 SDValue(Op, 0), SDValue(Op, 1)),
896 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
900 // Other cases are autogenerated.
901 break;
904 case ISD::LOAD: {
905 // Handle preincrement loads.
906 LoadSDNode *LD = cast<LoadSDNode>(Op);
907 EVT LoadedVT = LD->getMemoryVT();
909 // Normal loads are handled by code generated from the .td file.
910 if (LD->getAddressingMode() != ISD::PRE_INC)
911 break;
913 SDValue Offset = LD->getOffset();
914 if (isa<ConstantSDNode>(Offset) ||
915 Offset.getOpcode() == ISD::TargetGlobalAddress) {
917 unsigned Opcode;
918 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
919 if (LD->getValueType(0) != MVT::i64) {
920 // Handle PPC32 integer and normal FP loads.
921 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
922 switch (LoadedVT.getSimpleVT().SimpleTy) {
923 default: llvm_unreachable("Invalid PPC load type!");
924 case MVT::f64: Opcode = PPC::LFDU; break;
925 case MVT::f32: Opcode = PPC::LFSU; break;
926 case MVT::i32: Opcode = PPC::LWZU; break;
927 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
928 case MVT::i1:
929 case MVT::i8: Opcode = PPC::LBZU; break;
931 } else {
932 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
933 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
934 switch (LoadedVT.getSimpleVT().SimpleTy) {
935 default: llvm_unreachable("Invalid PPC load type!");
936 case MVT::i64: Opcode = PPC::LDU; break;
937 case MVT::i32: Opcode = PPC::LWZU8; break;
938 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
939 case MVT::i1:
940 case MVT::i8: Opcode = PPC::LBZU8; break;
944 SDValue Chain = LD->getChain();
945 SDValue Base = LD->getBasePtr();
946 SDValue Ops[] = { Offset, Base, Chain };
947 // FIXME: PPC64
948 return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
949 PPCLowering.getPointerTy(),
950 MVT::Other, Ops, 3);
951 } else {
952 llvm_unreachable("R+R preindex loads not supported yet!");
956 case ISD::AND: {
957 unsigned Imm, Imm2, SH, MB, ME;
959 // If this is an and of a value rotated between 0 and 31 bits and then and'd
960 // with a mask, emit rlwinm
961 if (isInt32Immediate(N->getOperand(1), Imm) &&
962 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
963 SDValue Val = N->getOperand(0).getOperand(0);
964 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
965 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
967 // If this is just a masked value where the input is not handled above, and
968 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
969 if (isInt32Immediate(N->getOperand(1), Imm) &&
970 isRunOfOnes(Imm, MB, ME) &&
971 N->getOperand(0).getOpcode() != ISD::ROTL) {
972 SDValue Val = N->getOperand(0);
973 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
974 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
976 // AND X, 0 -> 0, not "rlwinm 32".
977 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
978 ReplaceUses(SDValue(N, 0), N->getOperand(1));
979 return NULL;
981 // ISD::OR doesn't get all the bitfield insertion fun.
982 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
983 if (isInt32Immediate(N->getOperand(1), Imm) &&
984 N->getOperand(0).getOpcode() == ISD::OR &&
985 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
986 unsigned MB, ME;
987 Imm = ~(Imm^Imm2);
988 if (isRunOfOnes(Imm, MB, ME)) {
989 SDValue Ops[] = { N->getOperand(0).getOperand(0),
990 N->getOperand(0).getOperand(1),
991 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
992 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
996 // Other cases are autogenerated.
997 break;
999 case ISD::OR:
1000 if (N->getValueType(0) == MVT::i32)
1001 if (SDNode *I = SelectBitfieldInsert(N))
1002 return I;
1004 // Other cases are autogenerated.
1005 break;
1006 case ISD::SHL: {
1007 unsigned Imm, SH, MB, ME;
1008 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1009 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1010 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1011 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1012 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1015 // Other cases are autogenerated.
1016 break;
1018 case ISD::SRL: {
1019 unsigned Imm, SH, MB, ME;
1020 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1021 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1022 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1023 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1024 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1027 // Other cases are autogenerated.
1028 break;
1030 case ISD::SELECT_CC: {
1031 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1033 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1034 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1035 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1036 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1037 if (N1C->isNullValue() && N3C->isNullValue() &&
1038 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1039 // FIXME: Implement this optzn for PPC64.
1040 N->getValueType(0) == MVT::i32) {
1041 SDNode *Tmp =
1042 CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
1043 N->getOperand(0), getI32Imm(~0U));
1044 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1045 SDValue(Tmp, 0), N->getOperand(0),
1046 SDValue(Tmp, 1));
1049 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1050 unsigned BROpc = getPredicateForSetCC(CC);
1052 unsigned SelectCCOp;
1053 if (N->getValueType(0) == MVT::i32)
1054 SelectCCOp = PPC::SELECT_CC_I4;
1055 else if (N->getValueType(0) == MVT::i64)
1056 SelectCCOp = PPC::SELECT_CC_I8;
1057 else if (N->getValueType(0) == MVT::f32)
1058 SelectCCOp = PPC::SELECT_CC_F4;
1059 else if (N->getValueType(0) == MVT::f64)
1060 SelectCCOp = PPC::SELECT_CC_F8;
1061 else
1062 SelectCCOp = PPC::SELECT_CC_VRRC;
1064 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1065 getI32Imm(BROpc) };
1066 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1068 case PPCISD::COND_BRANCH: {
1069 // Op #0 is the Chain.
1070 // Op #1 is the PPC::PRED_* number.
1071 // Op #2 is the CR#
1072 // Op #3 is the Dest MBB
1073 // Op #4 is the Flag.
1074 // Prevent PPC::PRED_* from being selected into LI.
1075 SDValue Pred =
1076 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1077 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1078 N->getOperand(0), N->getOperand(4) };
1079 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1081 case ISD::BR_CC: {
1082 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1083 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1084 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1085 N->getOperand(4), N->getOperand(0) };
1086 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1088 case ISD::BRIND: {
1089 // FIXME: Should custom lower this.
1090 SDValue Chain = N->getOperand(0);
1091 SDValue Target = N->getOperand(1);
1092 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1093 Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
1094 Chain), 0);
1095 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1099 return SelectCode(Op);
1104 /// createPPCISelDag - This pass converts a legalized DAG into a
1105 /// PowerPC-specific DAG, ready for instruction scheduling.
1107 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1108 return new PPCDAGToDAGISel(TM);