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1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
12 //
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
19 //
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
22 ]>;
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
25 SDTCisVT<1, i32> ]>;
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
28 ]>;
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
32 ]>;
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
36 ]>;
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
40 ]>;
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 ]>;
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
47 ]>;
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
50 ]>;
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
54 ]>;
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
60 //
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
71 [SDNPOutFlag]>;
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInFlag, SDNPOutFlag]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
80 SDTCisVT<3, f64>]>,
81 [SDNPInFlag]>;
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutFlag]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
116 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
117 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>;
118 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
119 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
120 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
123 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
127 [SDNPHasChain, SDNPOptInFlag]>;
129 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
130 [SDNPHasChain, SDNPOptInFlag]>;
132 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
133 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
135 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
136 [SDNPHasChain, SDNPOptInFlag]>;
138 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
139 [SDNPHasChain, SDNPMayLoad]>;
140 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
141 [SDNPHasChain, SDNPMayStore]>;
143 // Instructions to support atomic operations
144 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
145 [SDNPHasChain, SDNPMayLoad]>;
146 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
147 [SDNPHasChain, SDNPMayStore]>;
149 // Instructions to support dynamic alloca.
150 def SDTDynOp : SDTypeProfile<1, 2, []>;
151 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
153 //===----------------------------------------------------------------------===//
154 // PowerPC specific transformation functions and pattern fragments.
155 //
157 def SHL32 : SDNodeXForm<imm, [{
158 // Transformation function: 31 - imm
159 return getI32Imm(31 - N->getZExtValue());
160 }]>;
162 def SRL32 : SDNodeXForm<imm, [{
163 // Transformation function: 32 - imm
164 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
165 }]>;
167 def LO16 : SDNodeXForm<imm, [{
168 // Transformation function: get the low 16 bits.
169 return getI32Imm((unsigned short)N->getZExtValue());
170 }]>;
172 def HI16 : SDNodeXForm<imm, [{
173 // Transformation function: shift the immediate value down into the low bits.
174 return getI32Imm((unsigned)N->getZExtValue() >> 16);
175 }]>;
177 def HA16 : SDNodeXForm<imm, [{
178 // Transformation function: shift the immediate value down into the low bits.
179 signed int Val = N->getZExtValue();
180 return getI32Imm((Val - (signed short)Val) >> 16);
181 }]>;
182 def MB : SDNodeXForm<imm, [{
183 // Transformation function: get the start bit of a mask
184 unsigned mb = 0, me;
185 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
186 return getI32Imm(mb);
187 }]>;
189 def ME : SDNodeXForm<imm, [{
190 // Transformation function: get the end bit of a mask
191 unsigned mb, me = 0;
192 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
193 return getI32Imm(me);
194 }]>;
195 def maskimm32 : PatLeaf<(imm), [{
196 // maskImm predicate - True if immediate is a run of ones.
197 unsigned mb, me;
198 if (N->getValueType(0) == MVT::i32)
199 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
200 else
201 return false;
202 }]>;
204 def immSExt16 : PatLeaf<(imm), [{
205 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
206 // field. Used by instructions like 'addi'.
207 if (N->getValueType(0) == MVT::i32)
208 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
209 else
210 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
211 }]>;
212 def immZExt16 : PatLeaf<(imm), [{
213 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
214 // field. Used by instructions like 'ori'.
215 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
216 }], LO16>;
218 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
219 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
220 // identical in 32-bit mode, but in 64-bit mode, they return true if the
221 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
222 // clear).
223 def imm16ShiftedZExt : PatLeaf<(imm), [{
224 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
225 // immediate are set. Used by instructions like 'xoris'.
226 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
227 }], HI16>;
229 def imm16ShiftedSExt : PatLeaf<(imm), [{
230 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
231 // immediate are set. Used by instructions like 'addis'. Identical to
232 // imm16ShiftedZExt in 32-bit mode.
233 if (N->getZExtValue() & 0xFFFF) return false;
234 if (N->getValueType(0) == MVT::i32)
235 return true;
236 // For 64-bit, make sure it is sext right.
237 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
238 }], HI16>;
241 //===----------------------------------------------------------------------===//
242 // PowerPC Flag Definitions.
244 class isPPC64 { bit PPC64 = 1; }
245 class isDOT {
246 list<Register> Defs = [CR0];
247 bit RC = 1;
248 }
250 class RegConstraint<string C> {
251 string Constraints = C;
252 }
253 class NoEncode<string E> {
254 string DisableEncoding = E;
255 }
258 //===----------------------------------------------------------------------===//
259 // PowerPC Operand Definitions.
261 def s5imm : Operand<i32> {
262 let PrintMethod = "printS5ImmOperand";
263 }
264 def u5imm : Operand<i32> {
265 let PrintMethod = "printU5ImmOperand";
266 }
267 def u6imm : Operand<i32> {
268 let PrintMethod = "printU6ImmOperand";
269 }
270 def s16imm : Operand<i32> {
271 let PrintMethod = "printS16ImmOperand";
272 }
273 def u16imm : Operand<i32> {
274 let PrintMethod = "printU16ImmOperand";
275 }
276 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
277 let PrintMethod = "printS16X4ImmOperand";
278 }
279 def target : Operand<OtherVT> {
280 let PrintMethod = "printBranchOperand";
281 }
282 def calltarget : Operand<iPTR> {
283 let PrintMethod = "printCallOperand";
284 }
285 def aaddr : Operand<iPTR> {
286 let PrintMethod = "printAbsAddrOperand";
287 }
288 def piclabel: Operand<iPTR> {
289 let PrintMethod = "printPICLabel";
290 }
291 def symbolHi: Operand<i32> {
292 let PrintMethod = "printSymbolHi";
293 }
294 def symbolLo: Operand<i32> {
295 let PrintMethod = "printSymbolLo";
296 }
297 def crbitm: Operand<i8> {
298 let PrintMethod = "printcrbitm";
299 }
300 // Address operands
301 def memri : Operand<iPTR> {
302 let PrintMethod = "printMemRegImm";
303 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
304 }
305 def memrr : Operand<iPTR> {
306 let PrintMethod = "printMemRegReg";
307 let MIOperandInfo = (ops ptr_rc, ptr_rc);
308 }
309 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
310 let PrintMethod = "printMemRegImmShifted";
311 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
312 }
313 def tocentry : Operand<iPTR> {
314 let PrintMethod = "printTOCEntryLabel";
315 let MIOperandInfo = (ops i32imm:$imm);
316 }
318 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
319 // that doesn't matter.
320 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
321 (ops (i32 20), (i32 zero_reg))> {
322 let PrintMethod = "printPredicateOperand";
323 }
325 // Define PowerPC specific addressing mode.
326 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
327 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
328 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
329 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
331 /// This is just the offset part of iaddr, used for preinc.
332 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
334 //===----------------------------------------------------------------------===//
335 // PowerPC Instruction Predicate Definitions.
336 def FPContractions : Predicate<"!NoExcessFPPrecision">;
337 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
338 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
341 //===----------------------------------------------------------------------===//
342 // PowerPC Instruction Definitions.
344 // Pseudo-instructions:
346 let hasCtrlDep = 1 in {
347 let Defs = [R1], Uses = [R1] in {
348 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
349 "${:comment} ADJCALLSTACKDOWN",
350 [(callseq_start timm:$amt)]>;
351 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
352 "${:comment} ADJCALLSTACKUP",
353 [(callseq_end timm:$amt1, timm:$amt2)]>;
354 }
356 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
357 "UPDATE_VRSAVE $rD, $rS", []>;
358 }
360 let Defs = [R1], Uses = [R1] in
361 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
362 "${:comment} DYNALLOC $result, $negsize, $fpsi",
363 [(set GPRC:$result,
364 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
366 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
367 // scheduler into a branch sequence.
368 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
369 PPC970_Single = 1 in {
370 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
371 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
372 []>;
373 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
374 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
375 []>;
376 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
377 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
378 []>;
379 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
380 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
381 []>;
382 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
383 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
384 []>;
385 }
387 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
388 // scavenge a register for it.
389 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
390 "${:comment} SPILL_CR $cond $F", []>;
392 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
393 let isReturn = 1, Uses = [LR, RM] in
394 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
395 "b${p:cc}lr ${p:reg}", BrB,
396 [(retflag)]>;
397 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
398 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
399 }
401 let Defs = [LR] in
402 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
403 PPC970_Unit_BRU;
405 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
406 let isBarrier = 1 in {
407 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
408 "b $dst", BrB,
409 [(br bb:$dst)]>;
410 }
412 // BCC represents an arbitrary conditional branch on a predicate.
413 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
414 // a two-value operand where a dag node expects two operands. :(
415 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
416 "b${cond:cc} ${cond:reg}, $dst"
417 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
418 }
420 // Darwin ABI Calls.
421 let isCall = 1, PPC970_Unit = 7,
422 // All calls clobber the non-callee saved registers...
423 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
424 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
425 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
426 LR,CTR,
427 CR0,CR1,CR5,CR6,CR7,
428 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
429 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
430 // Convenient aliases for call instructions
431 let Uses = [RM] in {
432 def BL_Darwin : IForm<18, 0, 1,
433 (outs), (ins calltarget:$func, variable_ops),
434 "bl $func", BrB, []>; // See Pat patterns below.
435 def BLA_Darwin : IForm<18, 1, 1,
436 (outs), (ins aaddr:$func, variable_ops),
437 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
438 }
439 let Uses = [CTR, RM] in {
440 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
441 (outs), (ins variable_ops),
442 "bctrl", BrB,
443 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
444 }
445 }
447 // SVR4 ABI Calls.
448 let isCall = 1, PPC970_Unit = 7,
449 // All calls clobber the non-callee saved registers...
450 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
451 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
452 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
453 LR,CTR,
454 CR0,CR1,CR5,CR6,CR7,
455 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
456 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
457 // Convenient aliases for call instructions
458 let Uses = [RM] in {
459 def BL_SVR4 : IForm<18, 0, 1,
460 (outs), (ins calltarget:$func, variable_ops),
461 "bl $func", BrB, []>; // See Pat patterns below.
462 def BLA_SVR4 : IForm<18, 1, 1,
463 (outs), (ins aaddr:$func, variable_ops),
464 "bla $func", BrB,
465 [(PPCcall_SVR4 (i32 imm:$func))]>;
466 }
467 let Uses = [CTR, RM] in {
468 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
469 (outs), (ins variable_ops),
470 "bctrl", BrB,
471 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
472 }
473 }
476 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
477 def TCRETURNdi :Pseudo< (outs),
478 (ins calltarget:$dst, i32imm:$offset, variable_ops),
479 "#TC_RETURNd $dst $offset",
480 []>;
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
484 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
485 "#TC_RETURNa $func $offset",
486 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
488 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
489 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
490 "#TC_RETURNr $dst $offset",
491 []>;
494 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
495 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
496 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
497 Requires<[In32BitMode]>;
501 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
502 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
503 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
504 "b $dst", BrB,
505 []>;
508 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
509 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
510 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
511 "ba $dst", BrB,
512 []>;
515 // DCB* instructions.
516 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
517 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
518 PPC970_DGroup_Single;
519 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
520 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
521 PPC970_DGroup_Single;
522 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
523 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
524 PPC970_DGroup_Single;
525 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
526 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
527 PPC970_DGroup_Single;
528 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
529 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
530 PPC970_DGroup_Single;
531 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
532 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
533 PPC970_DGroup_Single;
534 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
535 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
536 PPC970_DGroup_Single;
537 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
538 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
539 PPC970_DGroup_Single;
541 // Atomic operations
542 let usesCustomDAGSchedInserter = 1 in {
543 let Uses = [CR0] in {
544 def ATOMIC_LOAD_ADD_I8 : Pseudo<
545 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
546 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
547 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
548 def ATOMIC_LOAD_SUB_I8 : Pseudo<
549 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
550 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
551 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
552 def ATOMIC_LOAD_AND_I8 : Pseudo<
553 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
554 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
555 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
556 def ATOMIC_LOAD_OR_I8 : Pseudo<
557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
558 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
559 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
560 def ATOMIC_LOAD_XOR_I8 : Pseudo<
561 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
562 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
563 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
564 def ATOMIC_LOAD_NAND_I8 : Pseudo<
565 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
566 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
567 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
568 def ATOMIC_LOAD_ADD_I16 : Pseudo<
569 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
570 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
571 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
572 def ATOMIC_LOAD_SUB_I16 : Pseudo<
573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
574 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
575 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
576 def ATOMIC_LOAD_AND_I16 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
578 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
579 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
580 def ATOMIC_LOAD_OR_I16 : Pseudo<
581 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
582 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
583 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
584 def ATOMIC_LOAD_XOR_I16 : Pseudo<
585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
586 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
587 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_NAND_I16 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
590 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
591 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
592 def ATOMIC_LOAD_ADD_I32 : Pseudo<
593 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
594 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
595 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
596 def ATOMIC_LOAD_SUB_I32 : Pseudo<
597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
598 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
599 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_AND_I32 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
602 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
603 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
604 def ATOMIC_LOAD_OR_I32 : Pseudo<
605 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
606 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
607 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
608 def ATOMIC_LOAD_XOR_I32 : Pseudo<
609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
610 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
611 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
612 def ATOMIC_LOAD_NAND_I32 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
614 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
615 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
617 def ATOMIC_CMP_SWAP_I8 : Pseudo<
618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
619 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
620 [(set GPRC:$dst,
621 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
622 def ATOMIC_CMP_SWAP_I16 : Pseudo<
623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
624 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
625 [(set GPRC:$dst,
626 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
627 def ATOMIC_CMP_SWAP_I32 : Pseudo<
628 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
629 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
630 [(set GPRC:$dst,
631 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
633 def ATOMIC_SWAP_I8 : Pseudo<
634 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
635 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
636 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
637 def ATOMIC_SWAP_I16 : Pseudo<
638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
639 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
640 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
641 def ATOMIC_SWAP_I32 : Pseudo<
642 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
643 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
644 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
645 }
646 }
648 // Instructions to support atomic operations
649 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
650 "lwarx $rD, $src", LdStLWARX,
651 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
653 let Defs = [CR0] in
654 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
655 "stwcx. $rS, $dst", LdStSTWCX,
656 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
657 isDOT;
659 let isBarrier = 1, hasCtrlDep = 1 in
660 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
662 //===----------------------------------------------------------------------===//
663 // PPC32 Load Instructions.
664 //
666 // Unindexed (r+i) Loads.
667 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
668 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
669 "lbz $rD, $src", LdStGeneral,
670 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
671 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
672 "lha $rD, $src", LdStLHA,
673 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
674 PPC970_DGroup_Cracked;
675 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
676 "lhz $rD, $src", LdStGeneral,
677 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
678 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
679 "lwz $rD, $src", LdStGeneral,
680 [(set GPRC:$rD, (load iaddr:$src))]>;
682 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
683 "lfs $rD, $src", LdStLFDU,
684 [(set F4RC:$rD, (load iaddr:$src))]>;
685 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
686 "lfd $rD, $src", LdStLFD,
687 [(set F8RC:$rD, (load iaddr:$src))]>;
690 // Unindexed (r+i) Loads with Update (preinc).
691 let mayLoad = 1 in {
692 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
693 "lbzu $rD, $addr", LdStGeneral,
694 []>, RegConstraint<"$addr.reg = $ea_result">,
695 NoEncode<"$ea_result">;
697 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
698 "lhau $rD, $addr", LdStGeneral,
699 []>, RegConstraint<"$addr.reg = $ea_result">,
700 NoEncode<"$ea_result">;
702 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
703 "lhzu $rD, $addr", LdStGeneral,
704 []>, RegConstraint<"$addr.reg = $ea_result">,
705 NoEncode<"$ea_result">;
707 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
708 "lwzu $rD, $addr", LdStGeneral,
709 []>, RegConstraint<"$addr.reg = $ea_result">,
710 NoEncode<"$ea_result">;
712 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
713 "lfs $rD, $addr", LdStLFDU,
714 []>, RegConstraint<"$addr.reg = $ea_result">,
715 NoEncode<"$ea_result">;
717 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
718 "lfd $rD, $addr", LdStLFD,
719 []>, RegConstraint<"$addr.reg = $ea_result">,
720 NoEncode<"$ea_result">;
721 }
722 }
724 // Indexed (r+r) Loads.
725 //
726 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
727 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
728 "lbzx $rD, $src", LdStGeneral,
729 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
730 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
731 "lhax $rD, $src", LdStLHA,
732 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
733 PPC970_DGroup_Cracked;
734 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
735 "lhzx $rD, $src", LdStGeneral,
736 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
737 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
738 "lwzx $rD, $src", LdStGeneral,
739 [(set GPRC:$rD, (load xaddr:$src))]>;
742 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
743 "lhbrx $rD, $src", LdStGeneral,
744 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
745 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
746 "lwbrx $rD, $src", LdStGeneral,
747 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
749 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
750 "lfsx $frD, $src", LdStLFDU,
751 [(set F4RC:$frD, (load xaddr:$src))]>;
752 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
753 "lfdx $frD, $src", LdStLFDU,
754 [(set F8RC:$frD, (load xaddr:$src))]>;
755 }
757 //===----------------------------------------------------------------------===//
758 // PPC32 Store Instructions.
759 //
761 // Unindexed (r+i) Stores.
762 let PPC970_Unit = 2 in {
763 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
764 "stb $rS, $src", LdStGeneral,
765 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
766 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
767 "sth $rS, $src", LdStGeneral,
768 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
769 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
770 "stw $rS, $src", LdStGeneral,
771 [(store GPRC:$rS, iaddr:$src)]>;
772 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
773 "stfs $rS, $dst", LdStUX,
774 [(store F4RC:$rS, iaddr:$dst)]>;
775 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
776 "stfd $rS, $dst", LdStUX,
777 [(store F8RC:$rS, iaddr:$dst)]>;
778 }
780 // Unindexed (r+i) Stores with Update (preinc).
781 let PPC970_Unit = 2 in {
782 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
783 symbolLo:$ptroff, ptr_rc:$ptrreg),
784 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
785 [(set ptr_rc:$ea_res,
786 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
787 iaddroff:$ptroff))]>,
788 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
789 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
790 symbolLo:$ptroff, ptr_rc:$ptrreg),
791 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
792 [(set ptr_rc:$ea_res,
793 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
794 iaddroff:$ptroff))]>,
795 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
796 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
797 symbolLo:$ptroff, ptr_rc:$ptrreg),
798 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
799 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
800 iaddroff:$ptroff))]>,
801 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
802 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
803 symbolLo:$ptroff, ptr_rc:$ptrreg),
804 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
805 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
806 iaddroff:$ptroff))]>,
807 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
808 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
809 symbolLo:$ptroff, ptr_rc:$ptrreg),
810 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
811 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
812 iaddroff:$ptroff))]>,
813 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
814 }
817 // Indexed (r+r) Stores.
818 //
819 let PPC970_Unit = 2 in {
820 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
821 "stbx $rS, $dst", LdStGeneral,
822 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
823 PPC970_DGroup_Cracked;
824 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
825 "sthx $rS, $dst", LdStGeneral,
826 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
827 PPC970_DGroup_Cracked;
828 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
829 "stwx $rS, $dst", LdStGeneral,
830 [(store GPRC:$rS, xaddr:$dst)]>,
831 PPC970_DGroup_Cracked;
833 let mayStore = 1 in {
834 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
835 "stwux $rS, $rA, $rB", LdStGeneral,
836 []>;
837 }
838 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
839 "sthbrx $rS, $dst", LdStGeneral,
840 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
841 PPC970_DGroup_Cracked;
842 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
843 "stwbrx $rS, $dst", LdStGeneral,
844 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
845 PPC970_DGroup_Cracked;
847 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
848 "stfiwx $frS, $dst", LdStUX,
849 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
851 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
852 "stfsx $frS, $dst", LdStUX,
853 [(store F4RC:$frS, xaddr:$dst)]>;
854 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
855 "stfdx $frS, $dst", LdStUX,
856 [(store F8RC:$frS, xaddr:$dst)]>;
857 }
859 let isBarrier = 1 in
860 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
861 "sync", LdStSync,
862 [(int_ppc_sync)]>;
864 //===----------------------------------------------------------------------===//
865 // PPC32 Arithmetic Instructions.
866 //
868 let PPC970_Unit = 1 in { // FXU Operations.
869 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
870 "addi $rD, $rA, $imm", IntGeneral,
871 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
872 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
873 "addic $rD, $rA, $imm", IntGeneral,
874 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
875 PPC970_DGroup_Cracked;
876 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
877 "addic. $rD, $rA, $imm", IntGeneral,
878 []>;
879 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
880 "addis $rD, $rA, $imm", IntGeneral,
881 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
882 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
883 "la $rD, $sym($rA)", IntGeneral,
884 [(set GPRC:$rD, (add GPRC:$rA,
885 (PPClo tglobaladdr:$sym, 0)))]>;
886 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
887 "mulli $rD, $rA, $imm", IntMulLI,
888 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
889 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
890 "subfic $rD, $rA, $imm", IntGeneral,
891 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
893 let isReMaterializable = 1 in {
894 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
895 "li $rD, $imm", IntGeneral,
896 [(set GPRC:$rD, immSExt16:$imm)]>;
897 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
898 "lis $rD, $imm", IntGeneral,
899 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
900 }
901 }
903 let PPC970_Unit = 1 in { // FXU Operations.
904 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
905 "andi. $dst, $src1, $src2", IntGeneral,
906 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
907 isDOT;
908 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
909 "andis. $dst, $src1, $src2", IntGeneral,
910 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
911 isDOT;
912 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
913 "ori $dst, $src1, $src2", IntGeneral,
914 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
915 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
916 "oris $dst, $src1, $src2", IntGeneral,
917 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
918 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
919 "xori $dst, $src1, $src2", IntGeneral,
920 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
921 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
922 "xoris $dst, $src1, $src2", IntGeneral,
923 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
924 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
925 []>;
926 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
927 "cmpwi $crD, $rA, $imm", IntCompare>;
928 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
929 "cmplwi $dst, $src1, $src2", IntCompare>;
930 }
933 let PPC970_Unit = 1 in { // FXU Operations.
934 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
935 "nand $rA, $rS, $rB", IntGeneral,
936 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
937 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
938 "and $rA, $rS, $rB", IntGeneral,
939 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
940 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
941 "andc $rA, $rS, $rB", IntGeneral,
942 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
943 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
944 "or $rA, $rS, $rB", IntGeneral,
945 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
946 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
947 "nor $rA, $rS, $rB", IntGeneral,
948 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
949 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
950 "orc $rA, $rS, $rB", IntGeneral,
951 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
952 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
953 "eqv $rA, $rS, $rB", IntGeneral,
954 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
955 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
956 "xor $rA, $rS, $rB", IntGeneral,
957 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
958 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
959 "slw $rA, $rS, $rB", IntGeneral,
960 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
961 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
962 "srw $rA, $rS, $rB", IntGeneral,
963 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
964 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
965 "sraw $rA, $rS, $rB", IntShift,
966 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
967 }
969 let PPC970_Unit = 1 in { // FXU Operations.
970 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
971 "srawi $rA, $rS, $SH", IntShift,
972 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
973 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
974 "cntlzw $rA, $rS", IntGeneral,
975 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
976 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
977 "extsb $rA, $rS", IntGeneral,
978 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
979 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
980 "extsh $rA, $rS", IntGeneral,
981 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
983 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
984 "cmpw $crD, $rA, $rB", IntCompare>;
985 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
986 "cmplw $crD, $rA, $rB", IntCompare>;
987 }
988 let PPC970_Unit = 3 in { // FPU Operations.
989 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
990 // "fcmpo $crD, $fA, $fB", FPCompare>;
991 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
992 "fcmpu $crD, $fA, $fB", FPCompare>;
993 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
994 "fcmpu $crD, $fA, $fB", FPCompare>;
996 let Uses = [RM] in {
997 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
998 "fctiwz $frD, $frB", FPGeneral,
999 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1000 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1001 "frsp $frD, $frB", FPGeneral,
1002 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1003 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1004 "fsqrt $frD, $frB", FPSqrt,
1005 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1006 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1007 "fsqrts $frD, $frB", FPSqrt,
1008 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1009 }
1010 }
1012 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
1013 ///
1014 /// Note that these are defined as pseudo-ops on the PPC970 because they are
1015 /// often coalesced away and we don't want the dispatch group builder to think
1016 /// that they will fill slots (which could cause the load of a LSU reject to
1017 /// sneak into a d-group with a store).
1018 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1019 "fmr $frD, $frB", FPGeneral,
1020 []>, // (set F4RC:$frD, F4RC:$frB)
1021 PPC970_Unit_Pseudo;
1022 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
1023 "fmr $frD, $frB", FPGeneral,
1024 []>, // (set F8RC:$frD, F8RC:$frB)
1025 PPC970_Unit_Pseudo;
1026 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
1027 "fmr $frD, $frB", FPGeneral,
1028 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
1029 PPC970_Unit_Pseudo;
1031 let PPC970_Unit = 3 in { // FPU Operations.
1032 // These are artificially split into two different forms, for 4/8 byte FP.
1033 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1034 "fabs $frD, $frB", FPGeneral,
1035 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1036 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1037 "fabs $frD, $frB", FPGeneral,
1038 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1039 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1040 "fnabs $frD, $frB", FPGeneral,
1041 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1042 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1043 "fnabs $frD, $frB", FPGeneral,
1044 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1045 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1046 "fneg $frD, $frB", FPGeneral,
1047 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1048 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1049 "fneg $frD, $frB", FPGeneral,
1050 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1051 }
1054 // XL-Form instructions. condition register logical ops.
1055 //
1056 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1057 "mcrf $BF, $BFA", BrMCR>,
1058 PPC970_DGroup_First, PPC970_Unit_CRU;
1060 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1061 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1062 "creqv $CRD, $CRA, $CRB", BrCR,
1063 []>;
1065 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1066 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1067 "cror $CRD, $CRA, $CRB", BrCR,
1068 []>;
1070 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1071 "creqv $dst, $dst, $dst", BrCR,
1072 []>;
1074 // XFX-Form instructions. Instructions that deal with SPRs.
1075 //
1076 let Uses = [CTR] in {
1077 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1078 "mfctr $rT", SprMFSPR>,
1079 PPC970_DGroup_First, PPC970_Unit_FXU;
1080 }
1081 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1082 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1083 "mtctr $rS", SprMTSPR>,
1084 PPC970_DGroup_First, PPC970_Unit_FXU;
1085 }
1087 let Defs = [LR] in {
1088 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1089 "mtlr $rS", SprMTSPR>,
1090 PPC970_DGroup_First, PPC970_Unit_FXU;
1091 }
1092 let Uses = [LR] in {
1093 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1094 "mflr $rT", SprMFSPR>,
1095 PPC970_DGroup_First, PPC970_Unit_FXU;
1096 }
1098 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1099 // a GPR on the PPC970. As such, copies in and out have the same performance
1100 // characteristics as an OR instruction.
1101 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1102 "mtspr 256, $rS", IntGeneral>,
1103 PPC970_DGroup_Single, PPC970_Unit_FXU;
1104 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1105 "mfspr $rT, 256", IntGeneral>,
1106 PPC970_DGroup_First, PPC970_Unit_FXU;
1108 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1109 "mtcrf $FXM, $rS", BrMCRX>,
1110 PPC970_MicroCode, PPC970_Unit_CRU;
1111 // FIXME: this Uses all the CR registers. Marking it as such is
1112 // necessary for DeadMachineInstructionElim to do the right thing.
1113 // However, marking it also exposes PR 2964, and causes crashes in
1114 // the Local RA because it doesn't like this sequence:
1115 // vreg = MCRF CR0
1116 // MFCR <kill of whatever preg got assigned to vreg>
1117 // For now DeadMachineInstructionElim is turned off, so don't do the marking.
1118 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
1119 PPC970_MicroCode, PPC970_Unit_CRU;
1120 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1121 "mfcr $rT, $FXM", SprMFCR>,
1122 PPC970_DGroup_First, PPC970_Unit_CRU;
1124 // Instructions to manipulate FPSCR. Only long double handling uses these.
1125 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1127 let Uses = [RM], Defs = [RM] in {
1128 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1129 "mtfsb0 $FM", IntMTFSB0,
1130 [(PPCmtfsb0 (i32 imm:$FM))]>,
1131 PPC970_DGroup_Single, PPC970_Unit_FPU;
1132 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1133 "mtfsb1 $FM", IntMTFSB0,
1134 [(PPCmtfsb1 (i32 imm:$FM))]>,
1135 PPC970_DGroup_Single, PPC970_Unit_FPU;
1136 // MTFSF does not actually produce an FP result. We pretend it copies
1137 // input reg B to the output. If we didn't do this it would look like the
1138 // instruction had no outputs (because we aren't modelling the FPSCR) and
1139 // it would be deleted.
1140 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1141 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1142 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1143 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1144 F8RC:$rT, F8RC:$FRB))]>,
1145 PPC970_DGroup_Single, PPC970_Unit_FPU;
1146 }
1147 let Uses = [RM] in {
1148 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1149 "mffs $rT", IntMFFS,
1150 [(set F8RC:$rT, (PPCmffs))]>,
1151 PPC970_DGroup_Single, PPC970_Unit_FPU;
1152 def FADDrtz: AForm_2<63, 21,
1153 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1154 "fadd $FRT, $FRA, $FRB", FPGeneral,
1155 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1156 PPC970_DGroup_Single, PPC970_Unit_FPU;
1157 }
1160 let PPC970_Unit = 1 in { // FXU Operations.
1162 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1163 //
1164 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1165 "add $rT, $rA, $rB", IntGeneral,
1166 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1167 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1168 "addc $rT, $rA, $rB", IntGeneral,
1169 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1170 PPC970_DGroup_Cracked;
1171 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1172 "adde $rT, $rA, $rB", IntGeneral,
1173 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1174 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1175 "divw $rT, $rA, $rB", IntDivW,
1176 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1177 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1178 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "divwu $rT, $rA, $rB", IntDivW,
1180 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1181 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1182 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1183 "mulhw $rT, $rA, $rB", IntMulHW,
1184 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1185 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1186 "mulhwu $rT, $rA, $rB", IntMulHWU,
1187 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1188 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1189 "mullw $rT, $rA, $rB", IntMulHW,
1190 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1191 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1192 "subf $rT, $rA, $rB", IntGeneral,
1193 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1194 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1195 "subfc $rT, $rA, $rB", IntGeneral,
1196 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1197 PPC970_DGroup_Cracked;
1198 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1199 "subfe $rT, $rA, $rB", IntGeneral,
1200 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1201 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1202 "addme $rT, $rA", IntGeneral,
1203 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1204 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1205 "addze $rT, $rA", IntGeneral,
1206 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1207 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1208 "neg $rT, $rA", IntGeneral,
1209 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1210 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1211 "subfme $rT, $rA", IntGeneral,
1212 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1213 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1214 "subfze $rT, $rA", IntGeneral,
1215 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1216 }
1218 // A-Form instructions. Most of the instructions executed in the FPU are of
1219 // this type.
1220 //
1221 let PPC970_Unit = 3 in { // FPU Operations.
1222 let Uses = [RM] in {
1223 def FMADD : AForm_1<63, 29,
1224 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1225 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1226 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1227 F8RC:$FRB))]>,
1228 Requires<[FPContractions]>;
1229 def FMADDS : AForm_1<59, 29,
1230 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1231 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1232 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1233 F4RC:$FRB))]>,
1234 Requires<[FPContractions]>;
1235 def FMSUB : AForm_1<63, 28,
1236 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1237 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1238 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1239 F8RC:$FRB))]>,
1240 Requires<[FPContractions]>;
1241 def FMSUBS : AForm_1<59, 28,
1242 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1243 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1244 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1245 F4RC:$FRB))]>,
1246 Requires<[FPContractions]>;
1247 def FNMADD : AForm_1<63, 31,
1248 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1249 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1250 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1251 F8RC:$FRB)))]>,
1252 Requires<[FPContractions]>;
1253 def FNMADDS : AForm_1<59, 31,
1254 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1255 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1256 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1257 F4RC:$FRB)))]>,
1258 Requires<[FPContractions]>;
1259 def FNMSUB : AForm_1<63, 30,
1260 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1261 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1262 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1263 F8RC:$FRB)))]>,
1264 Requires<[FPContractions]>;
1265 def FNMSUBS : AForm_1<59, 30,
1266 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1267 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1268 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1269 F4RC:$FRB)))]>,
1270 Requires<[FPContractions]>;
1271 }
1272 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1273 // having 4 of these, force the comparison to always be an 8-byte double (code
1274 // should use an FMRSD if the input comparison value really wants to be a float)
1275 // and 4/8 byte forms for the result and operand type..
1276 def FSELD : AForm_1<63, 23,
1277 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1278 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1279 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1280 def FSELS : AForm_1<63, 23,
1281 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1282 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1283 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1284 let Uses = [RM] in {
1285 def FADD : AForm_2<63, 21,
1286 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1287 "fadd $FRT, $FRA, $FRB", FPGeneral,
1288 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1289 def FADDS : AForm_2<59, 21,
1290 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1291 "fadds $FRT, $FRA, $FRB", FPGeneral,
1292 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1293 def FDIV : AForm_2<63, 18,
1294 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1295 "fdiv $FRT, $FRA, $FRB", FPDivD,
1296 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1297 def FDIVS : AForm_2<59, 18,
1298 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1299 "fdivs $FRT, $FRA, $FRB", FPDivS,
1300 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1301 def FMUL : AForm_3<63, 25,
1302 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1303 "fmul $FRT, $FRA, $FRB", FPFused,
1304 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1305 def FMULS : AForm_3<59, 25,
1306 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1307 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1308 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1309 def FSUB : AForm_2<63, 20,
1310 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1311 "fsub $FRT, $FRA, $FRB", FPGeneral,
1312 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1313 def FSUBS : AForm_2<59, 20,
1314 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1315 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1316 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1317 }
1318 }
1320 let PPC970_Unit = 1 in { // FXU Operations.
1321 // M-Form instructions. rotate and mask instructions.
1322 //
1323 let isCommutable = 1 in {
1324 // RLWIMI can be commuted if the rotate amount is zero.
1325 def RLWIMI : MForm_2<20,
1326 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1327 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1328 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1329 NoEncode<"$rSi">;
1330 }
1331 def RLWINM : MForm_2<21,
1332 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1333 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1334 []>;
1335 def RLWINMo : MForm_2<21,
1336 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1337 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1338 []>, isDOT, PPC970_DGroup_Cracked;
1339 def RLWNM : MForm_2<23,
1340 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1341 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1342 []>;
1343 }
1346 //===----------------------------------------------------------------------===//
1347 // DWARF Pseudo Instructions
1348 //
1350 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1351 "${:comment} .loc $file, $line, $col",
1352 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1353 (i32 imm:$file))]>;
1355 //===----------------------------------------------------------------------===//
1356 // PowerPC Instruction Patterns
1357 //
1359 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1360 def : Pat<(i32 imm:$imm),
1361 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1363 // Implement the 'not' operation with the NOR instruction.
1364 def NOT : Pat<(not GPRC:$in),
1365 (NOR GPRC:$in, GPRC:$in)>;
1367 // ADD an arbitrary immediate.
1368 def : Pat<(add GPRC:$in, imm:$imm),
1369 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1370 // OR an arbitrary immediate.
1371 def : Pat<(or GPRC:$in, imm:$imm),
1372 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1373 // XOR an arbitrary immediate.
1374 def : Pat<(xor GPRC:$in, imm:$imm),
1375 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1376 // SUBFIC
1377 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1378 (SUBFIC GPRC:$in, imm:$imm)>;
1380 // SHL/SRL
1381 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1382 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1383 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1384 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1386 // ROTL
1387 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1388 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1389 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1390 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1392 // RLWNM
1393 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1394 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1396 // Calls
1397 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1398 (BL_Darwin tglobaladdr:$dst)>;
1399 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1400 (BL_Darwin texternalsym:$dst)>;
1401 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1402 (BL_SVR4 tglobaladdr:$dst)>;
1403 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1404 (BL_SVR4 texternalsym:$dst)>;
1407 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1408 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1410 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1411 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1413 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1414 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1418 // Hi and Lo for Darwin Global Addresses.
1419 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1420 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1421 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1422 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1423 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1424 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1425 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1426 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1427 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1428 (ADDIS GPRC:$in, tconstpool:$g)>;
1429 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1430 (ADDIS GPRC:$in, tjumptable:$g)>;
1432 // Fused negative multiply subtract, alternate pattern
1433 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1434 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1435 Requires<[FPContractions]>;
1436 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1437 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1438 Requires<[FPContractions]>;
1440 // Standard shifts. These are represented separately from the real shifts above
1441 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1442 // amounts.
1443 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1444 (SRAW GPRC:$rS, GPRC:$rB)>;
1445 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1446 (SRW GPRC:$rS, GPRC:$rB)>;
1447 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1448 (SLW GPRC:$rS, GPRC:$rB)>;
1450 def : Pat<(zextloadi1 iaddr:$src),
1451 (LBZ iaddr:$src)>;
1452 def : Pat<(zextloadi1 xaddr:$src),
1453 (LBZX xaddr:$src)>;
1454 def : Pat<(extloadi1 iaddr:$src),
1455 (LBZ iaddr:$src)>;
1456 def : Pat<(extloadi1 xaddr:$src),
1457 (LBZX xaddr:$src)>;
1458 def : Pat<(extloadi8 iaddr:$src),
1459 (LBZ iaddr:$src)>;
1460 def : Pat<(extloadi8 xaddr:$src),
1461 (LBZX xaddr:$src)>;
1462 def : Pat<(extloadi16 iaddr:$src),
1463 (LHZ iaddr:$src)>;
1464 def : Pat<(extloadi16 xaddr:$src),
1465 (LHZX xaddr:$src)>;
1466 def : Pat<(extloadf32 iaddr:$src),
1467 (FMRSD (LFS iaddr:$src))>;
1468 def : Pat<(extloadf32 xaddr:$src),
1469 (FMRSD (LFSX xaddr:$src))>;
1471 // Memory barriers
1472 def : Pat<(membarrier (i32 imm:$ll),
1473 (i32 imm:$ls),
1474 (i32 imm:$sl),
1475 (i32 imm:$ss),
1476 (i32 imm:$device)),
1477 (SYNC)>;
1479 include "PPCInstrAltivec.td"
1480 include "PPCInstr64Bit.td"