lib/Target/ARM/Thumb1RegisterInfo.cpp

   1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARM.h"
  15 #include "ARMAddressingModes.h"
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ARMMachineFunctionInfo.h"
  18 #include "ARMSubtarget.h"
  19 #include "Thumb1InstrInfo.h"
  20 #include "Thumb1RegisterInfo.h"
  21 #include "llvm/Constants.h"
  22 #include "llvm/DerivedTypes.h"
  23 #include "llvm/Function.h"
  24 #include "llvm/LLVMContext.h"
  25 #include "llvm/CodeGen/MachineConstantPool.h"
  26 #include "llvm/CodeGen/MachineFrameInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineInstrBuilder.h"
  29 #include "llvm/CodeGen/MachineLocation.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/Target/TargetFrameInfo.h"
  32 #include "llvm/Target/TargetMachine.h"
  33 #include "llvm/ADT/BitVector.h"
  34 #include "llvm/ADT/SmallVector.h"
  35 #include "llvm/Support/CommandLine.h"
  36 #include "llvm/Support/ErrorHandling.h"
  37 #include "llvm/Support/raw_ostream.h"
  38 using namespace llvm;
  39
  40 static cl::opt<bool>
  41 ThumbRegScavenging("enable-thumb-reg-scavenging",
  42                    cl::Hidden,
  43                    cl::desc("Enable register scavenging on Thumb"));
  44
  45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
  46                                        const ARMSubtarget &sti)
  47   : ARMBaseRegisterInfo(tii, sti) {
  48 }
  49
  50 /// emitLoadConstPool - Emits a load from constpool to materialize the
  51 /// specified immediate.
  52 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
  53                                            MachineBasicBlock::iterator &MBBI,
  54                                            DebugLoc dl,
  55                                            unsigned DestReg, unsigned SubIdx,
  56                                            int Val,
  57                                            ARMCC::CondCodes Pred,
  58                                            unsigned PredReg) const {
  59   MachineFunction &MF = *MBB.getParent();
  60   MachineConstantPool *ConstantPool = MF.getConstantPool();
  61   Constant *C = ConstantInt::get(
  62           Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
  63   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
  64
  65   BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
  66           .addReg(DestReg, getDefRegState(true), SubIdx)
  67           .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
  68 }
  69
  70 const TargetRegisterClass*
  71 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
  72   if (isARMLowRegister(Reg))
  73     return ARM::tGPRRegisterClass;
  74   switch (Reg) {
  75    default:
  76     break;
  77    case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
  78    case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
  79     return ARM::GPRRegisterClass;
  80   }
  81
  82   return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
  83 }
  84
  85 bool
  86 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
  87   return ThumbRegScavenging;
  88 }
  89
  90 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
  91   const MachineFrameInfo *FFI = MF.getFrameInfo();
  92   unsigned CFSize = FFI->getMaxCallFrameSize();
  93   // It's not always a good idea to include the call frame as part of the
  94   // stack frame. ARM (especially Thumb) has small immediate offset to
  95   // address the stack frame. So a large call frame can cause poor codegen
  96   // and may even makes it impossible to scavenge a register.
  97   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
  98     return false;
  99
 100   return !MF.getFrameInfo()->hasVarSizedObjects();
 101 }
 102
 103
 104 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
 105 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
 106 /// in a register using mov / mvn sequences or load the immediate from a
 107 /// constpool entry.
 108 static
 109 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
 110                               MachineBasicBlock::iterator &MBBI,
 111                               unsigned DestReg, unsigned BaseReg,
 112                               int NumBytes, bool CanChangeCC,
 113                               const TargetInstrInfo &TII,
 114                               const Thumb1RegisterInfo& MRI,
 115                               DebugLoc dl) {
 116     bool isHigh = !isARMLowRegister(DestReg) ||
 117                   (BaseReg != 0 && !isARMLowRegister(BaseReg));
 118     bool isSub = false;
 119     // Subtract doesn't have high register version. Load the negative value
 120     // if either base or dest register is a high register. Also, if do not
 121     // issue sub as part of the sequence if condition register is to be
 122     // preserved.
 123     if (NumBytes < 0 && !isHigh && CanChangeCC) {
 124       isSub = true;
 125       NumBytes = -NumBytes;
 126     }
 127     unsigned LdReg = DestReg;
 128     if (DestReg == ARM::SP) {
 129       assert(BaseReg == ARM::SP && "Unexpected!");
 130       LdReg = ARM::R3;
 131       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
 132         .addReg(ARM::R3, RegState::Kill);
 133     }
 134
 135     if (NumBytes <= 255 && NumBytes >= 0)
 136       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
 137         .addImm(NumBytes);
 138     else if (NumBytes < 0 && NumBytes >= -255) {
 139       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
 140         .addImm(NumBytes);
 141       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
 142         .addReg(LdReg, RegState::Kill);
 143     } else
 144       MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
 145
 146     // Emit add / sub.
 147     int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
 148     MachineInstrBuilder MIB =
 149       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
 150     if (Opc != ARM::tADDhirr)
 151       MIB = AddDefaultT1CC(MIB);
 152     if (DestReg == ARM::SP || isSub)
 153       MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
 154     else
 155       MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
 156     AddDefaultPred(MIB);
 157
 158     if (DestReg == ARM::SP)
 159       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
 160         .addReg(ARM::R12, RegState::Kill);
 161 }
 162
 163 /// calcNumMI - Returns the number of instructions required to materialize
 164 /// the specific add / sub r, c instruction.
 165 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
 166                           unsigned NumBits, unsigned Scale) {
 167   unsigned NumMIs = 0;
 168   unsigned Chunk = ((1 << NumBits) - 1) * Scale;
 169
 170   if (Opc == ARM::tADDrSPi) {
 171     unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
 172     Bytes -= ThisVal;
 173     NumMIs++;
 174     NumBits = 8;
 175     Scale = 1;  // Followed by a number of tADDi8.
 176     Chunk = ((1 << NumBits) - 1) * Scale;
 177   }
 178
 179   NumMIs += Bytes / Chunk;
 180   if ((Bytes % Chunk) != 0)
 181     NumMIs++;
 182   if (ExtraOpc)
 183     NumMIs++;
 184   return NumMIs;
 185 }
 186
 187 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
 188 /// a destreg = basereg + immediate in Thumb code.
 189 static
 190 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
 191                                MachineBasicBlock::iterator &MBBI,
 192                                unsigned DestReg, unsigned BaseReg,
 193                                int NumBytes, const TargetInstrInfo &TII,
 194                                const Thumb1RegisterInfo& MRI,
 195                                DebugLoc dl) {
 196   bool isSub = NumBytes < 0;
 197   unsigned Bytes = (unsigned)NumBytes;
 198   if (isSub) Bytes = -NumBytes;
 199   bool isMul4 = (Bytes & 3) == 0;
 200   bool isTwoAddr = false;
 201   bool DstNotEqBase = false;
 202   unsigned NumBits = 1;
 203   unsigned Scale = 1;
 204   int Opc = 0;
 205   int ExtraOpc = 0;
 206   bool NeedCC = false;
 207   bool NeedPred = false;
 208
 209   if (DestReg == BaseReg && BaseReg == ARM::SP) {
 210     assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
 211     NumBits = 7;
 212     Scale = 4;
 213     Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
 214     isTwoAddr = true;
 215   } else if (!isSub && BaseReg == ARM::SP) {
 216     // r1 = add sp, 403
 217     // =>
 218     // r1 = add sp, 100 * 4
 219     // r1 = add r1, 3
 220     if (!isMul4) {
 221       Bytes &= ~3;
 222       ExtraOpc = ARM::tADDi3;
 223     }
 224     NumBits = 8;
 225     Scale = 4;
 226     Opc = ARM::tADDrSPi;
 227   } else {
 228     // sp = sub sp, c
 229     // r1 = sub sp, c
 230     // r8 = sub sp, c
 231     if (DestReg != BaseReg)
 232       DstNotEqBase = true;
 233     NumBits = 8;
 234     if (DestReg == ARM::SP) {
 235       Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
 236       assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
 237       NumBits = 7;
 238       Scale = 4;
 239     } else {
 240       Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
 241       NumBits = 8;
 242       NeedPred = NeedCC = true;
 243     }
 244     isTwoAddr = true;
 245   }
 246
 247   unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
 248   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
 249   if (NumMIs > Threshold) {
 250     // This will expand into too many instructions. Load the immediate from a
 251     // constpool entry.
 252     emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
 253                              MRI, dl);
 254     return;
 255   }
 256
 257   if (DstNotEqBase) {
 258     if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
 259       // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
 260       unsigned Chunk = (1 << 3) - 1;
 261       unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
 262       Bytes -= ThisVal;
 263       const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
 264       const MachineInstrBuilder MIB =
 265         AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
 266       AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
 267     } else {
 268       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
 269         .addReg(BaseReg, RegState::Kill);
 270     }
 271     BaseReg = DestReg;
 272   }
 273
 274   unsigned Chunk = ((1 << NumBits) - 1) * Scale;
 275   while (Bytes) {
 276     unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
 277     Bytes -= ThisVal;
 278     ThisVal /= Scale;
 279     // Build the new tADD / tSUB.
 280     if (isTwoAddr) {
 281       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
 282       if (NeedCC)
 283         MIB = AddDefaultT1CC(MIB);
 284       MIB .addReg(DestReg).addImm(ThisVal);
 285       if (NeedPred)
 286         MIB = AddDefaultPred(MIB);
 287     }
 288     else {
 289       bool isKill = BaseReg != ARM::SP;
 290       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
 291       if (NeedCC)
 292         MIB = AddDefaultT1CC(MIB);
 293       MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
 294       if (NeedPred)
 295         MIB = AddDefaultPred(MIB);
 296       BaseReg = DestReg;
 297
 298       if (Opc == ARM::tADDrSPi) {
 299         // r4 = add sp, imm
 300         // r4 = add r4, imm
 301         // ...
 302         NumBits = 8;
 303         Scale = 1;
 304         Chunk = ((1 << NumBits) - 1) * Scale;
 305         Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
 306         NeedPred = NeedCC = isTwoAddr = true;
 307       }
 308     }
 309   }
 310
 311   if (ExtraOpc) {
 312     const TargetInstrDesc &TID = TII.get(ExtraOpc);
 313     AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
 314                    .addReg(DestReg, RegState::Kill)
 315                    .addImm(((unsigned)NumBytes) & 3));
 316   }
 317 }
 318
 319 static void emitSPUpdate(MachineBasicBlock &MBB,
 320                          MachineBasicBlock::iterator &MBBI,
 321                          const TargetInstrInfo &TII, DebugLoc dl,
 322                          const Thumb1RegisterInfo &MRI,
 323                          int NumBytes) {
 324   emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
 325                             MRI, dl);
 326 }
 327
 328 void Thumb1RegisterInfo::
 329 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 330                               MachineBasicBlock::iterator I) const {
 331   if (!hasReservedCallFrame(MF)) {
 332     // If we have alloca, convert as follows:
 333     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
 334     // ADJCALLSTACKUP   -> add, sp, sp, amount
 335     MachineInstr *Old = I;
 336     DebugLoc dl = Old->getDebugLoc();
 337     unsigned Amount = Old->getOperand(0).getImm();
 338     if (Amount != 0) {
 339       // We need to keep the stack aligned properly.  To do this, we round the
 340       // amount of space needed for the outgoing arguments up to the next
 341       // alignment boundary.
 342       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
 343       Amount = (Amount+Align-1)/Align*Align;
 344
 345       // Replace the pseudo instruction with a new instruction...
 346       unsigned Opc = Old->getOpcode();
 347       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
 348         emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
 349       } else {
 350         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
 351         emitSPUpdate(MBB, I, TII, dl, *this, Amount);
 352       }
 353     }
 354   }
 355   MBB.erase(I);
 356 }
 357
 358 /// emitThumbConstant - Emit a series of instructions to materialize a
 359 /// constant.
 360 static void emitThumbConstant(MachineBasicBlock &MBB,
 361                               MachineBasicBlock::iterator &MBBI,
 362                               unsigned DestReg, int Imm,
 363                               const TargetInstrInfo &TII,
 364                               const Thumb1RegisterInfo& MRI,
 365                               DebugLoc dl) {
 366   bool isSub = Imm < 0;
 367   if (isSub) Imm = -Imm;
 368
 369   int Chunk = (1 << 8) - 1;
 370   int ThisVal = (Imm > Chunk) ? Chunk : Imm;
 371   Imm -= ThisVal;
 372   AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
 373                                         DestReg))
 374                  .addImm(ThisVal));
 375   if (Imm > 0)
 376     emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
 377   if (isSub) {
 378     const TargetInstrDesc &TID = TII.get(ARM::tRSB);
 379     AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
 380                    .addReg(DestReg, RegState::Kill));
 381   }
 382 }
 383
 384 static void removeOperands(MachineInstr &MI, unsigned i) {
 385   unsigned Op = i;
 386   for (unsigned e = MI.getNumOperands(); i != e; ++i)
 387     MI.RemoveOperand(Op);
 388 }
 389
 390 int Thumb1RegisterInfo::
 391 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 392                   unsigned FrameReg, int Offset,
 393                   unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
 394 {
 395   // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
 396   // version then can pull out Thumb1 specific parts here
 397   return 0;
 398 }
 399
 400 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 401                                              int SPAdj, RegScavenger *RS) const{
 402   unsigned i = 0;
 403   MachineInstr &MI = *II;
 404   MachineBasicBlock &MBB = *MI.getParent();
 405   MachineFunction &MF = *MBB.getParent();
 406   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 407   DebugLoc dl = MI.getDebugLoc();
 408
 409   while (!MI.getOperand(i).isFI()) {
 410     ++i;
 411     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 412   }
 413
 414   unsigned FrameReg = ARM::SP;
 415   int FrameIndex = MI.getOperand(i).getIndex();
 416   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
 417                MF.getFrameInfo()->getStackSize() + SPAdj;
 418
 419   if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
 420     Offset -= AFI->getGPRCalleeSavedArea1Offset();
 421   else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
 422     Offset -= AFI->getGPRCalleeSavedArea2Offset();
 423   else if (hasFP(MF)) {
 424     assert(SPAdj == 0 && "Unexpected");
 425     // There is alloca()'s in this function, must reference off the frame
 426     // pointer instead.
 427     FrameReg = getFrameRegister(MF);
 428     Offset -= AFI->getFramePtrSpillOffset();
 429   }
 430
 431   unsigned Opcode = MI.getOpcode();
 432   const TargetInstrDesc &Desc = MI.getDesc();
 433   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
 434
 435   if (Opcode == ARM::tADDrSPi) {
 436     Offset += MI.getOperand(i+1).getImm();
 437
 438     // Can't use tADDrSPi if it's based off the frame pointer.
 439     unsigned NumBits = 0;
 440     unsigned Scale = 1;
 441     if (FrameReg != ARM::SP) {
 442       Opcode = ARM::tADDi3;
 443       MI.setDesc(TII.get(Opcode));
 444       NumBits = 3;
 445     } else {
 446       NumBits = 8;
 447       Scale = 4;
 448       assert((Offset & 3) == 0 &&
 449              "Thumb add/sub sp, #imm immediate must be multiple of 4!");
 450     }
 451
 452     if (Offset == 0) {
 453       // Turn it into a move.
 454       MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
 455       MI.getOperand(i).ChangeToRegister(FrameReg, false);
 456       MI.RemoveOperand(i+1);
 457       return;
 458     }
 459
 460     // Common case: small offset, fits into instruction.
 461     unsigned Mask = (1 << NumBits) - 1;
 462     if (((Offset / Scale) & ~Mask) == 0) {
 463       // Replace the FrameIndex with sp / fp
 464       if (Opcode == ARM::tADDi3) {
 465         removeOperands(MI, i);
 466         MachineInstrBuilder MIB(&MI);
 467         AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
 468                        .addImm(Offset / Scale));
 469       } else {
 470         MI.getOperand(i).ChangeToRegister(FrameReg, false);
 471         MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
 472       }
 473       return;
 474     }
 475
 476     unsigned DestReg = MI.getOperand(0).getReg();
 477     unsigned Bytes = (Offset > 0) ? Offset : -Offset;
 478     unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
 479     // MI would expand into a large number of instructions. Don't try to
 480     // simplify the immediate.
 481     if (NumMIs > 2) {
 482       emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
 483                                 *this, dl);
 484       MBB.erase(II);
 485       return;
 486     }
 487
 488     if (Offset > 0) {
 489       // Translate r0 = add sp, imm to
 490       // r0 = add sp, 255*4
 491       // r0 = add r0, (imm - 255*4)
 492       if (Opcode == ARM::tADDi3) {
 493         removeOperands(MI, i);
 494         MachineInstrBuilder MIB(&MI);
 495         AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
 496       } else {
 497         MI.getOperand(i).ChangeToRegister(FrameReg, false);
 498         MI.getOperand(i+1).ChangeToImmediate(Mask);
 499       }
 500       Offset = (Offset - Mask * Scale);
 501       MachineBasicBlock::iterator NII = next(II);
 502       emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
 503                                 *this, dl);
 504     } else {
 505       // Translate r0 = add sp, -imm to
 506       // r0 = -imm (this is then translated into a series of instructons)
 507       // r0 = add r0, sp
 508       emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
 509
 510       MI.setDesc(TII.get(ARM::tADDhirr));
 511       MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
 512       MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
 513       if (Opcode == ARM::tADDi3) {
 514         MachineInstrBuilder MIB(&MI);
 515         AddDefaultPred(MIB);
 516       }
 517     }
 518     return;
 519   } else {
 520     unsigned ImmIdx = 0;
 521     int InstrOffs = 0;
 522     unsigned NumBits = 0;
 523     unsigned Scale = 1;
 524     switch (AddrMode) {
 525     case ARMII::AddrModeT1_s: {
 526       ImmIdx = i+1;
 527       InstrOffs = MI.getOperand(ImmIdx).getImm();
 528       NumBits = (FrameReg == ARM::SP) ? 8 : 5;
 529       Scale = 4;
 530       break;
 531     }
 532     default:
 533       llvm_unreachable("Unsupported addressing mode!");
 534       break;
 535     }
 536
 537     Offset += InstrOffs * Scale;
 538     assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
 539
 540     // Common case: small offset, fits into instruction.
 541     MachineOperand &ImmOp = MI.getOperand(ImmIdx);
 542     int ImmedOffset = Offset / Scale;
 543     unsigned Mask = (1 << NumBits) - 1;
 544     if ((unsigned)Offset <= Mask * Scale) {
 545       // Replace the FrameIndex with sp
 546       MI.getOperand(i).ChangeToRegister(FrameReg, false);
 547       ImmOp.ChangeToImmediate(ImmedOffset);
 548       return;
 549     }
 550
 551     bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
 552     if (AddrMode == ARMII::AddrModeT1_s) {
 553       // Thumb tLDRspi, tSTRspi. These will change to instructions that use
 554       // a different base register.
 555       NumBits = 5;
 556       Mask = (1 << NumBits) - 1;
 557     }
 558     // If this is a thumb spill / restore, we will be using a constpool load to
 559     // materialize the offset.
 560     if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
 561       ImmOp.ChangeToImmediate(0);
 562     else {
 563       // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
 564       ImmedOffset = ImmedOffset & Mask;
 565       ImmOp.ChangeToImmediate(ImmedOffset);
 566       Offset &= ~(Mask*Scale);
 567     }
 568   }
 569
 570   // If we get here, the immediate doesn't fit into the instruction.  We folded
 571   // as much as possible above, handle the rest, providing a register that is
 572   // SP+LargeImm.
 573   assert(Offset && "This code isn't needed if offset already handled!");
 574
 575   // Remove predicate first.
 576   int PIdx = MI.findFirstPredOperandIdx();
 577   if (PIdx != -1)
 578     removeOperands(MI, PIdx);
 579
 580   if (Desc.mayLoad()) {
 581     // Use the destination register to materialize sp + offset.
 582     unsigned TmpReg = MI.getOperand(0).getReg();
 583     bool UseRR = false;
 584     if (Opcode == ARM::tRestore) {
 585       if (FrameReg == ARM::SP)
 586         emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
 587                                  Offset, false, TII, *this, dl);
 588       else {
 589         emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
 590         UseRR = true;
 591       }
 592     } else {
 593       emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
 594                                 *this, dl);
 595     }
 596
 597     MI.setDesc(TII.get(ARM::tLDR));
 598     MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
 599     if (UseRR)
 600       // Use [reg, reg] addrmode.
 601       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
 602     else  // tLDR has an extra register operand.
 603       MI.addOperand(MachineOperand::CreateReg(0, false));
 604   } else if (Desc.mayStore()) {
 605     // FIXME! This is horrific!!! We need register scavenging.
 606     // Our temporary workaround has marked r3 unavailable. Of course, r3 is
 607     // also a ABI register so it's possible that is is the register that is
 608     // being storing here. If that's the case, we do the following:
 609     // r12 = r2
 610     // Use r2 to materialize sp + offset
 611     // str r3, r2
 612     // r2 = r12
 613     unsigned ValReg = MI.getOperand(0).getReg();
 614     unsigned TmpReg = ARM::R3;
 615     bool UseRR = false;
 616     if (ValReg == ARM::R3) {
 617       BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
 618         .addReg(ARM::R2, RegState::Kill);
 619       TmpReg = ARM::R2;
 620     }
 621     if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
 622       BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
 623         .addReg(ARM::R3, RegState::Kill);
 624     if (Opcode == ARM::tSpill) {
 625       if (FrameReg == ARM::SP)
 626         emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
 627                                  Offset, false, TII, *this, dl);
 628       else {
 629         emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
 630         UseRR = true;
 631       }
 632     } else
 633       emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
 634                                 *this, dl);
 635     MI.setDesc(TII.get(ARM::tSTR));
 636     MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
 637     if (UseRR)  // Use [reg, reg] addrmode.
 638       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
 639     else // tSTR has an extra register operand.
 640       MI.addOperand(MachineOperand::CreateReg(0, false));
 641
 642     MachineBasicBlock::iterator NII = next(II);
 643     if (ValReg == ARM::R3)
 644       BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2)
 645         .addReg(ARM::R12, RegState::Kill);
 646     if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
 647       BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
 648         .addReg(ARM::R12, RegState::Kill);
 649   } else
 650     assert(false && "Unexpected opcode!");
 651
 652   // Add predicate back if it's needed.
 653   if (MI.getDesc().isPredicable()) {
 654     MachineInstrBuilder MIB(&MI);
 655     AddDefaultPred(MIB);
 656   }
 657 }
 658
 659 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
 660   MachineBasicBlock &MBB = MF.front();
 661   MachineBasicBlock::iterator MBBI = MBB.begin();
 662   MachineFrameInfo  *MFI = MF.getFrameInfo();
 663   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 664   unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
 665   unsigned NumBytes = MFI->getStackSize();
 666   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 667   DebugLoc dl = (MBBI != MBB.end() ?
 668                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 669
 670   // Check if R3 is live in. It might have to be used as a scratch register.
 671   for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
 672          E = MF.getRegInfo().livein_end(); I != E; ++I) {
 673     if (I->first == ARM::R3) {
 674       AFI->setR3IsLiveIn(true);
 675       break;
 676     }
 677   }
 678
 679   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
 680   NumBytes = (NumBytes + 3) & ~3;
 681   MFI->setStackSize(NumBytes);
 682
 683   // Determine the sizes of each callee-save spill areas and record which frame
 684   // belongs to which callee-save spill areas.
 685   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
 686   int FramePtrSpillFI = 0;
 687
 688   if (VARegSaveSize)
 689     emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
 690
 691   if (!AFI->hasStackFrame()) {
 692     if (NumBytes != 0)
 693       emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
 694     return;
 695   }
 696
 697   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 698     unsigned Reg = CSI[i].getReg();
 699     int FI = CSI[i].getFrameIdx();
 700     switch (Reg) {
 701     case ARM::R4:
 702     case ARM::R5:
 703     case ARM::R6:
 704     case ARM::R7:
 705     case ARM::LR:
 706       if (Reg == FramePtr)
 707         FramePtrSpillFI = FI;
 708       AFI->addGPRCalleeSavedArea1Frame(FI);
 709       GPRCS1Size += 4;
 710       break;
 711     case ARM::R8:
 712     case ARM::R9:
 713     case ARM::R10:
 714     case ARM::R11:
 715       if (Reg == FramePtr)
 716         FramePtrSpillFI = FI;
 717       if (STI.isTargetDarwin()) {
 718         AFI->addGPRCalleeSavedArea2Frame(FI);
 719         GPRCS2Size += 4;
 720       } else {
 721         AFI->addGPRCalleeSavedArea1Frame(FI);
 722         GPRCS1Size += 4;
 723       }
 724       break;
 725     default:
 726       AFI->addDPRCalleeSavedAreaFrame(FI);
 727       DPRCSSize += 8;
 728     }
 729   }
 730
 731   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
 732     ++MBBI;
 733     if (MBBI != MBB.end())
 734       dl = MBBI->getDebugLoc();
 735   }
 736
 737   // Darwin ABI requires FP to point to the stack slot that contains the
 738   // previous FP.
 739   if (STI.isTargetDarwin() || hasFP(MF)) {
 740     BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
 741       .addFrameIndex(FramePtrSpillFI).addImm(0);
 742   }
 743
 744   // Determine starting offsets of spill areas.
 745   unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
 746   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
 747   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
 748   AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
 749   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
 750   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
 751   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
 752
 753   NumBytes = DPRCSOffset;
 754   if (NumBytes) {
 755     // Insert it after all the callee-save spills.
 756     emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
 757   }
 758
 759   if (STI.isTargetELF() && hasFP(MF)) {
 760     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
 761                              AFI->getFramePtrSpillOffset());
 762   }
 763
 764   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
 765   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
 766   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 767 }
 768
 769 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
 770   for (unsigned i = 0; CSRegs[i]; ++i)
 771     if (Reg == CSRegs[i])
 772       return true;
 773   return false;
 774 }
 775
 776 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
 777   return (MI->getOpcode() == ARM::tRestore &&
 778           MI->getOperand(1).isFI() &&
 779           isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
 780 }
 781
 782 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
 783                                       MachineBasicBlock &MBB) const {
 784   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 785   assert((MBBI->getOpcode() == ARM::tBX_RET ||
 786           MBBI->getOpcode() == ARM::tPOP_RET) &&
 787          "Can only insert epilog into returning blocks");
 788   DebugLoc dl = MBBI->getDebugLoc();
 789   MachineFrameInfo *MFI = MF.getFrameInfo();
 790   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 791   unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
 792   int NumBytes = (int)MFI->getStackSize();
 793
 794   if (!AFI->hasStackFrame()) {
 795     if (NumBytes != 0)
 796       emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
 797   } else {
 798     // Unwind MBBI to point to first LDR / FLDD.
 799     const unsigned *CSRegs = getCalleeSavedRegs();
 800     if (MBBI != MBB.begin()) {
 801       do
 802         --MBBI;
 803       while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
 804       if (!isCSRestore(MBBI, CSRegs))
 805         ++MBBI;
 806     }
 807
 808     // Move SP to start of FP callee save spill area.
 809     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
 810                  AFI->getGPRCalleeSavedArea2Size() +
 811                  AFI->getDPRCalleeSavedAreaSize());
 812
 813     if (hasFP(MF)) {
 814       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
 815       // Reset SP based on frame pointer only if the stack frame extends beyond
 816       // frame pointer stack slot or target is ELF and the function has FP.
 817       if (NumBytes)
 818         emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
 819                                   TII, *this, dl);
 820       else
 821         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
 822           .addReg(FramePtr);
 823     } else {
 824       if (MBBI->getOpcode() == ARM::tBX_RET &&
 825           &MBB.front() != MBBI &&
 826           prior(MBBI)->getOpcode() == ARM::tPOP) {
 827         MachineBasicBlock::iterator PMBBI = prior(MBBI);
 828         emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
 829       } else
 830         emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
 831     }
 832   }
 833
 834   if (VARegSaveSize) {
 835     // Epilogue for vararg functions: pop LR to R3 and branch off it.
 836     // FIXME: Verify this is still ok when R3 is no longer being reserved.
 837     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))).addReg(ARM::R3);
 838
 839     emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
 840
 841     BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
 842     MBB.erase(MBBI);
 843   }
 844 }