we don't want people to override printBasicBlockLabel.
[llvm/avr.git] / include / llvm / Target / TargetRegisterInfo.h
blob80474240f4f8d36f61476f82c74883fab762f520
1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
22 #include <cassert>
23 #include <functional>
25 namespace llvm {
27 class BitVector;
28 class MachineFunction;
29 class MachineMove;
30 class RegScavenger;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
41 /// of AX.
42 ///
43 struct TargetRegisterDesc {
44 const char *AsmName; // Assembly language name for the register
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
52 public:
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const EVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
58 private:
59 unsigned ID;
60 const char *Name;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
67 const int CopyCost;
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
70 public:
71 TargetRegisterClass(unsigned id,
72 const char *name,
73 const EVT *vts,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
84 RegSet.insert(*I);
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
89 ///
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
93 ///
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
97 ///
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
109 return RegsBegin[i];
112 /// contains - Return true if the specified register is included in this
113 /// register class.
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(EVT vt) const {
121 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
122 if (VTs[i] == vt)
123 return true;
124 return false;
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
130 return VTs;
133 vt_iterator vt_end() const {
134 vt_iterator I = VTs;
135 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
136 return I;
139 /// subregclasses_begin / subregclasses_end - Loop over all of
140 /// the subreg register classes of this register class.
141 sc_iterator subregclasses_begin() const {
142 return SubRegClasses;
145 sc_iterator subregclasses_end() const {
146 sc_iterator I = SubRegClasses;
147 while (*I != NULL) ++I;
148 return I;
151 /// getSubRegisterRegClass - Return the register class of subregisters with
152 /// index SubIdx, or NULL if no such class exists.
153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
154 assert(SubIdx>0 && "Invalid subregister index");
155 for (unsigned s = 0; s != SubIdx-1; ++s)
156 if (!SubRegClasses[s])
157 return NULL;
158 return SubRegClasses[SubIdx-1];
161 /// superregclasses_begin / superregclasses_end - Loop over all of
162 /// the superreg register classes of this register class.
163 sc_iterator superregclasses_begin() const {
164 return SuperRegClasses;
167 sc_iterator superregclasses_end() const {
168 sc_iterator I = SuperRegClasses;
169 while (*I != NULL) ++I;
170 return I;
173 /// hasSubClass - return true if the the specified TargetRegisterClass
174 /// is a proper subset of this TargetRegisterClass.
175 bool hasSubClass(const TargetRegisterClass *cs) const {
176 for (int i = 0; SubClasses[i] != NULL; ++i)
177 if (SubClasses[i] == cs)
178 return true;
179 return false;
182 /// subclasses_begin / subclasses_end - Loop over all of the classes
183 /// that are proper subsets of this register class.
184 sc_iterator subclasses_begin() const {
185 return SubClasses;
188 sc_iterator subclasses_end() const {
189 sc_iterator I = SubClasses;
190 while (*I != NULL) ++I;
191 return I;
194 /// hasSuperClass - return true if the specified TargetRegisterClass is a
195 /// proper superset of this TargetRegisterClass.
196 bool hasSuperClass(const TargetRegisterClass *cs) const {
197 for (int i = 0; SuperClasses[i] != NULL; ++i)
198 if (SuperClasses[i] == cs)
199 return true;
200 return false;
203 /// superclasses_begin / superclasses_end - Loop over all of the classes
204 /// that are proper supersets of this register class.
205 sc_iterator superclasses_begin() const {
206 return SuperClasses;
209 sc_iterator superclasses_end() const {
210 sc_iterator I = SuperClasses;
211 while (*I != NULL) ++I;
212 return I;
215 /// isASubClass - return true if this TargetRegisterClass is a subset
216 /// class of at least one other TargetRegisterClass.
217 bool isASubClass() const {
218 return SuperClasses[0] != 0;
221 /// allocation_order_begin/end - These methods define a range of registers
222 /// which specify the registers in this class that are valid to register
223 /// allocate, and the preferred order to allocate them in. For example,
224 /// callee saved registers should be at the end of the list, because it is
225 /// cheaper to allocate caller saved registers.
227 /// These methods take a MachineFunction argument, which can be used to tune
228 /// the allocatable registers based on the characteristics of the function.
229 /// One simple example is that the frame pointer register can be used if
230 /// frame-pointer-elimination is performed.
232 /// By default, these methods return all registers in the class.
234 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
235 return begin();
237 virtual iterator allocation_order_end(const MachineFunction &MF) const {
238 return end();
241 /// getSize - Return the size of the register in bytes, which is also the size
242 /// of a stack slot allocated to hold a spilled copy of this register.
243 unsigned getSize() const { return RegSize; }
245 /// getAlignment - Return the minimum required alignment for a register of
246 /// this class.
247 unsigned getAlignment() const { return Alignment; }
249 /// getCopyCost - Return the cost of copying a value between two registers in
250 /// this class. A negative number means the register class is very expensive
251 /// to copy e.g. status flag register classes.
252 int getCopyCost() const { return CopyCost; }
256 /// TargetRegisterInfo base class - We assume that the target defines a static
257 /// array of TargetRegisterDesc objects that represent all of the machine
258 /// registers that the target has. As such, we simply have to track a pointer
259 /// to this array so that we can turn register number into a register
260 /// descriptor.
262 class TargetRegisterInfo {
263 protected:
264 const unsigned* SubregHash;
265 const unsigned SubregHashSize;
266 const unsigned* SuperregHash;
267 const unsigned SuperregHashSize;
268 const unsigned* AliasesHash;
269 const unsigned AliasesHashSize;
270 public:
271 typedef const TargetRegisterClass * const * regclass_iterator;
272 private:
273 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
274 unsigned NumRegs; // Number of entries in the array
276 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
278 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
279 protected:
280 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
281 regclass_iterator RegClassBegin,
282 regclass_iterator RegClassEnd,
283 int CallFrameSetupOpcode = -1,
284 int CallFrameDestroyOpcode = -1,
285 const unsigned* subregs = 0,
286 const unsigned subregsize = 0,
287 const unsigned* superregs = 0,
288 const unsigned superregsize = 0,
289 const unsigned* aliases = 0,
290 const unsigned aliasessize = 0);
291 virtual ~TargetRegisterInfo();
292 public:
294 enum { // Define some target independent constants
295 /// NoRegister - This physical register is not a real target register. It
296 /// is useful as a sentinal.
297 NoRegister = 0,
299 /// FirstVirtualRegister - This is the first register number that is
300 /// considered to be a 'virtual' register, which is part of the SSA
301 /// namespace. This must be the same for all targets, which means that each
302 /// target is limited to 1024 registers.
303 FirstVirtualRegister = 1024
306 /// isPhysicalRegister - Return true if the specified register number is in
307 /// the physical register namespace.
308 static bool isPhysicalRegister(unsigned Reg) {
309 assert(Reg && "this is not a register!");
310 return Reg < FirstVirtualRegister;
313 /// isVirtualRegister - Return true if the specified register number is in
314 /// the virtual register namespace.
315 static bool isVirtualRegister(unsigned Reg) {
316 assert(Reg && "this is not a register!");
317 return Reg >= FirstVirtualRegister;
320 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
321 /// register of the given type. If type is EVT::Other, then just return any
322 /// register class the register belongs to.
323 virtual const TargetRegisterClass *
324 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
326 /// getAllocatableSet - Returns a bitset indexed by register number
327 /// indicating if a register is allocatable or not. If a register class is
328 /// specified, returns the subset for the class.
329 BitVector getAllocatableSet(MachineFunction &MF,
330 const TargetRegisterClass *RC = NULL) const;
332 const TargetRegisterDesc &operator[](unsigned RegNo) const {
333 assert(RegNo < NumRegs &&
334 "Attempting to access record for invalid register number!");
335 return Desc[RegNo];
338 /// Provide a get method, equivalent to [], but more useful if we have a
339 /// pointer to this object.
341 const TargetRegisterDesc &get(unsigned RegNo) const {
342 return operator[](RegNo);
345 /// getAliasSet - Return the set of registers aliased by the specified
346 /// register, or a null list of there are none. The list returned is zero
347 /// terminated.
349 const unsigned *getAliasSet(unsigned RegNo) const {
350 return get(RegNo).AliasSet;
353 /// getSubRegisters - Return the list of registers that are sub-registers of
354 /// the specified register, or a null list of there are none. The list
355 /// returned is zero terminated and sorted according to super-sub register
356 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
358 const unsigned *getSubRegisters(unsigned RegNo) const {
359 return get(RegNo).SubRegs;
362 /// getSuperRegisters - Return the list of registers that are super-registers
363 /// of the specified register, or a null list of there are none. The list
364 /// returned is zero terminated and sorted according to super-sub register
365 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
367 const unsigned *getSuperRegisters(unsigned RegNo) const {
368 return get(RegNo).SuperRegs;
371 /// getAsmName - Return the symbolic target-specific name for the
372 /// specified physical register.
373 const char *getAsmName(unsigned RegNo) const {
374 return get(RegNo).AsmName;
377 /// getName - Return the human-readable symbolic target-specific name for the
378 /// specified physical register.
379 const char *getName(unsigned RegNo) const {
380 return get(RegNo).Name;
383 /// getNumRegs - Return the number of registers this target has (useful for
384 /// sizing arrays holding per register information)
385 unsigned getNumRegs() const {
386 return NumRegs;
389 /// regsOverlap - Returns true if the two registers are equal or alias each
390 /// other. The registers may be virtual register.
391 bool regsOverlap(unsigned regA, unsigned regB) const {
392 if (regA == regB)
393 return true;
395 if (isVirtualRegister(regA) || isVirtualRegister(regB))
396 return false;
398 // regA and regB are distinct physical registers. Do they alias?
399 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
400 unsigned ProbeAmt = 0;
401 while (AliasesHash[index*2] != 0 &&
402 AliasesHash[index*2+1] != 0) {
403 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
404 return true;
406 index = (index + ProbeAmt) & (AliasesHashSize-1);
407 ProbeAmt += 2;
410 return false;
413 /// isSubRegister - Returns true if regB is a sub-register of regA.
415 bool isSubRegister(unsigned regA, unsigned regB) const {
416 // SubregHash is a simple quadratically probed hash table.
417 size_t index = (regA + regB * 37) & (SubregHashSize-1);
418 unsigned ProbeAmt = 2;
419 while (SubregHash[index*2] != 0 &&
420 SubregHash[index*2+1] != 0) {
421 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
422 return true;
424 index = (index + ProbeAmt) & (SubregHashSize-1);
425 ProbeAmt += 2;
428 return false;
431 /// isSuperRegister - Returns true if regB is a super-register of regA.
433 bool isSuperRegister(unsigned regA, unsigned regB) const {
434 // SuperregHash is a simple quadratically probed hash table.
435 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
436 unsigned ProbeAmt = 2;
437 while (SuperregHash[index*2] != 0 &&
438 SuperregHash[index*2+1] != 0) {
439 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
440 return true;
442 index = (index + ProbeAmt) & (SuperregHashSize-1);
443 ProbeAmt += 2;
446 return false;
449 /// getCalleeSavedRegs - Return a null-terminated list of all of the
450 /// callee saved registers on this target. The register should be in the
451 /// order of desired callee-save stack frame offset. The first register is
452 /// closed to the incoming stack pointer if stack grows down, and vice versa.
453 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
454 const = 0;
456 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
457 /// register classes to spill each callee saved register with. The order and
458 /// length of this list match the getCalleeSaveRegs() list.
459 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
460 const MachineFunction *MF) const =0;
462 /// getReservedRegs - Returns a bitset indexed by physical register number
463 /// indicating if a register is a special register that has particular uses
464 /// and should be considered unavailable at all times, e.g. SP, RA. This is
465 /// used by register scavenger to determine what registers are free.
466 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
468 /// getSubReg - Returns the physical register number of sub-register "Index"
469 /// for physical register RegNo. Return zero if the sub-register does not
470 /// exist.
471 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
473 /// getMatchingSuperReg - Return a super-register of the specified register
474 /// Reg so its sub-register of index SubIdx is Reg.
475 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
476 const TargetRegisterClass *RC) const {
477 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
478 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
479 return SR;
480 return 0;
483 /// getMatchingSuperRegClass - Return a subclass of the specified register
484 /// class A so that each register in it has a sub-register of the
485 /// specified sub-register index which is in the specified register class B.
486 virtual const TargetRegisterClass *
487 getMatchingSuperRegClass(const TargetRegisterClass *A,
488 const TargetRegisterClass *B, unsigned Idx) const {
489 return 0;
492 //===--------------------------------------------------------------------===//
493 // Register Class Information
496 /// Register class iterators
498 regclass_iterator regclass_begin() const { return RegClassBegin; }
499 regclass_iterator regclass_end() const { return RegClassEnd; }
501 unsigned getNumRegClasses() const {
502 return (unsigned)(regclass_end()-regclass_begin());
505 /// getRegClass - Returns the register class associated with the enumeration
506 /// value. See class TargetOperandInfo.
507 const TargetRegisterClass *getRegClass(unsigned i) const {
508 assert(i <= getNumRegClasses() && "Register Class ID out of range");
509 return i ? RegClassBegin[i - 1] : NULL;
512 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
513 /// values. If a target supports multiple different pointer register classes,
514 /// kind specifies which one is indicated.
515 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
516 assert(0 && "Target didn't implement getPointerRegClass!");
517 return 0; // Must return a value in order to compile with VS 2005
520 /// getCrossCopyRegClass - Returns a legal register class to copy a register
521 /// in the specified class to or from. Returns NULL if it is possible to copy
522 /// between a two registers of the specified class.
523 virtual const TargetRegisterClass *
524 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
525 return NULL;
528 /// getAllocationOrder - Returns the register allocation order for a specified
529 /// register class in the form of a pair of TargetRegisterClass iterators.
530 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
531 getAllocationOrder(const TargetRegisterClass *RC,
532 unsigned HintType, unsigned HintReg,
533 const MachineFunction &MF) const {
534 return std::make_pair(RC->allocation_order_begin(MF),
535 RC->allocation_order_end(MF));
538 /// ResolveRegAllocHint - Resolves the specified register allocation hint
539 /// to a physical register. Returns the physical register if it is successful.
540 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
541 const MachineFunction &MF) const {
542 if (Type == 0 && Reg && isPhysicalRegister(Reg))
543 return Reg;
544 return 0;
547 /// UpdateRegAllocHint - A callback to allow target a chance to update
548 /// register allocation hints when a register is "changed" (e.g. coalesced)
549 /// to another register. e.g. On ARM, some virtual registers should target
550 /// register pairs, if one of pair is coalesced to another register, the
551 /// allocation hint of the other half of the pair should be changed to point
552 /// to the new register.
553 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
554 MachineFunction &MF) const {
555 // Do nothing.
558 /// targetHandlesStackFrameRounding - Returns true if the target is
559 /// responsible for rounding up the stack frame (probably at emitPrologue
560 /// time).
561 virtual bool targetHandlesStackFrameRounding() const {
562 return false;
565 /// requiresRegisterScavenging - returns true if the target requires (and can
566 /// make use of) the register scavenger.
567 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
568 return false;
571 /// hasFP - Return true if the specified function should have a dedicated
572 /// frame pointer register. For most targets this is true only if the function
573 /// has variable sized allocas or if frame pointer elimination is disabled.
574 virtual bool hasFP(const MachineFunction &MF) const = 0;
576 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
577 /// not required, we reserve argument space for call sites in the function
578 /// immediately on entry to the current function. This eliminates the need for
579 /// add/sub sp brackets around call sites. Returns true if the call frame is
580 /// included as part of the stack frame.
581 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
582 return !hasFP(MF);
585 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
586 /// the stack frame of the given function for the specified register. e.g. On
587 /// x86, if the frame register is required, the first fixed stack object is
588 /// reserved as its spill slot. This tells PEI not to create a new stack frame
589 /// object for the given register. It should be called only after
590 /// processFunctionBeforeCalleeSavedScan().
591 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
592 int &FrameIdx) const {
593 return false;
596 /// needsStackRealignment - true if storage within the function requires the
597 /// stack pointer to be aligned more than the normal calling convention calls
598 /// for.
599 virtual bool needsStackRealignment(const MachineFunction &MF) const {
600 return false;
603 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
604 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
605 /// targets use pseudo instructions in order to abstract away the difference
606 /// between operating with a frame pointer and operating without, through the
607 /// use of these two instructions.
609 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
610 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
612 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
613 /// code insertion to eliminate call frame setup and destroy pseudo
614 /// instructions (but only if the Target is using them). It is responsible
615 /// for eliminating these instructions, replacing them with concrete
616 /// instructions. This method need only be implemented if using call frame
617 /// setup/destroy pseudo instructions.
619 virtual void
620 eliminateCallFramePseudoInstr(MachineFunction &MF,
621 MachineBasicBlock &MBB,
622 MachineBasicBlock::iterator MI) const {
623 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
624 "eliminateCallFramePseudoInstr must be implemented if using"
625 " call frame setup/destroy pseudo instructions!");
626 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
629 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
630 /// before PrologEpilogInserter scans the physical registers used to determine
631 /// what callee saved registers should be spilled. This method is optional.
632 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
633 RegScavenger *RS = NULL) const {
637 /// processFunctionBeforeFrameFinalized - This method is called immediately
638 /// before the specified functions frame layout (MF.getFrameInfo()) is
639 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
640 /// replaced with direct constants. This method is optional.
642 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
645 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
646 /// frame indices from instructions which may use them. The instruction
647 /// referenced by the iterator contains an MO_FrameIndex operand which must be
648 /// eliminated by this method. This method may modify or replace the
649 /// specified instruction, as long as it keeps the iterator pointing the the
650 /// finished product. SPAdj is the SP adjustment due to call frame setup
651 /// instruction.
652 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
653 int SPAdj, RegScavenger *RS=NULL) const = 0;
655 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
656 /// the function.
657 virtual void emitPrologue(MachineFunction &MF) const = 0;
658 virtual void emitEpilogue(MachineFunction &MF,
659 MachineBasicBlock &MBB) const = 0;
661 //===--------------------------------------------------------------------===//
662 /// Debug information queries.
664 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
665 /// number. Returns -1 if there is no equivalent value. The second
666 /// parameter allows targets to use different numberings for EH info and
667 /// debugging info.
668 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
670 /// getFrameRegister - This method should return the register used as a base
671 /// for values allocated in the current stack frame.
672 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
674 /// getFrameIndexOffset - Returns the displacement from the frame register to
675 /// the stack frame of the specified index.
676 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
678 /// getRARegister - This method should return the register where the return
679 /// address can be found.
680 virtual unsigned getRARegister() const = 0;
682 /// getInitialFrameState - Returns a list of machine moves that are assumed
683 /// on entry to all functions. Note that LabelID is ignored (assumed to be
684 /// the beginning of the function.)
685 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
689 // This is useful when building IndexedMaps keyed on virtual registers
690 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
691 unsigned operator()(unsigned Reg) const {
692 return Reg - TargetRegisterInfo::FirstVirtualRegister;
696 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
697 /// if there is no common subclass.
698 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
699 const TargetRegisterClass *B);
701 } // End llvm namespace
703 #endif