1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "llvm/Support/raw_ostream.h"
21 #include "CodeGenRegisters.h"
22 #include "CodeGenInstruction.h"
30 struct CodeGenRegister
;
33 // SelectionDAG node properties.
34 // SDNPMemOperand: indicates that a node touches memory and therefore must
35 // have an associated memory operand that describes the access.
49 // ComplexPattern attributes.
50 enum CPAttr
{ CPAttrParentAsRoot
};
52 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
53 /// record corresponds to.
54 MVT::SimpleValueType
getValueType(Record
*Rec
);
56 std::string
getName(MVT::SimpleValueType T
);
57 std::string
getEnumName(MVT::SimpleValueType T
);
59 /// getQualifiedName - Return the name of the specified record, with a
60 /// namespace qualifier if the record contains one.
61 std::string
getQualifiedName(const Record
*R
);
63 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
68 mutable std::map
<std::string
, CodeGenInstruction
> Instructions
;
69 mutable std::vector
<CodeGenRegister
> Registers
;
70 mutable std::vector
<CodeGenRegisterClass
> RegisterClasses
;
71 mutable std::vector
<MVT::SimpleValueType
> LegalValueTypes
;
72 void ReadRegisters() const;
73 void ReadRegisterClasses() const;
74 void ReadInstructions() const;
75 void ReadLegalValueTypes() const;
79 Record
*getTargetRecord() const { return TargetRec
; }
80 const std::string
&getName() const;
82 /// getInstNamespace - Return the target-specific instruction namespace.
84 std::string
getInstNamespace() const;
86 /// getInstructionSet - Return the InstructionSet object.
88 Record
*getInstructionSet() const;
90 /// getAsmParser - Return the AssemblyParser definition for this target.
92 Record
*getAsmParser() const;
94 /// getAsmWriter - Return the AssemblyWriter definition for this target.
96 Record
*getAsmWriter() const;
98 const std::vector
<CodeGenRegister
> &getRegisters() const {
99 if (Registers
.empty()) ReadRegisters();
103 const std::vector
<CodeGenRegisterClass
> &getRegisterClasses() const {
104 if (RegisterClasses
.empty()) ReadRegisterClasses();
105 return RegisterClasses
;
108 const CodeGenRegisterClass
&getRegisterClass(Record
*R
) const {
109 const std::vector
<CodeGenRegisterClass
> &RC
= getRegisterClasses();
110 for (unsigned i
= 0, e
= RC
.size(); i
!= e
; ++i
)
111 if (RC
[i
].TheDef
== R
)
113 assert(0 && "Didn't find the register class");
117 /// getRegisterClassForRegister - Find the register class that contains the
118 /// specified physical register. If the register is not in a register
119 /// class, return null. If the register is in multiple classes, and the
120 /// classes have a superset-subset relationship and the same set of
121 /// types, return the superclass. Otherwise return null.
122 const CodeGenRegisterClass
*getRegisterClassForRegister(Record
*R
) const {
123 const std::vector
<CodeGenRegisterClass
> &RCs
= getRegisterClasses();
124 const CodeGenRegisterClass
*FoundRC
= 0;
125 for (unsigned i
= 0, e
= RCs
.size(); i
!= e
; ++i
) {
126 const CodeGenRegisterClass
&RC
= RegisterClasses
[i
];
127 for (unsigned ei
= 0, ee
= RC
.Elements
.size(); ei
!= ee
; ++ei
) {
128 if (R
!= RC
.Elements
[ei
])
131 // If a register's classes have different types, return null.
132 if (FoundRC
&& RC
.getValueTypes() != FoundRC
->getValueTypes())
135 // If this is the first class that contains the register,
136 // make a note of it and go on to the next class.
142 std::vector
<Record
*> Elements(RC
.Elements
);
143 std::vector
<Record
*> FoundElements(FoundRC
->Elements
);
144 std::sort(Elements
.begin(), Elements
.end());
145 std::sort(FoundElements
.begin(), FoundElements
.end());
147 // Check to see if the previously found class that contains
148 // the register is a subclass of the current class. If so,
149 // prefer the superclass.
150 if (std::includes(Elements
.begin(), Elements
.end(),
151 FoundElements
.begin(), FoundElements
.end())) {
156 // Check to see if the previously found class that contains
157 // the register is a superclass of the current class. If so,
158 // prefer the superclass.
159 if (std::includes(FoundElements
.begin(), FoundElements
.end(),
160 Elements
.begin(), Elements
.end()))
163 // Multiple classes, and neither is a superclass of the other.
171 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
172 /// specified physical register.
173 std::vector
<unsigned char> getRegisterVTs(Record
*R
) const;
175 const std::vector
<MVT::SimpleValueType
> &getLegalValueTypes() const {
176 if (LegalValueTypes
.empty()) ReadLegalValueTypes();
177 return LegalValueTypes
;
180 /// isLegalValueType - Return true if the specified value type is natively
181 /// supported by the target (i.e. there are registers that directly hold it).
182 bool isLegalValueType(MVT::SimpleValueType VT
) const {
183 const std::vector
<MVT::SimpleValueType
> &LegalVTs
= getLegalValueTypes();
184 for (unsigned i
= 0, e
= LegalVTs
.size(); i
!= e
; ++i
)
185 if (LegalVTs
[i
] == VT
) return true;
189 /// getInstructions - Return all of the instructions defined for this target.
191 const std::map
<std::string
, CodeGenInstruction
> &getInstructions() const {
192 if (Instructions
.empty()) ReadInstructions();
195 std::map
<std::string
, CodeGenInstruction
> &getInstructions() {
196 if (Instructions
.empty()) ReadInstructions();
200 CodeGenInstruction
&getInstruction(const std::string
&Name
) const {
201 const std::map
<std::string
, CodeGenInstruction
> &Insts
= getInstructions();
202 assert(Insts
.count(Name
) && "Not an instruction!");
203 return const_cast<CodeGenInstruction
&>(Insts
.find(Name
)->second
);
206 typedef std::map
<std::string
,
207 CodeGenInstruction
>::const_iterator inst_iterator
;
208 inst_iterator
inst_begin() const { return getInstructions().begin(); }
209 inst_iterator
inst_end() const { return Instructions
.end(); }
211 /// getInstructionsByEnumValue - Return all of the instructions defined by the
212 /// target, ordered by their enum value.
213 void getInstructionsByEnumValue(std::vector
<const CodeGenInstruction
*>
214 &NumberedInstructions
);
217 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
219 bool isLittleEndianEncoding() const;
222 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
223 /// tablegen class in TargetSelectionDAG.td
224 class ComplexPattern
{
225 MVT::SimpleValueType Ty
;
226 unsigned NumOperands
;
227 std::string SelectFunc
;
228 std::vector
<Record
*> RootNodes
;
229 unsigned Properties
; // Node properties
230 unsigned Attributes
; // Pattern attributes
232 ComplexPattern() : NumOperands(0) {};
233 ComplexPattern(Record
*R
);
235 MVT::SimpleValueType
getValueType() const { return Ty
; }
236 unsigned getNumOperands() const { return NumOperands
; }
237 const std::string
&getSelectFunc() const { return SelectFunc
; }
238 const std::vector
<Record
*> &getRootNodes() const {
241 bool hasProperty(enum SDNP Prop
) const { return Properties
& (1 << Prop
); }
242 bool hasAttribute(enum CPAttr Attr
) const { return Attributes
& (1 << Attr
); }
245 } // End llvm namespace