utils/TableGen/InstrInfoEmitter.cpp

   1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This tablegen backend is responsible for emitting a description of the target
  11 // instruction set for the code generator.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "InstrInfoEmitter.h"
  16 #include "CodeGenTarget.h"
  17 #include "Record.h"
  18 #include "llvm/ADT/StringExtras.h"
  19 #include <algorithm>
  20 using namespace llvm;
  21
  22 static void PrintDefList(const std::vector<Record*> &Uses,
  23                          unsigned Num, raw_ostream &OS) {
  24   OS << "static const unsigned ImplicitList" << Num << "[] = { ";
  25   for (unsigned i = 0, e = Uses.size(); i != e; ++i)
  26     OS << getQualifiedName(Uses[i]) << ", ";
  27   OS << "0 };\n";
  28 }
  29
  30 static void PrintBarriers(std::vector<Record*> &Barriers,
  31                           unsigned Num, raw_ostream &OS) {
  32   OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
  33   for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
  34     OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
  35   OS << "NULL };\n";
  36 }
  37
  38 //===----------------------------------------------------------------------===//
  39 // Instruction Itinerary Information.
  40 //===----------------------------------------------------------------------===//
  41
  42 struct RecordNameComparator {
  43   bool operator()(const Record *Rec1, const Record *Rec2) const {
  44     return Rec1->getName() < Rec2->getName();
  45   }
  46 };
  47
  48 void InstrInfoEmitter::GatherItinClasses() {
  49   std::vector<Record*> DefList =
  50   Records.getAllDerivedDefinitions("InstrItinClass");
  51   std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
  52
  53   for (unsigned i = 0, N = DefList.size(); i < N; i++)
  54     ItinClassMap[DefList[i]->getName()] = i;
  55 }
  56
  57 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
  58   return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
  59 }
  60
  61 //===----------------------------------------------------------------------===//
  62 // Operand Info Emission.
  63 //===----------------------------------------------------------------------===//
  64
  65 std::vector<std::string>
  66 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
  67   std::vector<std::string> Result;
  68
  69   for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
  70     // Handle aggregate operands and normal operands the same way by expanding
  71     // either case into a list of operands for this op.
  72     std::vector<CodeGenInstruction::OperandInfo> OperandList;
  73
  74     // This might be a multiple operand thing.  Targets like X86 have
  75     // registers in their multi-operand operands.  It may also be an anonymous
  76     // operand, which has a single operand, but no declared class for the
  77     // operand.
  78     DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
  79
  80     if (!MIOI || MIOI->getNumArgs() == 0) {
  81       // Single, anonymous, operand.
  82       OperandList.push_back(Inst.OperandList[i]);
  83     } else {
  84       for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
  85         OperandList.push_back(Inst.OperandList[i]);
  86
  87         Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
  88         OperandList.back().Rec = OpR;
  89       }
  90     }
  91
  92     for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
  93       Record *OpR = OperandList[j].Rec;
  94       std::string Res;
  95
  96       if (OpR->isSubClassOf("RegisterClass"))
  97         Res += getQualifiedName(OpR) + "RegClassID, ";
  98       else if (OpR->isSubClassOf("PointerLikeRegClass"))
  99         Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
 100       else
 101         Res += "0, ";
 102
 103       // Fill in applicable flags.
 104       Res += "0";
 105
 106       // Ptr value whose register class is resolved via callback.
 107       if (OpR->isSubClassOf("PointerLikeRegClass"))
 108         Res += "|(1<<TOI::LookupPtrRegClass)";
 109
 110       // Predicate operands.  Check to see if the original unexpanded operand
 111       // was of type PredicateOperand.
 112       if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
 113         Res += "|(1<<TOI::Predicate)";
 114
 115       // Optional def operands.  Check to see if the original unexpanded operand
 116       // was of type OptionalDefOperand.
 117       if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
 118         Res += "|(1<<TOI::OptionalDef)";
 119
 120       // Fill in constraint info.
 121       Res += ", " + Inst.OperandList[i].Constraints[j];
 122       Result.push_back(Res);
 123     }
 124   }
 125
 126   return Result;
 127 }
 128
 129 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
 130                                        OperandInfoMapTy &OperandInfoIDs) {
 131   // ID #0 is for no operand info.
 132   unsigned OperandListNum = 0;
 133   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 134
 135   OS << "\n";
 136   const CodeGenTarget &Target = CDP.getTargetInfo();
 137   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
 138        E = Target.inst_end(); II != E; ++II) {
 139     std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
 140     unsigned &N = OperandInfoIDs[OperandInfo];
 141     if (N != 0) continue;
 142
 143     N = ++OperandListNum;
 144     OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
 145     for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
 146       OS << "{ " << OperandInfo[i] << " }, ";
 147     OS << "};\n";
 148   }
 149 }
 150
 151 void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
 152                                   const std::vector<CodeGenRegisterClass> &RCs,
 153                                   std::vector<Record*> &Barriers) {
 154   std::set<Record*> DefSet;
 155   unsigned NumDefs = Defs.size();
 156   for (unsigned i = 0; i < NumDefs; ++i)
 157     DefSet.insert(Defs[i]);
 158
 159   for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
 160     const CodeGenRegisterClass &RC = RCs[i];
 161     unsigned NumRegs = RC.Elements.size();
 162     if (NumRegs > NumDefs)
 163       continue; // Can't possibly clobber this RC.
 164
 165     bool Clobber = true;
 166     for (unsigned j = 0; j < NumRegs; ++j) {
 167       Record *Reg = RC.Elements[j];
 168       if (!DefSet.count(Reg)) {
 169         Clobber = false;
 170         break;
 171       }
 172     }
 173     if (Clobber)
 174       Barriers.push_back(RC.TheDef);
 175   }
 176 }
 177
 178 //===----------------------------------------------------------------------===//
 179 // Main Output.
 180 //===----------------------------------------------------------------------===//
 181
 182 // run - Emit the main instruction description records for the target...
 183 void InstrInfoEmitter::run(raw_ostream &OS) {
 184   GatherItinClasses();
 185
 186   EmitSourceFileHeader("Target Instruction Descriptors", OS);
 187   OS << "namespace llvm {\n\n";
 188
 189   CodeGenTarget &Target = CDP.getTargetInfo();
 190   const std::string &TargetName = Target.getName();
 191   Record *InstrInfo = Target.getInstructionSet();
 192   const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
 193
 194   // Keep track of all of the def lists we have emitted already.
 195   std::map<std::vector<Record*>, unsigned> EmittedLists;
 196   unsigned ListNumber = 0;
 197   std::map<std::vector<Record*>, unsigned> EmittedBarriers;
 198   unsigned BarrierNumber = 0;
 199   std::map<Record*, unsigned> BarriersMap;
 200
 201   // Emit all of the instruction's implicit uses and defs.
 202   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
 203          E = Target.inst_end(); II != E; ++II) {
 204     Record *Inst = II->second.TheDef;
 205     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
 206     if (!Uses.empty()) {
 207       unsigned &IL = EmittedLists[Uses];
 208       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
 209     }
 210     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
 211     if (!Defs.empty()) {
 212       std::vector<Record*> RCBarriers;
 213       DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
 214       if (!RCBarriers.empty()) {
 215         unsigned &IB = EmittedBarriers[RCBarriers];
 216         if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
 217         BarriersMap.insert(std::make_pair(Inst, IB));
 218       }
 219
 220       unsigned &IL = EmittedLists[Defs];
 221       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
 222     }
 223   }
 224
 225   OperandInfoMapTy OperandInfoIDs;
 226
 227   // Emit all of the operand info records.
 228   EmitOperandInfo(OS, OperandInfoIDs);
 229
 230   // Emit all of the TargetInstrDesc records in their ENUM ordering.
 231   //
 232   OS << "\nstatic const TargetInstrDesc " << TargetName
 233      << "Insts[] = {\n";
 234   std::vector<const CodeGenInstruction*> NumberedInstructions;
 235   Target.getInstructionsByEnumValue(NumberedInstructions);
 236
 237   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
 238     emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
 239                BarriersMap, OperandInfoIDs, OS);
 240   OS << "};\n";
 241   OS << "} // End llvm namespace \n";
 242 }
 243
 244 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 245                                   Record *InstrInfo,
 246                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
 247                                   std::map<Record*, unsigned> &BarriersMap,
 248                                   const OperandInfoMapTy &OpInfo,
 249                                   raw_ostream &OS) {
 250   int MinOperands = 0;
 251   if (!Inst.OperandList.empty())
 252     // Each logical operand can be multiple MI operands.
 253     MinOperands = Inst.OperandList.back().MIOperandNo +
 254                   Inst.OperandList.back().MINumOperands;
 255
 256   OS << "  { ";
 257   OS << Num << ",\t" << MinOperands << ",\t"
 258      << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
 259      << ",\t\"" << Inst.TheDef->getName() << "\", 0";
 260
 261   // Emit all of the target indepedent flags...
 262   if (Inst.isReturn)           OS << "|(1<<TID::Return)";
 263   if (Inst.isBranch)           OS << "|(1<<TID::Branch)";
 264   if (Inst.isIndirectBranch)   OS << "|(1<<TID::IndirectBranch)";
 265   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
 266   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
 267   if (Inst.isCall)             OS << "|(1<<TID::Call)";
 268   if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
 269   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
 270   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
 271   if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";
 272   if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
 273   if (Inst.isCommutable)       OS << "|(1<<TID::Commutable)";
 274   if (Inst.isTerminator)       OS << "|(1<<TID::Terminator)";
 275   if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
 276   if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
 277   if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
 278   if (Inst.usesCustomDAGSchedInserter)
 279     OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
 280   if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
 281   if (Inst.hasSideEffects)     OS << "|(1<<TID::UnmodeledSideEffects)";
 282   if (Inst.isAsCheapAsAMove)   OS << "|(1<<TID::CheapAsAMove)";
 283   OS << ", 0";
 284
 285   // Emit all of the target-specific flags...
 286   ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
 287   ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
 288   if (LI->getSize() != Shift->getSize())
 289     throw "Lengths of " + InstrInfo->getName() +
 290           ":(TargetInfoFields, TargetInfoPositions) must be equal!";
 291
 292   for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
 293     emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
 294                      dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
 295
 296   OS << ", ";
 297
 298   // Emit the implicit uses and defs lists...
 299   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
 300   if (UseList.empty())
 301     OS << "NULL, ";
 302   else
 303     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 304
 305   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
 306   if (DefList.empty())
 307     OS << "NULL, ";
 308   else
 309     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 310
 311   std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
 312   if (BI == BarriersMap.end())
 313     OS << "NULL, ";
 314   else
 315     OS << "Barriers" << BI->second << ", ";
 316
 317   // Emit the operand info.
 318   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
 319   if (OperandInfo.empty())
 320     OS << "0";
 321   else
 322     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 323
 324   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 325 }
 326
 327
 328 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
 329                                         IntInit *ShiftInt, raw_ostream &OS) {
 330   if (Val == 0 || ShiftInt == 0)
 331     throw std::string("Illegal value or shift amount in TargetInfo*!");
 332   RecordVal *RV = R->getValue(Val->getValue());
 333   int Shift = ShiftInt->getValue();
 334
 335   if (RV == 0 || RV->getValue() == 0) {
 336     // This isn't an error if this is a builtin instruction.
 337     if (R->getName() != "PHI" &&
 338         R->getName() != "INLINEASM" &&
 339         R->getName() != "DBG_LABEL" &&
 340         R->getName() != "EH_LABEL" &&
 341         R->getName() != "GC_LABEL" &&
 342         R->getName() != "DECLARE" &&
 343         R->getName() != "EXTRACT_SUBREG" &&
 344         R->getName() != "INSERT_SUBREG" &&
 345         R->getName() != "IMPLICIT_DEF" &&
 346         R->getName() != "SUBREG_TO_REG" &&
 347         R->getName() != "COPY_TO_REGCLASS")
 348       throw R->getName() + " doesn't have a field named '" +
 349             Val->getValue() + "'!";
 350     return;
 351   }
 352
 353   Init *Value = RV->getValue();
 354   if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
 355     if (BI->getValue()) OS << "|(1<<" << Shift << ")";
 356     return;
 357   } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
 358     // Convert the Bits to an integer to print...
 359     Init *I = BI->convertInitializerTo(new IntRecTy());
 360     if (I)
 361       if (IntInit *II = dynamic_cast<IntInit*>(I)) {
 362         if (II->getValue()) {
 363           if (Shift)
 364             OS << "|(" << II->getValue() << "<<" << Shift << ")";
 365           else
 366             OS << "|" << II->getValue();
 367         }
 368         return;
 369       }
 370
 371   } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
 372     if (II->getValue()) {
 373       if (Shift)
 374         OS << "|(" << II->getValue() << "<<" << Shift << ")";
 375       else
 376         OS << II->getValue();
 377     }
 378     return;
 379   }
 380
 381   errs() << "Unhandled initializer: " << *Val << "\n";
 382   throw "In record '" + R->getName() + "' for TSFlag emission.";
 383 }
 384