lib/Target/ARM/ARMBaseInstrInfo.cpp

   1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInstrInfo.h"
  15 #include "ARM.h"
  16 #include "ARMAddressingModes.h"
  17 #include "ARMGenInstrInfo.inc"
  18 #include "ARMMachineFunctionInfo.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/CodeGen/LiveVariables.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  24 #include "llvm/MC/MCAsmInfo.h"
  25 #include "llvm/Support/CommandLine.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 using namespace llvm;
  28
  29 static cl::opt<bool>
  30 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
  31                cl::desc("Enable ARM 2-addr to 3-addr conv"));
  32
  33 ARMBaseInstrInfo::ARMBaseInstrInfo()
  34   : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
  35 }
  36
  37 MachineInstr *
  38 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
  39                                         MachineBasicBlock::iterator &MBBI,
  40                                         LiveVariables *LV) const {
  41   // FIXME: Thumb2 support.
  42
  43   if (!EnableARM3Addr)
  44     return NULL;
  45
  46   MachineInstr *MI = MBBI;
  47   MachineFunction &MF = *MI->getParent()->getParent();
  48   unsigned TSFlags = MI->getDesc().TSFlags;
  49   bool isPre = false;
  50   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
  51   default: return NULL;
  52   case ARMII::IndexModePre:
  53     isPre = true;
  54     break;
  55   case ARMII::IndexModePost:
  56     break;
  57   }
  58
  59   // Try splitting an indexed load/store to an un-indexed one plus an add/sub
  60   // operation.
  61   unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
  62   if (MemOpc == 0)
  63     return NULL;
  64
  65   MachineInstr *UpdateMI = NULL;
  66   MachineInstr *MemMI = NULL;
  67   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
  68   const TargetInstrDesc &TID = MI->getDesc();
  69   unsigned NumOps = TID.getNumOperands();
  70   bool isLoad = !TID.mayStore();
  71   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
  72   const MachineOperand &Base = MI->getOperand(2);
  73   const MachineOperand &Offset = MI->getOperand(NumOps-3);
  74   unsigned WBReg = WB.getReg();
  75   unsigned BaseReg = Base.getReg();
  76   unsigned OffReg = Offset.getReg();
  77   unsigned OffImm = MI->getOperand(NumOps-2).getImm();
  78   ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
  79   switch (AddrMode) {
  80   default:
  81     assert(false && "Unknown indexed op!");
  82     return NULL;
  83   case ARMII::AddrMode2: {
  84     bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
  85     unsigned Amt = ARM_AM::getAM2Offset(OffImm);
  86     if (OffReg == 0) {
  87       if (ARM_AM::getSOImmVal(Amt) == -1)
  88         // Can't encode it in a so_imm operand. This transformation will
  89         // add more than 1 instruction. Abandon!
  90         return NULL;
  91       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
  92                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
  93         .addReg(BaseReg).addImm(Amt)
  94         .addImm(Pred).addReg(0).addReg(0);
  95     } else if (Amt != 0) {
  96       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
  97       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
  98       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
  99                          get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
 100         .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
 101         .addImm(Pred).addReg(0).addReg(0);
 102     } else
 103       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
 104                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
 105         .addReg(BaseReg).addReg(OffReg)
 106         .addImm(Pred).addReg(0).addReg(0);
 107     break;
 108   }
 109   case ARMII::AddrMode3 : {
 110     bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
 111     unsigned Amt = ARM_AM::getAM3Offset(OffImm);
 112     if (OffReg == 0)
 113       // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
 114       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
 115                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
 116         .addReg(BaseReg).addImm(Amt)
 117         .addImm(Pred).addReg(0).addReg(0);
 118     else
 119       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
 120                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
 121         .addReg(BaseReg).addReg(OffReg)
 122         .addImm(Pred).addReg(0).addReg(0);
 123     break;
 124   }
 125   }
 126
 127   std::vector<MachineInstr*> NewMIs;
 128   if (isPre) {
 129     if (isLoad)
 130       MemMI = BuildMI(MF, MI->getDebugLoc(),
 131                       get(MemOpc), MI->getOperand(0).getReg())
 132         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
 133     else
 134       MemMI = BuildMI(MF, MI->getDebugLoc(),
 135                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
 136         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
 137     NewMIs.push_back(MemMI);
 138     NewMIs.push_back(UpdateMI);
 139   } else {
 140     if (isLoad)
 141       MemMI = BuildMI(MF, MI->getDebugLoc(),
 142                       get(MemOpc), MI->getOperand(0).getReg())
 143         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
 144     else
 145       MemMI = BuildMI(MF, MI->getDebugLoc(),
 146                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
 147         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
 148     if (WB.isDead())
 149       UpdateMI->getOperand(0).setIsDead();
 150     NewMIs.push_back(UpdateMI);
 151     NewMIs.push_back(MemMI);
 152   }
 153
 154   // Transfer LiveVariables states, kill / dead info.
 155   if (LV) {
 156     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 157       MachineOperand &MO = MI->getOperand(i);
 158       if (MO.isReg() && MO.getReg() &&
 159           TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
 160         unsigned Reg = MO.getReg();
 161
 162         LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
 163         if (MO.isDef()) {
 164           MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
 165           if (MO.isDead())
 166             LV->addVirtualRegisterDead(Reg, NewMI);
 167         }
 168         if (MO.isUse() && MO.isKill()) {
 169           for (unsigned j = 0; j < 2; ++j) {
 170             // Look at the two new MI's in reverse order.
 171             MachineInstr *NewMI = NewMIs[j];
 172             if (!NewMI->readsRegister(Reg))
 173               continue;
 174             LV->addVirtualRegisterKilled(Reg, NewMI);
 175             if (VI.removeKill(MI))
 176               VI.Kills.push_back(NewMI);
 177             break;
 178           }
 179         }
 180       }
 181     }
 182   }
 183
 184   MFI->insert(MBBI, NewMIs[1]);
 185   MFI->insert(MBBI, NewMIs[0]);
 186   return NewMIs[0];
 187 }
 188
 189 // Branch analysis.
 190 bool
 191 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 192                                 MachineBasicBlock *&FBB,
 193                                 SmallVectorImpl<MachineOperand> &Cond,
 194                                 bool AllowModify) const {
 195   // If the block has no terminators, it just falls into the block after it.
 196   MachineBasicBlock::iterator I = MBB.end();
 197   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 198     return false;
 199
 200   // Get the last instruction in the block.
 201   MachineInstr *LastInst = I;
 202
 203   // If there is only one terminator instruction, process it.
 204   unsigned LastOpc = LastInst->getOpcode();
 205   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 206     if (isUncondBranchOpcode(LastOpc)) {
 207       TBB = LastInst->getOperand(0).getMBB();
 208       return false;
 209     }
 210     if (isCondBranchOpcode(LastOpc)) {
 211       // Block ends with fall-through condbranch.
 212       TBB = LastInst->getOperand(0).getMBB();
 213       Cond.push_back(LastInst->getOperand(1));
 214       Cond.push_back(LastInst->getOperand(2));
 215       return false;
 216     }
 217     return true;  // Can't handle indirect branch.
 218   }
 219
 220   // Get the instruction before it if it is a terminator.
 221   MachineInstr *SecondLastInst = I;
 222
 223   // If there are three terminators, we don't know what sort of block this is.
 224   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
 225     return true;
 226
 227   // If the block ends with a B and a Bcc, handle it.
 228   unsigned SecondLastOpc = SecondLastInst->getOpcode();
 229   if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
 230     TBB =  SecondLastInst->getOperand(0).getMBB();
 231     Cond.push_back(SecondLastInst->getOperand(1));
 232     Cond.push_back(SecondLastInst->getOperand(2));
 233     FBB = LastInst->getOperand(0).getMBB();
 234     return false;
 235   }
 236
 237   // If the block ends with two unconditional branches, handle it.  The second
 238   // one is not executed, so remove it.
 239   if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
 240     TBB = SecondLastInst->getOperand(0).getMBB();
 241     I = LastInst;
 242     if (AllowModify)
 243       I->eraseFromParent();
 244     return false;
 245   }
 246
 247   // ...likewise if it ends with a branch table followed by an unconditional
 248   // branch. The branch folder can create these, and we must get rid of them for
 249   // correctness of Thumb constant islands.
 250   if (isJumpTableBranchOpcode(SecondLastOpc) &&
 251       isUncondBranchOpcode(LastOpc)) {
 252     I = LastInst;
 253     if (AllowModify)
 254       I->eraseFromParent();
 255     return true;
 256   }
 257
 258   // Otherwise, can't handle this.
 259   return true;
 260 }
 261
 262
 263 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 264   MachineBasicBlock::iterator I = MBB.end();
 265   if (I == MBB.begin()) return 0;
 266   --I;
 267   if (!isUncondBranchOpcode(I->getOpcode()) &&
 268       !isCondBranchOpcode(I->getOpcode()))
 269     return 0;
 270
 271   // Remove the branch.
 272   I->eraseFromParent();
 273
 274   I = MBB.end();
 275
 276   if (I == MBB.begin()) return 1;
 277   --I;
 278   if (!isCondBranchOpcode(I->getOpcode()))
 279     return 1;
 280
 281   // Remove the branch.
 282   I->eraseFromParent();
 283   return 2;
 284 }
 285
 286 unsigned
 287 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 288                                MachineBasicBlock *FBB,
 289                              const SmallVectorImpl<MachineOperand> &Cond) const {
 290   // FIXME this should probably have a DebugLoc argument
 291   DebugLoc dl = DebugLoc::getUnknownLoc();
 292
 293   ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
 294   int BOpc   = !AFI->isThumbFunction()
 295     ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
 296   int BccOpc = !AFI->isThumbFunction()
 297     ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
 298
 299   // Shouldn't be a fall through.
 300   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 301   assert((Cond.size() == 2 || Cond.size() == 0) &&
 302          "ARM branch conditions have two components!");
 303
 304   if (FBB == 0) {
 305     if (Cond.empty()) // Unconditional branch?
 306       BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
 307     else
 308       BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
 309         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
 310     return 1;
 311   }
 312
 313   // Two-way conditional branch.
 314   BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
 315     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
 316   BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
 317   return 2;
 318 }
 319
 320 bool ARMBaseInstrInfo::
 321 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 322   ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
 323   Cond[0].setImm(ARMCC::getOppositeCondition(CC));
 324   return false;
 325 }
 326
 327 bool ARMBaseInstrInfo::
 328 PredicateInstruction(MachineInstr *MI,
 329                      const SmallVectorImpl<MachineOperand> &Pred) const {
 330   unsigned Opc = MI->getOpcode();
 331   if (isUncondBranchOpcode(Opc)) {
 332     MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
 333     MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
 334     MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
 335     return true;
 336   }
 337
 338   int PIdx = MI->findFirstPredOperandIdx();
 339   if (PIdx != -1) {
 340     MachineOperand &PMO = MI->getOperand(PIdx);
 341     PMO.setImm(Pred[0].getImm());
 342     MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
 343     return true;
 344   }
 345   return false;
 346 }
 347
 348 bool ARMBaseInstrInfo::
 349 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 350                   const SmallVectorImpl<MachineOperand> &Pred2) const {
 351   if (Pred1.size() > 2 || Pred2.size() > 2)
 352     return false;
 353
 354   ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
 355   ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
 356   if (CC1 == CC2)
 357     return true;
 358
 359   switch (CC1) {
 360   default:
 361     return false;
 362   case ARMCC::AL:
 363     return true;
 364   case ARMCC::HS:
 365     return CC2 == ARMCC::HI;
 366   case ARMCC::LS:
 367     return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
 368   case ARMCC::GE:
 369     return CC2 == ARMCC::GT;
 370   case ARMCC::LE:
 371     return CC2 == ARMCC::LT;
 372   }
 373 }
 374
 375 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
 376                                     std::vector<MachineOperand> &Pred) const {
 377   // FIXME: This confuses implicit_def with optional CPSR def.
 378   const TargetInstrDesc &TID = MI->getDesc();
 379   if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
 380     return false;
 381
 382   bool Found = false;
 383   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 384     const MachineOperand &MO = MI->getOperand(i);
 385     if (MO.isReg() && MO.getReg() == ARM::CPSR) {
 386       Pred.push_back(MO);
 387       Found = true;
 388     }
 389   }
 390
 391   return Found;
 392 }
 393
 394
 395 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
 396 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
 397                                 unsigned JTI) DISABLE_INLINE;
 398 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
 399                                 unsigned JTI) {
 400   return JT[JTI].MBBs.size();
 401 }
 402
 403 /// GetInstSize - Return the size of the specified MachineInstr.
 404 ///
 405 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
 406   const MachineBasicBlock &MBB = *MI->getParent();
 407   const MachineFunction *MF = MBB.getParent();
 408   const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
 409
 410   // Basic size info comes from the TSFlags field.
 411   const TargetInstrDesc &TID = MI->getDesc();
 412   unsigned TSFlags = TID.TSFlags;
 413
 414   unsigned Opc = MI->getOpcode();
 415   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
 416   default: {
 417     // If this machine instr is an inline asm, measure it.
 418     if (MI->getOpcode() == ARM::INLINEASM)
 419       return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
 420     if (MI->isLabel())
 421       return 0;
 422     switch (Opc) {
 423     default:
 424       llvm_unreachable("Unknown or unset size field for instr!");
 425     case TargetInstrInfo::IMPLICIT_DEF:
 426     case TargetInstrInfo::DBG_LABEL:
 427     case TargetInstrInfo::EH_LABEL:
 428       return 0;
 429     }
 430     break;
 431   }
 432   case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
 433   case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
 434   case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
 435   case ARMII::SizeSpecial: {
 436     switch (Opc) {
 437     case ARM::CONSTPOOL_ENTRY:
 438       // If this machine instr is a constant pool entry, its size is recorded as
 439       // operand #2.
 440       return MI->getOperand(2).getImm();
 441     case ARM::Int_eh_sjlj_setjmp:
 442       return 24;
 443     case ARM::t2Int_eh_sjlj_setjmp:
 444       return 20;
 445     case ARM::BR_JTr:
 446     case ARM::BR_JTm:
 447     case ARM::BR_JTadd:
 448     case ARM::tBR_JTr:
 449     case ARM::t2BR_JT:
 450     case ARM::t2TBB:
 451     case ARM::t2TBH: {
 452       // These are jumptable branches, i.e. a branch followed by an inlined
 453       // jumptable. The size is 4 + 4 * number of entries. For TBB, each
 454       // entry is one byte; TBH two byte each.
 455       unsigned EntrySize = (Opc == ARM::t2TBB)
 456         ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
 457       unsigned NumOps = TID.getNumOperands();
 458       MachineOperand JTOP =
 459         MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
 460       unsigned JTI = JTOP.getIndex();
 461       const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
 462       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
 463       assert(JTI < JT.size());
 464       // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
 465       // 4 aligned. The assembler / linker may add 2 byte padding just before
 466       // the JT entries.  The size does not include this padding; the
 467       // constant islands pass does separate bookkeeping for it.
 468       // FIXME: If we know the size of the function is less than (1 << 16) *2
 469       // bytes, we can use 16-bit entries instead. Then there won't be an
 470       // alignment issue.
 471       unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
 472       unsigned NumEntries = getNumJTEntries(JT, JTI);
 473       if (Opc == ARM::t2TBB && (NumEntries & 1))
 474         // Make sure the instruction that follows TBB is 2-byte aligned.
 475         // FIXME: Constant island pass should insert an "ALIGN" instruction
 476         // instead.
 477         ++NumEntries;
 478       return NumEntries * EntrySize + InstSize;
 479     }
 480     default:
 481       // Otherwise, pseudo-instruction sizes are zero.
 482       return 0;
 483     }
 484   }
 485   }
 486   return 0; // Not reached
 487 }
 488
 489 /// Return true if the instruction is a register to register move and
 490 /// leave the source and dest operands in the passed parameters.
 491 ///
 492 bool
 493 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
 494                               unsigned &SrcReg, unsigned &DstReg,
 495                               unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
 496   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
 497
 498   switch (MI.getOpcode()) {
 499   default: break;
 500   case ARM::FCPYS:
 501   case ARM::FCPYD:
 502   case ARM::VMOVD:
 503   case  ARM::VMOVQ: {
 504     SrcReg = MI.getOperand(1).getReg();
 505     DstReg = MI.getOperand(0).getReg();
 506     return true;
 507   }
 508   case ARM::MOVr:
 509   case ARM::tMOVr:
 510   case ARM::tMOVgpr2tgpr:
 511   case ARM::tMOVtgpr2gpr:
 512   case ARM::tMOVgpr2gpr:
 513   case ARM::t2MOVr: {
 514     assert(MI.getDesc().getNumOperands() >= 2 &&
 515            MI.getOperand(0).isReg() &&
 516            MI.getOperand(1).isReg() &&
 517            "Invalid ARM MOV instruction");
 518     SrcReg = MI.getOperand(1).getReg();
 519     DstReg = MI.getOperand(0).getReg();
 520     return true;
 521   }
 522   }
 523
 524   return false;
 525 }
 526
 527 unsigned
 528 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
 529                                       int &FrameIndex) const {
 530   switch (MI->getOpcode()) {
 531   default: break;
 532   case ARM::LDR:
 533   case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
 534     if (MI->getOperand(1).isFI() &&
 535         MI->getOperand(2).isReg() &&
 536         MI->getOperand(3).isImm() &&
 537         MI->getOperand(2).getReg() == 0 &&
 538         MI->getOperand(3).getImm() == 0) {
 539       FrameIndex = MI->getOperand(1).getIndex();
 540       return MI->getOperand(0).getReg();
 541     }
 542     break;
 543   case ARM::t2LDRi12:
 544   case ARM::tRestore:
 545     if (MI->getOperand(1).isFI() &&
 546         MI->getOperand(2).isImm() &&
 547         MI->getOperand(2).getImm() == 0) {
 548       FrameIndex = MI->getOperand(1).getIndex();
 549       return MI->getOperand(0).getReg();
 550     }
 551     break;
 552   case ARM::FLDD:
 553   case ARM::FLDS:
 554     if (MI->getOperand(1).isFI() &&
 555         MI->getOperand(2).isImm() &&
 556         MI->getOperand(2).getImm() == 0) {
 557       FrameIndex = MI->getOperand(1).getIndex();
 558       return MI->getOperand(0).getReg();
 559     }
 560     break;
 561   }
 562
 563   return 0;
 564 }
 565
 566 unsigned
 567 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
 568                                      int &FrameIndex) const {
 569   switch (MI->getOpcode()) {
 570   default: break;
 571   case ARM::STR:
 572   case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
 573     if (MI->getOperand(1).isFI() &&
 574         MI->getOperand(2).isReg() &&
 575         MI->getOperand(3).isImm() &&
 576         MI->getOperand(2).getReg() == 0 &&
 577         MI->getOperand(3).getImm() == 0) {
 578       FrameIndex = MI->getOperand(1).getIndex();
 579       return MI->getOperand(0).getReg();
 580     }
 581     break;
 582   case ARM::t2STRi12:
 583   case ARM::tSpill:
 584     if (MI->getOperand(1).isFI() &&
 585         MI->getOperand(2).isImm() &&
 586         MI->getOperand(2).getImm() == 0) {
 587       FrameIndex = MI->getOperand(1).getIndex();
 588       return MI->getOperand(0).getReg();
 589     }
 590     break;
 591   case ARM::FSTD:
 592   case ARM::FSTS:
 593     if (MI->getOperand(1).isFI() &&
 594         MI->getOperand(2).isImm() &&
 595         MI->getOperand(2).getImm() == 0) {
 596       FrameIndex = MI->getOperand(1).getIndex();
 597       return MI->getOperand(0).getReg();
 598     }
 599     break;
 600   }
 601
 602   return 0;
 603 }
 604
 605 bool
 606 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 607                                MachineBasicBlock::iterator I,
 608                                unsigned DestReg, unsigned SrcReg,
 609                                const TargetRegisterClass *DestRC,
 610                                const TargetRegisterClass *SrcRC) const {
 611   DebugLoc DL = DebugLoc::getUnknownLoc();
 612   if (I != MBB.end()) DL = I->getDebugLoc();
 613
 614   if (DestRC != SrcRC) {
 615     // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
 616     if (DestRC == ARM::DPRRegisterClass) {
 617       if (SrcRC == ARM::DPR_VFP2RegisterClass ||
 618           SrcRC == ARM::DPR_8RegisterClass) {
 619       } else
 620         return false;
 621     } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
 622       if (SrcRC == ARM::DPRRegisterClass ||
 623           SrcRC == ARM::DPR_8RegisterClass) {
 624       } else
 625         return false;
 626     } else if (DestRC == ARM::DPR_8RegisterClass) {
 627       if (SrcRC == ARM::DPRRegisterClass ||
 628           SrcRC == ARM::DPR_VFP2RegisterClass) {
 629       } else
 630         return false;
 631     } else
 632       return false;
 633   }
 634
 635   if (DestRC == ARM::GPRRegisterClass) {
 636     AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
 637                                         DestReg).addReg(SrcReg)));
 638   } else if (DestRC == ARM::SPRRegisterClass) {
 639     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
 640                    .addReg(SrcReg));
 641   } else if ((DestRC == ARM::DPRRegisterClass) ||
 642              (DestRC == ARM::DPR_VFP2RegisterClass) ||
 643              (DestRC == ARM::DPR_8RegisterClass)) {
 644     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
 645                    .addReg(SrcReg));
 646   } else if (DestRC == ARM::QPRRegisterClass) {
 647     BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
 648   } else {
 649     return false;
 650   }
 651
 652   return true;
 653 }
 654
 655 void ARMBaseInstrInfo::
 656 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 657                     unsigned SrcReg, bool isKill, int FI,
 658                     const TargetRegisterClass *RC) const {
 659   DebugLoc DL = DebugLoc::getUnknownLoc();
 660   if (I != MBB.end()) DL = I->getDebugLoc();
 661
 662   if (RC == ARM::GPRRegisterClass) {
 663     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
 664                    .addReg(SrcReg, getKillRegState(isKill))
 665                    .addFrameIndex(FI).addReg(0).addImm(0));
 666   } else if (RC == ARM::DPRRegisterClass ||
 667              RC == ARM::DPR_VFP2RegisterClass ||
 668              RC == ARM::DPR_8RegisterClass) {
 669     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
 670                    .addReg(SrcReg, getKillRegState(isKill))
 671                    .addFrameIndex(FI).addImm(0));
 672   } else if (RC == ARM::SPRRegisterClass) {
 673     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
 674                    .addReg(SrcReg, getKillRegState(isKill))
 675                    .addFrameIndex(FI).addImm(0));
 676   } else {
 677     assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
 678     // FIXME: Neon instructions should support predicates
 679     BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
 680       .addFrameIndex(FI).addImm(0);
 681   }
 682 }
 683
 684 void ARMBaseInstrInfo::
 685 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 686                      unsigned DestReg, int FI,
 687                      const TargetRegisterClass *RC) const {
 688   DebugLoc DL = DebugLoc::getUnknownLoc();
 689   if (I != MBB.end()) DL = I->getDebugLoc();
 690
 691   if (RC == ARM::GPRRegisterClass) {
 692     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
 693                    .addFrameIndex(FI).addReg(0).addImm(0));
 694   } else if (RC == ARM::DPRRegisterClass ||
 695              RC == ARM::DPR_VFP2RegisterClass ||
 696              RC == ARM::DPR_8RegisterClass) {
 697     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
 698                    .addFrameIndex(FI).addImm(0));
 699   } else if (RC == ARM::SPRRegisterClass) {
 700     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
 701                    .addFrameIndex(FI).addImm(0));
 702   } else {
 703     assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
 704     // FIXME: Neon instructions should support predicates
 705     BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0);
 706   }
 707 }
 708
 709 MachineInstr *ARMBaseInstrInfo::
 710 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
 711                       const SmallVectorImpl<unsigned> &Ops, int FI) const {
 712   if (Ops.size() != 1) return NULL;
 713
 714   unsigned OpNum = Ops[0];
 715   unsigned Opc = MI->getOpcode();
 716   MachineInstr *NewMI = NULL;
 717   if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
 718     // If it is updating CPSR, then it cannot be folded.
 719     if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
 720       return NULL;
 721     unsigned Pred = MI->getOperand(2).getImm();
 722     unsigned PredReg = MI->getOperand(3).getReg();
 723     if (OpNum == 0) { // move -> store
 724       unsigned SrcReg = MI->getOperand(1).getReg();
 725       bool isKill = MI->getOperand(1).isKill();
 726       bool isUndef = MI->getOperand(1).isUndef();
 727       if (Opc == ARM::MOVr)
 728         NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
 729           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 730           .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
 731       else // ARM::t2MOVr
 732         NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
 733           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 734           .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
 735     } else {          // move -> load
 736       unsigned DstReg = MI->getOperand(0).getReg();
 737       bool isDead = MI->getOperand(0).isDead();
 738       bool isUndef = MI->getOperand(0).isUndef();
 739       if (Opc == ARM::MOVr)
 740         NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
 741           .addReg(DstReg,
 742                   RegState::Define |
 743                   getDeadRegState(isDead) |
 744                   getUndefRegState(isUndef))
 745           .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
 746       else // ARM::t2MOVr
 747         NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
 748           .addReg(DstReg,
 749                   RegState::Define |
 750                   getDeadRegState(isDead) |
 751                   getUndefRegState(isUndef))
 752           .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
 753     }
 754   } else if (Opc == ARM::tMOVgpr2gpr ||
 755              Opc == ARM::tMOVtgpr2gpr ||
 756              Opc == ARM::tMOVgpr2tgpr) {
 757     if (OpNum == 0) { // move -> store
 758       unsigned SrcReg = MI->getOperand(1).getReg();
 759       bool isKill = MI->getOperand(1).isKill();
 760       bool isUndef = MI->getOperand(1).isUndef();
 761       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
 762         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 763         .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
 764     } else {          // move -> load
 765       unsigned DstReg = MI->getOperand(0).getReg();
 766       bool isDead = MI->getOperand(0).isDead();
 767       bool isUndef = MI->getOperand(0).isUndef();
 768       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
 769         .addReg(DstReg,
 770                 RegState::Define |
 771                 getDeadRegState(isDead) |
 772                 getUndefRegState(isUndef))
 773         .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
 774     }
 775   } else if (Opc == ARM::FCPYS) {
 776     unsigned Pred = MI->getOperand(2).getImm();
 777     unsigned PredReg = MI->getOperand(3).getReg();
 778     if (OpNum == 0) { // move -> store
 779       unsigned SrcReg = MI->getOperand(1).getReg();
 780       bool isKill = MI->getOperand(1).isKill();
 781       bool isUndef = MI->getOperand(1).isUndef();
 782       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
 783         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 784         .addFrameIndex(FI)
 785         .addImm(0).addImm(Pred).addReg(PredReg);
 786     } else {          // move -> load
 787       unsigned DstReg = MI->getOperand(0).getReg();
 788       bool isDead = MI->getOperand(0).isDead();
 789       bool isUndef = MI->getOperand(0).isUndef();
 790       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
 791         .addReg(DstReg,
 792                 RegState::Define |
 793                 getDeadRegState(isDead) |
 794                 getUndefRegState(isUndef))
 795         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
 796     }
 797   }
 798   else if (Opc == ARM::FCPYD) {
 799     unsigned Pred = MI->getOperand(2).getImm();
 800     unsigned PredReg = MI->getOperand(3).getReg();
 801     if (OpNum == 0) { // move -> store
 802       unsigned SrcReg = MI->getOperand(1).getReg();
 803       bool isKill = MI->getOperand(1).isKill();
 804       bool isUndef = MI->getOperand(1).isUndef();
 805       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
 806         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 807         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
 808     } else {          // move -> load
 809       unsigned DstReg = MI->getOperand(0).getReg();
 810       bool isDead = MI->getOperand(0).isDead();
 811       bool isUndef = MI->getOperand(0).isUndef();
 812       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
 813         .addReg(DstReg,
 814                 RegState::Define |
 815                 getDeadRegState(isDead) |
 816                 getUndefRegState(isUndef))
 817         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
 818     }
 819   }
 820
 821   return NewMI;
 822 }
 823
 824 MachineInstr*
 825 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 826                                         MachineInstr* MI,
 827                                         const SmallVectorImpl<unsigned> &Ops,
 828                                         MachineInstr* LoadMI) const {
 829   // FIXME
 830   return 0;
 831 }
 832
 833 bool
 834 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
 835                                    const SmallVectorImpl<unsigned> &Ops) const {
 836   if (Ops.size() != 1) return false;
 837
 838   unsigned Opc = MI->getOpcode();
 839   if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
 840     // If it is updating CPSR, then it cannot be folded.
 841     return MI->getOperand(4).getReg() != ARM::CPSR ||
 842       MI->getOperand(4).isDead();
 843   } else if (Opc == ARM::tMOVgpr2gpr ||
 844              Opc == ARM::tMOVtgpr2gpr ||
 845              Opc == ARM::tMOVgpr2tgpr) {
 846     return true;
 847   } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
 848     return true;
 849   } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
 850     return false; // FIXME
 851   }
 852
 853   return false;
 854 }
 855
 856 /// getInstrPredicate - If instruction is predicated, returns its predicate
 857 /// condition, otherwise returns AL. It also returns the condition code
 858 /// register by reference.
 859 ARMCC::CondCodes llvm::getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
 860   int PIdx = MI->findFirstPredOperandIdx();
 861   if (PIdx == -1) {
 862     PredReg = 0;
 863     return ARMCC::AL;
 864   }
 865
 866   PredReg = MI->getOperand(PIdx+1).getReg();
 867   return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
 868 }
 869
 870
 871 int llvm::getMatchingCondBranchOpcode(int Opc) {
 872   if (Opc == ARM::B)
 873     return ARM::Bcc;
 874   else if (Opc == ARM::tB)
 875     return ARM::tBcc;
 876   else if (Opc == ARM::t2B)
 877       return ARM::t2Bcc;
 878
 879   llvm_unreachable("Unknown unconditional branch opcode!");
 880   return 0;
 881 }
 882
 883
 884 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
 885                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 886                                unsigned DestReg, unsigned BaseReg, int NumBytes,
 887                                ARMCC::CondCodes Pred, unsigned PredReg,
 888                                const ARMBaseInstrInfo &TII) {
 889   bool isSub = NumBytes < 0;
 890   if (isSub) NumBytes = -NumBytes;
 891
 892   while (NumBytes) {
 893     unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
 894     unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
 895     assert(ThisVal && "Didn't extract field correctly");
 896
 897     // We will handle these bits from offset, clear them.
 898     NumBytes &= ~ThisVal;
 899
 900     assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
 901
 902     // Build the new ADD / SUB.
 903     unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
 904     BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
 905       .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
 906       .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
 907     BaseReg = DestReg;
 908   }
 909 }
 910
 911 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 912                                 unsigned FrameReg, int &Offset,
 913                                 const ARMBaseInstrInfo &TII) {
 914   unsigned Opcode = MI.getOpcode();
 915   const TargetInstrDesc &Desc = MI.getDesc();
 916   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
 917   bool isSub = false;
 918
 919   // Memory operands in inline assembly always use AddrMode2.
 920   if (Opcode == ARM::INLINEASM)
 921     AddrMode = ARMII::AddrMode2;
 922
 923   if (Opcode == ARM::ADDri) {
 924     Offset += MI.getOperand(FrameRegIdx+1).getImm();
 925     if (Offset == 0) {
 926       // Turn it into a move.
 927       MI.setDesc(TII.get(ARM::MOVr));
 928       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 929       MI.RemoveOperand(FrameRegIdx+1);
 930       Offset = 0;
 931       return true;
 932     } else if (Offset < 0) {
 933       Offset = -Offset;
 934       isSub = true;
 935       MI.setDesc(TII.get(ARM::SUBri));
 936     }
 937
 938     // Common case: small offset, fits into instruction.
 939     if (ARM_AM::getSOImmVal(Offset) != -1) {
 940       // Replace the FrameIndex with sp / fp
 941       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 942       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
 943       Offset = 0;
 944       return true;
 945     }
 946
 947     // Otherwise, pull as much of the immedidate into this ADDri/SUBri
 948     // as possible.
 949     unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
 950     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
 951
 952     // We will handle these bits from offset, clear them.
 953     Offset &= ~ThisImmVal;
 954
 955     // Get the properly encoded SOImmVal field.
 956     assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
 957            "Bit extraction didn't work?");
 958     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
 959  } else {
 960     unsigned ImmIdx = 0;
 961     int InstrOffs = 0;
 962     unsigned NumBits = 0;
 963     unsigned Scale = 1;
 964     switch (AddrMode) {
 965     case ARMII::AddrMode2: {
 966       ImmIdx = FrameRegIdx+2;
 967       InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
 968       if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
 969         InstrOffs *= -1;
 970       NumBits = 12;
 971       break;
 972     }
 973     case ARMII::AddrMode3: {
 974       ImmIdx = FrameRegIdx+2;
 975       InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
 976       if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
 977         InstrOffs *= -1;
 978       NumBits = 8;
 979       break;
 980     }
 981     case ARMII::AddrMode4:
 982       // Can't fold any offset even if it's zero.
 983       return false;
 984     case ARMII::AddrMode5: {
 985       ImmIdx = FrameRegIdx+1;
 986       InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
 987       if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
 988         InstrOffs *= -1;
 989       NumBits = 8;
 990       Scale = 4;
 991       break;
 992     }
 993     default:
 994       llvm_unreachable("Unsupported addressing mode!");
 995       break;
 996     }
 997
 998     Offset += InstrOffs * Scale;
 999     assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1000     if (Offset < 0) {
1001       Offset = -Offset;
1002       isSub = true;
1003     }
1004
1005     // Attempt to fold address comp. if opcode has offset bits
1006     if (NumBits > 0) {
1007       // Common case: small offset, fits into instruction.
1008       MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1009       int ImmedOffset = Offset / Scale;
1010       unsigned Mask = (1 << NumBits) - 1;
1011       if ((unsigned)Offset <= Mask * Scale) {
1012         // Replace the FrameIndex with sp
1013         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1014         if (isSub)
1015           ImmedOffset |= 1 << NumBits;
1016         ImmOp.ChangeToImmediate(ImmedOffset);
1017         Offset = 0;
1018         return true;
1019       }
1020
1021       // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1022       ImmedOffset = ImmedOffset & Mask;
1023       if (isSub)
1024         ImmedOffset |= 1 << NumBits;
1025       ImmOp.ChangeToImmediate(ImmedOffset);
1026       Offset &= ~(Mask*Scale);
1027     }
1028   }
1029
1030   Offset = (isSub) ? -Offset : Offset;
1031   return Offset == 0;
1032 }