lib/Target/ARM/ARMBaseRegisterInfo.h

   1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the base ARM implementation of TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMBASEREGISTERINFO_H
  15 #define ARMBASEREGISTERINFO_H
  16
  17 #include "ARM.h"
  18 #include "llvm/Target/TargetRegisterInfo.h"
  19 #include "ARMGenRegisterInfo.h.inc"
  20
  21 namespace llvm {
  22   class ARMSubtarget;
  23   class ARMBaseInstrInfo;
  24   class Type;
  25
  26 /// Register allocation hints.
  27 namespace ARMRI {
  28   enum {
  29     RegPairOdd  = 1,
  30     RegPairEven = 2
  31   };
  32 }
  33
  34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
  35 ///
  36 static inline bool isARMLowRegister(unsigned Reg) {
  37   using namespace ARM;
  38   switch (Reg) {
  39   case R0:  case R1:  case R2:  case R3:
  40   case R4:  case R5:  case R6:  case R7:
  41     return true;
  42   default:
  43     return false;
  44   }
  45 }
  46
  47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
  48 protected:
  49   const ARMBaseInstrInfo &TII;
  50   const ARMSubtarget &STI;
  51
  52   /// FramePtr - ARM physical register used as frame ptr.
  53   unsigned FramePtr;
  54
  55   // Can be only subclassed.
  56   explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
  57                                const ARMSubtarget &STI);
  58
  59   // Return the opcode that implements 'Op', or 0 if no opcode
  60   unsigned getOpcode(int Op) const;
  61
  62 public:
  63   /// getRegisterNumbering - Given the enum value for some register, e.g.
  64   /// ARM::LR, return the number that it corresponds to (e.g. 14). It
  65   /// also returns true in isSPVFP if the register is a single precision
  66   /// VFP register.
  67   static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
  68
  69   /// Code Generation virtual methods...
  70   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
  71
  72   const TargetRegisterClass* const*
  73   getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
  74
  75   BitVector getReservedRegs(const MachineFunction &MF) const;
  76
  77   const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
  78
  79   std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
  80   getAllocationOrder(const TargetRegisterClass *RC,
  81                      unsigned HintType, unsigned HintReg,
  82                      const MachineFunction &MF) const;
  83
  84   unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
  85                                const MachineFunction &MF) const;
  86
  87   void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
  88                           MachineFunction &MF) const;
  89
  90   bool hasFP(const MachineFunction &MF) const;
  91
  92   bool cannotEliminateFrame(const MachineFunction &MF) const;
  93
  94   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
  95                                             RegScavenger *RS = NULL) const;
  96
  97   // Debug information queries.
  98   unsigned getRARegister() const;
  99   unsigned getFrameRegister(MachineFunction &MF) const;
 100
 101   // Exception handling queries.
 102   unsigned getEHExceptionRegister() const;
 103   unsigned getEHHandlerRegister() const;
 104
 105   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
 106
 107   bool isLowRegister(unsigned Reg) const;
 108
 109
 110   /// emitLoadConstPool - Emits a load from constpool to materialize the
 111   /// specified immediate.
 112   virtual void emitLoadConstPool(MachineBasicBlock &MBB,
 113                                  MachineBasicBlock::iterator &MBBI,
 114                                  DebugLoc dl,
 115                                  unsigned DestReg, unsigned SubIdx,
 116                                  int Val,
 117                                  ARMCC::CondCodes Pred = ARMCC::AL,
 118                                  unsigned PredReg = 0) const;
 119
 120   /// Code Generation virtual methods...
 121   virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
 122
 123   virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
 124
 125   virtual bool hasReservedCallFrame(MachineFunction &MF) const;
 126
 127   virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
 128                                              MachineBasicBlock &MBB,
 129                                              MachineBasicBlock::iterator I) const;
 130
 131   virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
 132                                    int SPAdj, RegScavenger *RS = NULL) const;
 133
 134   virtual void emitPrologue(MachineFunction &MF) const;
 135   virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 136
 137 private:
 138   unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
 139
 140   unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
 141
 142   unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
 143 };
 144
 145 } // end namespace llvm
 146
 147 #endif