lib/Target/ARM/ARMSchedule.td

   1 //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 //===----------------------------------------------------------------------===//
  11 // Functional units across ARM processors
  12 //
  13 def FU_Issue   : FuncUnit; // issue
  14 def FU_Pipe0   : FuncUnit; // pipeline 0
  15 def FU_Pipe1   : FuncUnit; // pipeline 1
  16 def FU_LdSt0   : FuncUnit; // pipeline 0 load/store
  17 def FU_LdSt1   : FuncUnit; // pipeline 1 load/store
  18
  19 //===----------------------------------------------------------------------===//
  20 // Instruction Itinerary classes used for ARM
  21 //
  22 def IIC_iALUx      : InstrItinClass;
  23 def IIC_iALUi      : InstrItinClass;
  24 def IIC_iALUr      : InstrItinClass;
  25 def IIC_iALUsi     : InstrItinClass;
  26 def IIC_iALUsr     : InstrItinClass;
  27 def IIC_iUNAr      : InstrItinClass;
  28 def IIC_iUNAsi     : InstrItinClass;
  29 def IIC_iUNAsr     : InstrItinClass;
  30 def IIC_iCMPi      : InstrItinClass;
  31 def IIC_iCMPr      : InstrItinClass;
  32 def IIC_iCMPsi     : InstrItinClass;
  33 def IIC_iCMPsr     : InstrItinClass;
  34 def IIC_iMOVi      : InstrItinClass;
  35 def IIC_iMOVr      : InstrItinClass;
  36 def IIC_iMOVsi     : InstrItinClass;
  37 def IIC_iMOVsr     : InstrItinClass;
  38 def IIC_iCMOVi     : InstrItinClass;
  39 def IIC_iCMOVr     : InstrItinClass;
  40 def IIC_iCMOVsi    : InstrItinClass;
  41 def IIC_iCMOVsr    : InstrItinClass;
  42 def IIC_iMUL16     : InstrItinClass;
  43 def IIC_iMAC16     : InstrItinClass;
  44 def IIC_iMUL32     : InstrItinClass;
  45 def IIC_iMAC32     : InstrItinClass;
  46 def IIC_iMUL64     : InstrItinClass;
  47 def IIC_iMAC64     : InstrItinClass;
  48 def IIC_iLoadi     : InstrItinClass;
  49 def IIC_iLoadr     : InstrItinClass;
  50 def IIC_iLoadsi    : InstrItinClass;
  51 def IIC_iLoadiu    : InstrItinClass;
  52 def IIC_iLoadru    : InstrItinClass;
  53 def IIC_iLoadsiu   : InstrItinClass;
  54 def IIC_iLoadm     : InstrItinClass;
  55 def IIC_iStorei    : InstrItinClass;
  56 def IIC_iStorer    : InstrItinClass;
  57 def IIC_iStoresi   : InstrItinClass;
  58 def IIC_iStoreiu   : InstrItinClass;
  59 def IIC_iStoreru   : InstrItinClass;
  60 def IIC_iStoresiu  : InstrItinClass;
  61 def IIC_iStorem    : InstrItinClass;
  62 def IIC_fpALU      : InstrItinClass;
  63 def IIC_fpMPY      : InstrItinClass;
  64 def IIC_fpLoad     : InstrItinClass;
  65 def IIC_fpStore    : InstrItinClass;
  66 def IIC_Br         : InstrItinClass;
  67
  68 //===----------------------------------------------------------------------===//
  69 // Processor instruction itineraries.
  70
  71 def GenericItineraries : ProcessorItineraries<[
  72   InstrItinData<IIC_iALUx   , [InstrStage<1, [FU_Pipe0]>]>,
  73   InstrItinData<IIC_iALUi   , [InstrStage<1, [FU_Pipe0]>]>,
  74   InstrItinData<IIC_iALUr   , [InstrStage<1, [FU_Pipe0]>]>,
  75   InstrItinData<IIC_iALUsi  , [InstrStage<1, [FU_Pipe0]>]>,
  76   InstrItinData<IIC_iALUsr  , [InstrStage<1, [FU_Pipe0]>]>,
  77   InstrItinData<IIC_iUNAr   , [InstrStage<1, [FU_Pipe0]>]>,
  78   InstrItinData<IIC_iUNAsi  , [InstrStage<1, [FU_Pipe0]>]>,
  79   InstrItinData<IIC_iUNAsr  , [InstrStage<1, [FU_Pipe0]>]>,
  80   InstrItinData<IIC_iCMPi   , [InstrStage<1, [FU_Pipe0]>]>,
  81   InstrItinData<IIC_iCMPr   , [InstrStage<1, [FU_Pipe0]>]>,
  82   InstrItinData<IIC_iCMPsi  , [InstrStage<1, [FU_Pipe0]>]>,
  83   InstrItinData<IIC_iCMPsr  , [InstrStage<1, [FU_Pipe0]>]>,
  84   InstrItinData<IIC_iMOVi   , [InstrStage<1, [FU_Pipe0]>]>,
  85   InstrItinData<IIC_iMOVr   , [InstrStage<1, [FU_Pipe0]>]>,
  86   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [FU_Pipe0]>]>,
  87   InstrItinData<IIC_iMOVsr  , [InstrStage<1, [FU_Pipe0]>]>,
  88   InstrItinData<IIC_iCMOVi  , [InstrStage<1, [FU_Pipe0]>]>,
  89   InstrItinData<IIC_iCMOVr  , [InstrStage<1, [FU_Pipe0]>]>,
  90   InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
  91   InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
  92   InstrItinData<IIC_iMUL16  , [InstrStage<1, [FU_Pipe0]>]>,
  93   InstrItinData<IIC_iMAC16  , [InstrStage<1, [FU_Pipe0]>]>,
  94   InstrItinData<IIC_iMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
  95   InstrItinData<IIC_iMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
  96   InstrItinData<IIC_iMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
  97   InstrItinData<IIC_iMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
  98   InstrItinData<IIC_iLoadi  , [InstrStage<1, [FU_Pipe0]>,
  99                                InstrStage<1, [FU_LdSt0]>]>,
 100   InstrItinData<IIC_iLoadr  , [InstrStage<1, [FU_Pipe0]>,
 101                                InstrStage<1, [FU_LdSt0]>]>,
 102   InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
 103                                InstrStage<1, [FU_LdSt0]>]>,
 104   InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
 105                                InstrStage<1, [FU_LdSt0]>]>,
 106   InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
 107                                InstrStage<1, [FU_LdSt0]>]>,
 108   InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
 109                                InstrStage<1, [FU_LdSt0]>]>,
 110   InstrItinData<IIC_iLoadm  , [InstrStage<2, [FU_Pipe0]>,
 111                                InstrStage<2, [FU_LdSt0]>]>,
 112   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Pipe0]>]>,
 113   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Pipe0]>]>,
 114   InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
 115   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
 116   InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
 117   InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
 118   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Pipe0]>]>,
 119   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0]>]>,
 120   InstrItinData<IIC_fpALU   , [InstrStage<1, [FU_Pipe0]>]>,
 121   InstrItinData<IIC_fpMPY   , [InstrStage<1, [FU_Pipe0]>]>,
 122   InstrItinData<IIC_fpLoad  , [InstrStage<1, [FU_Pipe0]>,
 123                                InstrStage<1, [FU_LdSt0]>]>,
 124   InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
 125 ]>;
 126
 127
 128 include "ARMScheduleV6.td"
 129 include "ARMScheduleV7.td"