lib/CodeGen/SelectionDAG/SelectionDAGBuild.h

   1 //===-- SelectionDAGBuild.h - Selection-DAG building ----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SELECTIONDAGBUILD_H
  15 #define SELECTIONDAGBUILD_H
  16
  17 #include "llvm/Constants.h"
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/ADT/APInt.h"
  20 #include "llvm/ADT/DenseMap.h"
  21 #ifndef NDEBUG
  22 #include "llvm/ADT/SmallSet.h"
  23 #endif
  24 #include "llvm/CodeGen/SelectionDAGNodes.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/Support/CallSite.h"
  27 #include "llvm/Support/ErrorHandling.h"
  28 #include "llvm/Target/TargetMachine.h"
  29 #include <vector>
  30 #include <set>
  31
  32 namespace llvm {
  33
  34 class AliasAnalysis;
  35 class AllocaInst;
  36 class BasicBlock;
  37 class BitCastInst;
  38 class BranchInst;
  39 class CallInst;
  40 class ExtractElementInst;
  41 class ExtractValueInst;
  42 class FCmpInst;
  43 class FPExtInst;
  44 class FPToSIInst;
  45 class FPToUIInst;
  46 class FPTruncInst;
  47 class FreeInst;
  48 class Function;
  49 class GetElementPtrInst;
  50 class GCFunctionInfo;
  51 class ICmpInst;
  52 class IntToPtrInst;
  53 class InvokeInst;
  54 class InsertElementInst;
  55 class InsertValueInst;
  56 class Instruction;
  57 class LoadInst;
  58 class MachineBasicBlock;
  59 class MachineFunction;
  60 class MachineInstr;
  61 class MachineModuleInfo;
  62 class MachineRegisterInfo;
  63 class MallocInst;
  64 class PHINode;
  65 class PtrToIntInst;
  66 class ReturnInst;
  67 class SDISelAsmOperandInfo;
  68 class SExtInst;
  69 class SelectInst;
  70 class ShuffleVectorInst;
  71 class SIToFPInst;
  72 class StoreInst;
  73 class SwitchInst;
  74 class TargetData;
  75 class TargetLowering;
  76 class TruncInst;
  77 class UIToFPInst;
  78 class UnreachableInst;
  79 class UnwindInst;
  80 class VAArgInst;
  81 class ZExtInst;
  82
  83 //===--------------------------------------------------------------------===//
  84 /// FunctionLoweringInfo - This contains information that is global to a
  85 /// function that is used when lowering a region of the function.
  86 ///
  87 class FunctionLoweringInfo {
  88 public:
  89   TargetLowering &TLI;
  90   Function *Fn;
  91   MachineFunction *MF;
  92   MachineRegisterInfo *RegInfo;
  93
  94   explicit FunctionLoweringInfo(TargetLowering &TLI);
  95
  96   /// set - Initialize this FunctionLoweringInfo with the given Function
  97   /// and its associated MachineFunction.
  98   ///
  99   void set(Function &Fn, MachineFunction &MF, SelectionDAG &DAG,
 100            bool EnableFastISel);
 101
 102   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
 103   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
 104
 105   /// ValueMap - Since we emit code for the function a basic block at a time,
 106   /// we must remember which virtual registers hold the values for
 107   /// cross-basic-block values.
 108   DenseMap<const Value*, unsigned> ValueMap;
 109
 110   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
 111   /// the entry block.  This allows the allocas to be efficiently referenced
 112   /// anywhere in the function.
 113   DenseMap<const AllocaInst*, int> StaticAllocaMap;
 114
 115 #ifndef NDEBUG
 116   SmallSet<Instruction*, 8> CatchInfoLost;
 117   SmallSet<Instruction*, 8> CatchInfoFound;
 118 #endif
 119
 120   unsigned MakeReg(MVT VT);
 121
 122   /// isExportedInst - Return true if the specified value is an instruction
 123   /// exported from its block.
 124   bool isExportedInst(const Value *V) {
 125     return ValueMap.count(V);
 126   }
 127
 128   unsigned CreateRegForValue(const Value *V);
 129
 130   unsigned InitializeRegForValue(const Value *V) {
 131     unsigned &R = ValueMap[V];
 132     assert(R == 0 && "Already initialized this value register!");
 133     return R = CreateRegForValue(V);
 134   }
 135
 136   struct LiveOutInfo {
 137     unsigned NumSignBits;
 138     APInt KnownOne, KnownZero;
 139     LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
 140   };
 141
 142   /// LiveOutRegInfo - Information about live out vregs, indexed by their
 143   /// register number offset by 'FirstVirtualRegister'.
 144   std::vector<LiveOutInfo> LiveOutRegInfo;
 145
 146   /// clear - Clear out all the function-specific state. This returns this
 147   /// FunctionLoweringInfo to an empty state, ready to be used for a
 148   /// different function.
 149   void clear() {
 150     MBBMap.clear();
 151     ValueMap.clear();
 152     StaticAllocaMap.clear();
 153 #ifndef NDEBUG
 154     CatchInfoLost.clear();
 155     CatchInfoFound.clear();
 156 #endif
 157     LiveOutRegInfo.clear();
 158   }
 159 };
 160
 161 //===----------------------------------------------------------------------===//
 162 /// SelectionDAGLowering - This is the common target-independent lowering
 163 /// implementation that is parameterized by a TargetLowering object.
 164 /// Also, targets can overload any lowering method.
 165 ///
 166 class SelectionDAGLowering {
 167   MachineBasicBlock *CurMBB;
 168
 169   /// CurDebugLoc - current file + line number.  Changes as we build the DAG.
 170   DebugLoc CurDebugLoc;
 171
 172   DenseMap<const Value*, SDValue> NodeMap;
 173
 174   /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
 175   /// them up and then emit token factor nodes when possible.  This allows us to
 176   /// get simple disambiguation between loads without worrying about alias
 177   /// analysis.
 178   SmallVector<SDValue, 8> PendingLoads;
 179
 180   /// PendingExports - CopyToReg nodes that copy values to virtual registers
 181   /// for export to other blocks need to be emitted before any terminator
 182   /// instruction, but they have no other ordering requirements. We bunch them
 183   /// up and the emit a single tokenfactor for them just before terminator
 184   /// instructions.
 185   SmallVector<SDValue, 8> PendingExports;
 186
 187   /// Case - A struct to record the Value for a switch case, and the
 188   /// case's target basic block.
 189   struct Case {
 190     Constant* Low;
 191     Constant* High;
 192     MachineBasicBlock* BB;
 193
 194     Case() : Low(0), High(0), BB(0) { }
 195     Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
 196       Low(low), High(high), BB(bb) { }
 197     uint64_t size() const {
 198       uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
 199       uint64_t rLow  = cast<ConstantInt>(Low)->getSExtValue();
 200       return (rHigh - rLow + 1ULL);
 201     }
 202   };
 203
 204   struct CaseBits {
 205     uint64_t Mask;
 206     MachineBasicBlock* BB;
 207     unsigned Bits;
 208
 209     CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
 210       Mask(mask), BB(bb), Bits(bits) { }
 211   };
 212
 213   typedef std::vector<Case>           CaseVector;
 214   typedef std::vector<CaseBits>       CaseBitsVector;
 215   typedef CaseVector::iterator        CaseItr;
 216   typedef std::pair<CaseItr, CaseItr> CaseRange;
 217
 218   /// CaseRec - A struct with ctor used in lowering switches to a binary tree
 219   /// of conditional branches.
 220   struct CaseRec {
 221     CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
 222     CaseBB(bb), LT(lt), GE(ge), Range(r) {}
 223
 224     /// CaseBB - The MBB in which to emit the compare and branch
 225     MachineBasicBlock *CaseBB;
 226     /// LT, GE - If nonzero, we know the current case value must be less-than or
 227     /// greater-than-or-equal-to these Constants.
 228     Constant *LT;
 229     Constant *GE;
 230     /// Range - A pair of iterators representing the range of case values to be
 231     /// processed at this point in the binary search tree.
 232     CaseRange Range;
 233   };
 234
 235   typedef std::vector<CaseRec> CaseRecVector;
 236
 237   /// The comparison function for sorting the switch case values in the vector.
 238   /// WARNING: Case ranges should be disjoint!
 239   struct CaseCmp {
 240     bool operator () (const Case& C1, const Case& C2) {
 241       assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
 242       const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
 243       const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
 244       return CI1->getValue().slt(CI2->getValue());
 245     }
 246   };
 247
 248   struct CaseBitsCmp {
 249     bool operator () (const CaseBits& C1, const CaseBits& C2) {
 250       return C1.Bits > C2.Bits;
 251     }
 252   };
 253
 254   size_t Clusterify(CaseVector& Cases, const SwitchInst &SI);
 255
 256   /// CaseBlock - This structure is used to communicate between SDLowering and
 257   /// SDISel for the code generation of additional basic blocks needed by multi-
 258   /// case switch statements.
 259   struct CaseBlock {
 260     CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
 261               MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
 262               MachineBasicBlock *me)
 263       : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
 264         TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
 265     // CC - the condition code to use for the case block's setcc node
 266     ISD::CondCode CC;
 267     // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
 268     // Emit by default LHS op RHS. MHS is used for range comparisons:
 269     // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
 270     Value *CmpLHS, *CmpMHS, *CmpRHS;
 271     // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
 272     MachineBasicBlock *TrueBB, *FalseBB;
 273     // ThisBB - the block into which to emit the code for the setcc and branches
 274     MachineBasicBlock *ThisBB;
 275   };
 276   struct JumpTable {
 277     JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
 278               MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
 279
 280     /// Reg - the virtual register containing the index of the jump table entry
 281     //. to jump to.
 282     unsigned Reg;
 283     /// JTI - the JumpTableIndex for this jump table in the function.
 284     unsigned JTI;
 285     /// MBB - the MBB into which to emit the code for the indirect jump.
 286     MachineBasicBlock *MBB;
 287     /// Default - the MBB of the default bb, which is a successor of the range
 288     /// check MBB.  This is when updating PHI nodes in successors.
 289     MachineBasicBlock *Default;
 290   };
 291   struct JumpTableHeader {
 292     JumpTableHeader(APInt F, APInt L, Value* SV, MachineBasicBlock* H,
 293                     bool E = false):
 294       First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
 295     APInt First;
 296     APInt Last;
 297     Value *SValue;
 298     MachineBasicBlock *HeaderBB;
 299     bool Emitted;
 300   };
 301   typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
 302
 303   struct BitTestCase {
 304     BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
 305       Mask(M), ThisBB(T), TargetBB(Tr) { }
 306     uint64_t Mask;
 307     MachineBasicBlock* ThisBB;
 308     MachineBasicBlock* TargetBB;
 309   };
 310
 311   typedef SmallVector<BitTestCase, 3> BitTestInfo;
 312
 313   struct BitTestBlock {
 314     BitTestBlock(APInt F, APInt R, Value* SV,
 315                  unsigned Rg, bool E,
 316                  MachineBasicBlock* P, MachineBasicBlock* D,
 317                  const BitTestInfo& C):
 318       First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
 319       Parent(P), Default(D), Cases(C) { }
 320     APInt First;
 321     APInt Range;
 322     Value  *SValue;
 323     unsigned Reg;
 324     bool Emitted;
 325     MachineBasicBlock *Parent;
 326     MachineBasicBlock *Default;
 327     BitTestInfo Cases;
 328   };
 329
 330 public:
 331   // TLI - This is information that describes the available target features we
 332   // need for lowering.  This indicates when operations are unavailable,
 333   // implemented with a libcall, etc.
 334   TargetLowering &TLI;
 335   SelectionDAG &DAG;
 336   const TargetData *TD;
 337   AliasAnalysis *AA;
 338
 339   /// SwitchCases - Vector of CaseBlock structures used to communicate
 340   /// SwitchInst code generation information.
 341   std::vector<CaseBlock> SwitchCases;
 342   /// JTCases - Vector of JumpTable structures used to communicate
 343   /// SwitchInst code generation information.
 344   std::vector<JumpTableBlock> JTCases;
 345   /// BitTestCases - Vector of BitTestBlock structures used to communicate
 346   /// SwitchInst code generation information.
 347   std::vector<BitTestBlock> BitTestCases;
 348
 349   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
 350
 351   // Emit PHI-node-operand constants only once even if used by multiple
 352   // PHI nodes.
 353   DenseMap<Constant*, unsigned> ConstantsOut;
 354
 355   /// FuncInfo - Information about the function as a whole.
 356   ///
 357   FunctionLoweringInfo &FuncInfo;
 358
 359   /// OptLevel - What optimization level we're generating code for.
 360   ///
 361   CodeGenOpt::Level OptLevel;
 362
 363   /// GFI - Garbage collection metadata for the function.
 364   GCFunctionInfo *GFI;
 365
 366   /// HasTailCall - This is set to true if a call in the current
 367   /// block has been translated as a tail call. In this case,
 368   /// no subsequent DAG nodes should be created.
 369   ///
 370   bool HasTailCall;
 371
 372   LLVMContext *Context;
 373
 374   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
 375                        FunctionLoweringInfo &funcinfo,
 376                        CodeGenOpt::Level ol)
 377     : CurDebugLoc(DebugLoc::getUnknownLoc()),
 378       TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
 379       HasTailCall(false),
 380       Context(dag.getContext()) {
 381   }
 382
 383   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
 384
 385   /// clear - Clear out the curret SelectionDAG and the associated
 386   /// state and prepare this SelectionDAGLowering object to be used
 387   /// for a new block. This doesn't clear out information about
 388   /// additional blocks that are needed to complete switch lowering
 389   /// or PHI node updating; that information is cleared out as it is
 390   /// consumed.
 391   void clear();
 392
 393   /// getRoot - Return the current virtual root of the Selection DAG,
 394   /// flushing any PendingLoad items. This must be done before emitting
 395   /// a store or any other node that may need to be ordered after any
 396   /// prior load instructions.
 397   ///
 398   SDValue getRoot();
 399
 400   /// getControlRoot - Similar to getRoot, but instead of flushing all the
 401   /// PendingLoad items, flush all the PendingExports items. It is necessary
 402   /// to do this before emitting a terminator instruction.
 403   ///
 404   SDValue getControlRoot();
 405
 406   DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
 407   void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; }
 408
 409   void CopyValueToVirtualRegister(Value *V, unsigned Reg);
 410
 411   void visit(Instruction &I);
 412
 413   void visit(unsigned Opcode, User &I);
 414
 415   void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
 416
 417   SDValue getValue(const Value *V);
 418
 419   void setValue(const Value *V, SDValue NewN) {
 420     SDValue &N = NodeMap[V];
 421     assert(N.getNode() == 0 && "Already set a value for this node!");
 422     N = NewN;
 423   }
 424
 425   void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
 426                             std::set<unsigned> &OutputRegs,
 427                             std::set<unsigned> &InputRegs);
 428
 429   void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
 430                             MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
 431                             unsigned Opc);
 432   void EmitBranchForMergedCondition(Value *Cond, MachineBasicBlock *TBB,
 433                                     MachineBasicBlock *FBB,
 434                                     MachineBasicBlock *CurBB);
 435   bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
 436   bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
 437   void CopyToExportRegsIfNeeded(Value *V);
 438   void ExportFromCurrentBlock(Value *V);
 439   void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
 440                    MachineBasicBlock *LandingPad = NULL);
 441
 442 private:
 443   // Terminator instructions.
 444   void visitRet(ReturnInst &I);
 445   void visitBr(BranchInst &I);
 446   void visitSwitch(SwitchInst &I);
 447   void visitUnreachable(UnreachableInst &I) { /* noop */ }
 448
 449   // Helpers for visitSwitch
 450   bool handleSmallSwitchRange(CaseRec& CR,
 451                               CaseRecVector& WorkList,
 452                               Value* SV,
 453                               MachineBasicBlock* Default);
 454   bool handleJTSwitchCase(CaseRec& CR,
 455                           CaseRecVector& WorkList,
 456                           Value* SV,
 457                           MachineBasicBlock* Default);
 458   bool handleBTSplitSwitchCase(CaseRec& CR,
 459                                CaseRecVector& WorkList,
 460                                Value* SV,
 461                                MachineBasicBlock* Default);
 462   bool handleBitTestsSwitchCase(CaseRec& CR,
 463                                 CaseRecVector& WorkList,
 464                                 Value* SV,
 465                                 MachineBasicBlock* Default);
 466 public:
 467   void visitSwitchCase(CaseBlock &CB);
 468   void visitBitTestHeader(BitTestBlock &B);
 469   void visitBitTestCase(MachineBasicBlock* NextMBB,
 470                         unsigned Reg,
 471                         BitTestCase &B);
 472   void visitJumpTable(JumpTable &JT);
 473   void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
 474
 475 private:
 476   // These all get lowered before this pass.
 477   void visitInvoke(InvokeInst &I);
 478   void visitUnwind(UnwindInst &I);
 479
 480   void visitBinary(User &I, unsigned OpCode);
 481   void visitShift(User &I, unsigned Opcode);
 482   void visitAdd(User &I)  { visitBinary(I, ISD::ADD); }
 483   void visitFAdd(User &I) { visitBinary(I, ISD::FADD); }
 484   void visitSub(User &I)  { visitBinary(I, ISD::SUB); }
 485   void visitFSub(User &I);
 486   void visitMul(User &I)  { visitBinary(I, ISD::MUL); }
 487   void visitFMul(User &I) { visitBinary(I, ISD::FMUL); }
 488   void visitURem(User &I) { visitBinary(I, ISD::UREM); }
 489   void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
 490   void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
 491   void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
 492   void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
 493   void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
 494   void visitAnd (User &I) { visitBinary(I, ISD::AND); }
 495   void visitOr  (User &I) { visitBinary(I, ISD::OR); }
 496   void visitXor (User &I) { visitBinary(I, ISD::XOR); }
 497   void visitShl (User &I) { visitShift(I, ISD::SHL); }
 498   void visitLShr(User &I) { visitShift(I, ISD::SRL); }
 499   void visitAShr(User &I) { visitShift(I, ISD::SRA); }
 500   void visitICmp(User &I);
 501   void visitFCmp(User &I);
 502   // Visit the conversion instructions
 503   void visitTrunc(User &I);
 504   void visitZExt(User &I);
 505   void visitSExt(User &I);
 506   void visitFPTrunc(User &I);
 507   void visitFPExt(User &I);
 508   void visitFPToUI(User &I);
 509   void visitFPToSI(User &I);
 510   void visitUIToFP(User &I);
 511   void visitSIToFP(User &I);
 512   void visitPtrToInt(User &I);
 513   void visitIntToPtr(User &I);
 514   void visitBitCast(User &I);
 515
 516   void visitExtractElement(User &I);
 517   void visitInsertElement(User &I);
 518   void visitShuffleVector(User &I);
 519
 520   void visitExtractValue(ExtractValueInst &I);
 521   void visitInsertValue(InsertValueInst &I);
 522
 523   void visitGetElementPtr(User &I);
 524   void visitSelect(User &I);
 525
 526   void visitMalloc(MallocInst &I);
 527   void visitFree(FreeInst &I);
 528   void visitAlloca(AllocaInst &I);
 529   void visitLoad(LoadInst &I);
 530   void visitStore(StoreInst &I);
 531   void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
 532   void visitCall(CallInst &I);
 533   void visitInlineAsm(CallSite CS);
 534   const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
 535   void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
 536
 537   void visitPow(CallInst &I);
 538   void visitExp2(CallInst &I);
 539   void visitExp(CallInst &I);
 540   void visitLog(CallInst &I);
 541   void visitLog2(CallInst &I);
 542   void visitLog10(CallInst &I);
 543
 544   void visitVAStart(CallInst &I);
 545   void visitVAArg(VAArgInst &I);
 546   void visitVAEnd(CallInst &I);
 547   void visitVACopy(CallInst &I);
 548
 549   void visitUserOp1(Instruction &I) {
 550     llvm_unreachable("UserOp1 should not exist at instruction selection time!");
 551   }
 552   void visitUserOp2(Instruction &I) {
 553     llvm_unreachable("UserOp2 should not exist at instruction selection time!");
 554   }
 555
 556   const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
 557   const char *implVisitAluOverflow(CallInst &I, ISD::NodeType Op);
 558 };
 559
 560 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
 561 /// call, and add them to the specified machine basic block.
 562 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
 563                   MachineBasicBlock *MBB);
 564
 565 } // end namespace llvm
 566
 567 #endif