1 // FIXME
: Switch back to FileCheck once we print actual instructions
3 // RUN
: llvm-mc
-triple x86_64-unknown-unknown
%s
> %t
5 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:2, reg:0, reg:2.)} %t
8 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:19, reg:0, val:24.)} %t
11 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:20, imm:1, reg:0, val:10, reg:0, reg:19.)} %t
13 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:20, imm:1, reg:21, val:10, reg:0, reg:19.)} %t
14 movl
%eax
, 10(%ebp
, %ebx
)
15 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:20, imm:4, reg:21, val:10, reg:0, reg:19.)} %t
16 movl
%eax
, 10(%ebp
, %ebx
, 4)
17 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:0, imm:4, reg:21, val:10, reg:0, reg:19.)} %t
18 movl
%eax
, 10(, %ebx
, 4)
20 // FIXME
: Check that this matches SUB32ri8
21 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:19, reg:0, val:1.)} %t
24 // FIXME
: Check that this matches SUB32ri8
25 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:19, reg:0, val:-1.)} %t
28 // FIXME
: Check that this matches SUB32ri
29 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:19, reg:0, val:256.)} %t
32 // FIXME
: Check that this matches XOR64ri8
33 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:80, reg:0, val:1.)} %t
36 // FIXME
: Check that this matches XOR64ri32
37 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:80, reg:0, val:256.)} %t
40 // FIXME
: Check that this matches SUB8rr
41 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:5, reg:0, reg:2.)} %t
44 // FIXME
: Check that this matches SUB16rr
45 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:8, reg:0, reg:3.)} %t
48 // FIXME
: Check that this matches SUB32rr
49 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:21, reg:0, reg:19.)} %t
52 // FIXME
: Check that this matches the correct instruction.
53 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:80.)} %t
56 // FIXME
: Check that this matches the correct instruction.
57 // RUN
: grep
{MCInst
(opcode
=.*, operands=.reg:21, reg:0, reg:19.)} %t