lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h

   1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the ScheduleDAGSDNodes class, which implements
  11 // scheduling for an SDNode-based dependency graph.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SCHEDULEDAGSDNODES_H
  16 #define SCHEDULEDAGSDNODES_H
  17
  18 #include "llvm/CodeGen/ScheduleDAG.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20
  21 namespace llvm {
  22   /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
  23   ///
  24   /// Edges between SUnits are initially based on edges in the SelectionDAG,
  25   /// and additional edges can be added by the schedulers as heuristics.
  26   /// SDNodes such as Constants, Registers, and a few others that are not
  27   /// interesting to schedulers are not allocated SUnits.
  28   ///
  29   /// SDNodes with MVT::Flag operands are grouped along with the flagged
  30   /// nodes into a single SUnit so that they are scheduled together.
  31   ///
  32   /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
  33   /// edges.  Physical register dependence information is not carried in
  34   /// the DAG and must be handled explicitly by schedulers.
  35   ///
  36   class ScheduleDAGSDNodes : public ScheduleDAG {
  37   public:
  38     SelectionDAG *DAG;                    // DAG of the current basic block
  39
  40     explicit ScheduleDAGSDNodes(MachineFunction &mf);
  41
  42     virtual ~ScheduleDAGSDNodes() {}
  43
  44     /// Run - perform scheduling.
  45     ///
  46     void Run(SelectionDAG *dag, MachineBasicBlock *bb,
  47              MachineBasicBlock::iterator insertPos);
  48
  49     /// isPassiveNode - Return true if the node is a non-scheduled leaf.
  50     ///
  51     static bool isPassiveNode(SDNode *Node) {
  52       if (isa<ConstantSDNode>(Node))       return true;
  53       if (isa<ConstantFPSDNode>(Node))     return true;
  54       if (isa<RegisterSDNode>(Node))       return true;
  55       if (isa<GlobalAddressSDNode>(Node))  return true;
  56       if (isa<BasicBlockSDNode>(Node))     return true;
  57       if (isa<FrameIndexSDNode>(Node))     return true;
  58       if (isa<ConstantPoolSDNode>(Node))   return true;
  59       if (isa<JumpTableSDNode>(Node))      return true;
  60       if (isa<ExternalSymbolSDNode>(Node)) return true;
  61       if (isa<MemOperandSDNode>(Node))     return true;
  62       if (Node->getOpcode() == ISD::EntryToken) return true;
  63       return false;
  64     }
  65
  66     /// NewSUnit - Creates a new SUnit and return a ptr to it.
  67     ///
  68     SUnit *NewSUnit(SDNode *N) {
  69 #ifndef NDEBUG
  70       const SUnit *Addr = 0;
  71       if (!SUnits.empty())
  72         Addr = &SUnits[0];
  73 #endif
  74       SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
  75       assert((Addr == 0 || Addr == &SUnits[0]) &&
  76              "SUnits std::vector reallocated on the fly!");
  77       SUnits.back().OrigNode = &SUnits.back();
  78       return &SUnits.back();
  79     }
  80
  81     /// Clone - Creates a clone of the specified SUnit. It does not copy the
  82     /// predecessors / successors info nor the temporary scheduling states.
  83     ///
  84     SUnit *Clone(SUnit *N);
  85
  86     /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
  87     /// are input.  This SUnit graph is similar to the SelectionDAG, but
  88     /// excludes nodes that aren't interesting to scheduling, and represents
  89     /// flagged together nodes with a single SUnit.
  90     virtual void BuildSchedGraph();
  91
  92     /// ComputeLatency - Compute node latency.
  93     ///
  94     virtual void ComputeLatency(SUnit *SU);
  95
  96     /// CountResults - The results of target nodes have register or immediate
  97     /// operands first, then an optional chain, and optional flag operands
  98     /// (which do not go into the machine instrs.)
  99     static unsigned CountResults(SDNode *Node);
 100
 101     /// CountOperands - The inputs to target nodes have any actual inputs first,
 102     /// followed by special operands that describe memory references, then an
 103     /// optional chain operand, then flag operands.  Compute the number of
 104     /// actual operands that will go into the resulting MachineInstr.
 105     static unsigned CountOperands(SDNode *Node);
 106
 107     /// ComputeMemOperandsEnd - Find the index one past the last
 108     /// MemOperandSDNode operand
 109     static unsigned ComputeMemOperandsEnd(SDNode *Node);
 110
 111     /// EmitNode - Generate machine code for an node and needed dependencies.
 112     /// VRBaseMap contains, for each already emitted node, the first virtual
 113     /// register number for the results of the node.
 114     ///
 115     void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
 116                   DenseMap<SDValue, unsigned> &VRBaseMap);
 117
 118     virtual MachineBasicBlock *EmitSchedule();
 119
 120     /// Schedule - Order nodes according to selected style, filling
 121     /// in the Sequence member.
 122     ///
 123     virtual void Schedule() = 0;
 124
 125     virtual void dumpNode(const SUnit *SU) const;
 126
 127     virtual std::string getGraphNodeLabel(const SUnit *SU) const;
 128
 129     virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
 130
 131   private:
 132     /// EmitSubregNode - Generate machine code for subreg nodes.
 133     ///
 134     void EmitSubregNode(SDNode *Node,
 135                         DenseMap<SDValue, unsigned> &VRBaseMap);
 136
 137     /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS
 138     /// nodes.
 139     ///
 140     void EmitCopyToRegClassNode(SDNode *Node,
 141                                 DenseMap<SDValue, unsigned> &VRBaseMap);
 142
 143     /// getVR - Return the virtual register corresponding to the specified result
 144     /// of the specified node.
 145     unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
 146
 147     /// getDstOfCopyToRegUse - If the only use of the specified result number of
 148     /// node is a CopyToReg, return its destination register. Return 0 otherwise.
 149     unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
 150
 151     void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
 152                     const TargetInstrDesc *II,
 153                     DenseMap<SDValue, unsigned> &VRBaseMap);
 154
 155     /// AddRegisterOperand - Add the specified register as an operand to the
 156     /// specified machine instr. Insert register copies if the register is
 157     /// not in the required register class.
 158     void AddRegisterOperand(MachineInstr *MI, SDValue Op,
 159                             unsigned IIOpNum, const TargetInstrDesc *II,
 160                             DenseMap<SDValue, unsigned> &VRBaseMap);
 161
 162     /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
 163     /// implicit physical register output.
 164     void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
 165                          bool IsCloned, unsigned SrcReg,
 166                          DenseMap<SDValue, unsigned> &VRBaseMap);
 167
 168     void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
 169                                 const TargetInstrDesc &II, bool IsClone,
 170                                 bool IsCloned,
 171                                 DenseMap<SDValue, unsigned> &VRBaseMap);
 172
 173     /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
 174     void BuildSchedUnits();
 175     void AddSchedEdges();
 176   };
 177 }
 178
 179 #endif