It's not legal to fold a load from a narrower stack slot into a wider instruction...
[llvm/avr.git] / lib / CodeGen / LiveStackAnalysis.cpp
bloba7bea1fd4f986af9f63896056db99f223648c7f1
1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the live stack slot analysis pass. It is analogous to
11 // live interval analysis except it's analyzing liveness of stack slots rather
12 // than registers.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "livestacks"
17 #include "llvm/CodeGen/LiveStackAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/Statistic.h"
24 #include <limits>
25 using namespace llvm;
27 char LiveStacks::ID = 0;
28 static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
30 void LiveStacks::scaleNumbering(int factor) {
31 // Scale the intervals.
32 for (iterator LI = begin(), LE = end(); LI != LE; ++LI) {
33 LI->second.scaleNumbering(factor);
37 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
38 AU.setPreservesAll();
39 MachineFunctionPass::getAnalysisUsage(AU);
42 void LiveStacks::releaseMemory() {
43 // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
44 VNInfoAllocator.Reset();
45 S2IMap.clear();
46 S2RCMap.clear();
49 bool LiveStacks::runOnMachineFunction(MachineFunction &) {
50 // FIXME: No analysis is being done right now. We are relying on the
51 // register allocators to provide the information.
52 return false;
55 /// print - Implement the dump method.
56 void LiveStacks::print(raw_ostream &OS, const Module*) const {
58 OS << "********** INTERVALS **********\n";
59 for (const_iterator I = begin(), E = end(); I != E; ++I) {
60 I->second.print(OS);
61 int Slot = I->first;
62 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
63 if (RC)
64 OS << " [" << RC->getName() << "]\n";
65 else
66 OS << " [Unknown]\n";