lib/CodeGen/MachineInstr.cpp

   1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Methods common to all machine instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MachineInstr.h"
  15 #include "llvm/Constants.h"
  16 #include "llvm/InlineAsm.h"
  17 #include "llvm/Value.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/CodeGen/PseudoSourceValue.h"
  21 #include "llvm/Target/TargetMachine.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23 #include "llvm/Target/TargetInstrDesc.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Analysis/DebugInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/LeakDetector.h"
  28 #include "llvm/Support/MathExtras.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 #include "llvm/ADT/FoldingSet.h"
  31 using namespace llvm;
  32
  33 //===----------------------------------------------------------------------===//
  34 // MachineOperand Implementation
  35 //===----------------------------------------------------------------------===//
  36
  37 /// AddRegOperandToRegInfo - Add this register operand to the specified
  38 /// MachineRegisterInfo.  If it is null, then the next/prev fields should be
  39 /// explicitly nulled out.
  40 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
  41   assert(isReg() && "Can only add reg operand to use lists");
  42
  43   // If the reginfo pointer is null, just explicitly null out or next/prev
  44   // pointers, to ensure they are not garbage.
  45   if (RegInfo == 0) {
  46     Contents.Reg.Prev = 0;
  47     Contents.Reg.Next = 0;
  48     return;
  49   }
  50
  51   // Otherwise, add this operand to the head of the registers use/def list.
  52   MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
  53
  54   // For SSA values, we prefer to keep the definition at the start of the list.
  55   // we do this by skipping over the definition if it is at the head of the
  56   // list.
  57   if (*Head && (*Head)->isDef())
  58     Head = &(*Head)->Contents.Reg.Next;
  59
  60   Contents.Reg.Next = *Head;
  61   if (Contents.Reg.Next) {
  62     assert(getReg() == Contents.Reg.Next->getReg() &&
  63            "Different regs on the same list!");
  64     Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
  65   }
  66
  67   Contents.Reg.Prev = Head;
  68   *Head = this;
  69 }
  70
  71 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
  72 /// MachineRegisterInfo it is linked with.
  73 void MachineOperand::RemoveRegOperandFromRegInfo() {
  74   assert(isOnRegUseList() && "Reg operand is not on a use list");
  75   // Unlink this from the doubly linked list of operands.
  76   MachineOperand *NextOp = Contents.Reg.Next;
  77   *Contents.Reg.Prev = NextOp;
  78   if (NextOp) {
  79     assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
  80     NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
  81   }
  82   Contents.Reg.Prev = 0;
  83   Contents.Reg.Next = 0;
  84 }
  85
  86 void MachineOperand::setReg(unsigned Reg) {
  87   if (getReg() == Reg) return; // No change.
  88
  89   // Otherwise, we have to change the register.  If this operand is embedded
  90   // into a machine function, we need to update the old and new register's
  91   // use/def lists.
  92   if (MachineInstr *MI = getParent())
  93     if (MachineBasicBlock *MBB = MI->getParent())
  94       if (MachineFunction *MF = MBB->getParent()) {
  95         RemoveRegOperandFromRegInfo();
  96         Contents.Reg.RegNo = Reg;
  97         AddRegOperandToRegInfo(&MF->getRegInfo());
  98         return;
  99       }
 100
 101   // Otherwise, just change the register, no problem.  :)
 102   Contents.Reg.RegNo = Reg;
 103 }
 104
 105 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 106 /// the specified value.  If an operand is known to be an immediate already,
 107 /// the setImm method should be used.
 108 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
 109   // If this operand is currently a register operand, and if this is in a
 110   // function, deregister the operand from the register's use/def list.
 111   if (isReg() && getParent() && getParent()->getParent() &&
 112       getParent()->getParent()->getParent())
 113     RemoveRegOperandFromRegInfo();
 114
 115   OpKind = MO_Immediate;
 116   Contents.ImmVal = ImmVal;
 117 }
 118
 119 /// ChangeToRegister - Replace this operand with a new register operand of
 120 /// the specified value.  If an operand is known to be an register already,
 121 /// the setReg method should be used.
 122 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
 123                                       bool isKill, bool isDead, bool isUndef) {
 124   // If this operand is already a register operand, use setReg to update the
 125   // register's use/def lists.
 126   if (isReg()) {
 127     assert(!isEarlyClobber());
 128     setReg(Reg);
 129   } else {
 130     // Otherwise, change this to a register and set the reg#.
 131     OpKind = MO_Register;
 132     Contents.Reg.RegNo = Reg;
 133
 134     // If this operand is embedded in a function, add the operand to the
 135     // register's use/def list.
 136     if (MachineInstr *MI = getParent())
 137       if (MachineBasicBlock *MBB = MI->getParent())
 138         if (MachineFunction *MF = MBB->getParent())
 139           AddRegOperandToRegInfo(&MF->getRegInfo());
 140   }
 141
 142   IsDef = isDef;
 143   IsImp = isImp;
 144   IsKill = isKill;
 145   IsDead = isDead;
 146   IsUndef = isUndef;
 147   IsEarlyClobber = false;
 148   SubReg = 0;
 149 }
 150
 151 /// isIdenticalTo - Return true if this operand is identical to the specified
 152 /// operand.
 153 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 154   if (getType() != Other.getType() ||
 155       getTargetFlags() != Other.getTargetFlags())
 156     return false;
 157
 158   switch (getType()) {
 159   default: llvm_unreachable("Unrecognized operand type");
 160   case MachineOperand::MO_Register:
 161     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 162            getSubReg() == Other.getSubReg();
 163   case MachineOperand::MO_Immediate:
 164     return getImm() == Other.getImm();
 165   case MachineOperand::MO_FPImmediate:
 166     return getFPImm() == Other.getFPImm();
 167   case MachineOperand::MO_MachineBasicBlock:
 168     return getMBB() == Other.getMBB();
 169   case MachineOperand::MO_FrameIndex:
 170     return getIndex() == Other.getIndex();
 171   case MachineOperand::MO_ConstantPoolIndex:
 172     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 173   case MachineOperand::MO_JumpTableIndex:
 174     return getIndex() == Other.getIndex();
 175   case MachineOperand::MO_GlobalAddress:
 176     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 177   case MachineOperand::MO_ExternalSymbol:
 178     return !strcmp(getSymbolName(), Other.getSymbolName()) &&
 179            getOffset() == Other.getOffset();
 180   }
 181 }
 182
 183 /// print - Print the specified machine operand.
 184 ///
 185 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
 186   switch (getType()) {
 187   case MachineOperand::MO_Register:
 188     if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
 189       OS << "%reg" << getReg();
 190     } else {
 191       // If the instruction is embedded into a basic block, we can find the
 192       // target info for the instruction.
 193       if (TM == 0)
 194         if (const MachineInstr *MI = getParent())
 195           if (const MachineBasicBlock *MBB = MI->getParent())
 196             if (const MachineFunction *MF = MBB->getParent())
 197               TM = &MF->getTarget();
 198
 199       if (TM)
 200         OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
 201       else
 202         OS << "%mreg" << getReg();
 203     }
 204
 205     if (getSubReg() != 0)
 206       OS << ':' << getSubReg();
 207
 208     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
 209         isEarlyClobber()) {
 210       OS << '<';
 211       bool NeedComma = false;
 212       if (isImplicit()) {
 213         if (NeedComma) OS << ',';
 214         OS << (isDef() ? "imp-def" : "imp-use");
 215         NeedComma = true;
 216       } else if (isDef()) {
 217         if (NeedComma) OS << ',';
 218         if (isEarlyClobber())
 219           OS << "earlyclobber,";
 220         OS << "def";
 221         NeedComma = true;
 222       }
 223       if (isKill() || isDead() || isUndef()) {
 224         if (NeedComma) OS << ',';
 225         if (isKill())  OS << "kill";
 226         if (isDead())  OS << "dead";
 227         if (isUndef()) {
 228           if (isKill() || isDead())
 229             OS << ',';
 230           OS << "undef";
 231         }
 232       }
 233       OS << '>';
 234     }
 235     break;
 236   case MachineOperand::MO_Immediate:
 237     OS << getImm();
 238     break;
 239   case MachineOperand::MO_FPImmediate:
 240     if (getFPImm()->getType() == Type::getFloatTy(getFPImm()->getContext()))
 241       OS << getFPImm()->getValueAPF().convertToFloat();
 242     else
 243       OS << getFPImm()->getValueAPF().convertToDouble();
 244     break;
 245   case MachineOperand::MO_MachineBasicBlock:
 246     OS << "mbb<"
 247        << ((Value*)getMBB()->getBasicBlock())->getName()
 248        << "," << (void*)getMBB() << '>';
 249     break;
 250   case MachineOperand::MO_FrameIndex:
 251     OS << "<fi#" << getIndex() << '>';
 252     break;
 253   case MachineOperand::MO_ConstantPoolIndex:
 254     OS << "<cp#" << getIndex();
 255     if (getOffset()) OS << "+" << getOffset();
 256     OS << '>';
 257     break;
 258   case MachineOperand::MO_JumpTableIndex:
 259     OS << "<jt#" << getIndex() << '>';
 260     break;
 261   case MachineOperand::MO_GlobalAddress:
 262     OS << "<ga:" << ((Value*)getGlobal())->getName();
 263     if (getOffset()) OS << "+" << getOffset();
 264     OS << '>';
 265     break;
 266   case MachineOperand::MO_ExternalSymbol:
 267     OS << "<es:" << getSymbolName();
 268     if (getOffset()) OS << "+" << getOffset();
 269     OS << '>';
 270     break;
 271   default:
 272     llvm_unreachable("Unrecognized operand type");
 273   }
 274
 275   if (unsigned TF = getTargetFlags())
 276     OS << "[TF=" << TF << ']';
 277 }
 278
 279 //===----------------------------------------------------------------------===//
 280 // MachineMemOperand Implementation
 281 //===----------------------------------------------------------------------===//
 282
 283 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
 284                                      int64_t o, uint64_t s, unsigned int a)
 285   : Offset(o), Size(s), V(v),
 286     Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
 287   assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
 288   assert((isLoad() || isStore()) && "Not a load/store!");
 289 }
 290
 291 /// Profile - Gather unique data for the object.
 292 ///
 293 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
 294   ID.AddInteger(Offset);
 295   ID.AddInteger(Size);
 296   ID.AddPointer(V);
 297   ID.AddInteger(Flags);
 298 }
 299
 300 //===----------------------------------------------------------------------===//
 301 // MachineInstr Implementation
 302 //===----------------------------------------------------------------------===//
 303
 304 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
 305 /// TID NULL and no operands.
 306 MachineInstr::MachineInstr()
 307   : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
 308   // Make sure that we get added to a machine basicblock
 309   LeakDetector::addGarbageObject(this);
 310 }
 311
 312 void MachineInstr::addImplicitDefUseOperands() {
 313   if (TID->ImplicitDefs)
 314     for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
 315       addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
 316   if (TID->ImplicitUses)
 317     for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
 318       addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
 319 }
 320
 321 /// MachineInstr ctor - This constructor create a MachineInstr and add the
 322 /// implicit operands. It reserves space for number of operands specified by
 323 /// TargetInstrDesc or the numOperands if it is not zero. (for
 324 /// instructions with variable number of operands).
 325 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
 326   : TID(&tid), NumImplicitOps(0), Parent(0),
 327     debugLoc(DebugLoc::getUnknownLoc()) {
 328   if (!NoImp && TID->getImplicitDefs())
 329     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 330       NumImplicitOps++;
 331   if (!NoImp && TID->getImplicitUses())
 332     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 333       NumImplicitOps++;
 334   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 335   if (!NoImp)
 336     addImplicitDefUseOperands();
 337   // Make sure that we get added to a machine basicblock
 338   LeakDetector::addGarbageObject(this);
 339 }
 340
 341 /// MachineInstr ctor - As above, but with a DebugLoc.
 342 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
 343                            bool NoImp)
 344   : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
 345   if (!NoImp && TID->getImplicitDefs())
 346     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 347       NumImplicitOps++;
 348   if (!NoImp && TID->getImplicitUses())
 349     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 350       NumImplicitOps++;
 351   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 352   if (!NoImp)
 353     addImplicitDefUseOperands();
 354   // Make sure that we get added to a machine basicblock
 355   LeakDetector::addGarbageObject(this);
 356 }
 357
 358 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
 359 /// that the MachineInstr is created and added to the end of the specified
 360 /// basic block.
 361 ///
 362 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
 363   : TID(&tid), NumImplicitOps(0), Parent(0),
 364     debugLoc(DebugLoc::getUnknownLoc()) {
 365   assert(MBB && "Cannot use inserting ctor with null basic block!");
 366   if (TID->ImplicitDefs)
 367     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 368       NumImplicitOps++;
 369   if (TID->ImplicitUses)
 370     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 371       NumImplicitOps++;
 372   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 373   addImplicitDefUseOperands();
 374   // Make sure that we get added to a machine basicblock
 375   LeakDetector::addGarbageObject(this);
 376   MBB->push_back(this);  // Add instruction to end of basic block!
 377 }
 378
 379 /// MachineInstr ctor - As above, but with a DebugLoc.
 380 ///
 381 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
 382                            const TargetInstrDesc &tid)
 383   : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
 384   assert(MBB && "Cannot use inserting ctor with null basic block!");
 385   if (TID->ImplicitDefs)
 386     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 387       NumImplicitOps++;
 388   if (TID->ImplicitUses)
 389     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 390       NumImplicitOps++;
 391   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 392   addImplicitDefUseOperands();
 393   // Make sure that we get added to a machine basicblock
 394   LeakDetector::addGarbageObject(this);
 395   MBB->push_back(this);  // Add instruction to end of basic block!
 396 }
 397
 398 /// MachineInstr ctor - Copies MachineInstr arg exactly
 399 ///
 400 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
 401   : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
 402         debugLoc(MI.getDebugLoc()) {
 403   Operands.reserve(MI.getNumOperands());
 404
 405   // Add operands
 406   for (unsigned i = 0; i != MI.getNumOperands(); ++i)
 407     addOperand(MI.getOperand(i));
 408   NumImplicitOps = MI.NumImplicitOps;
 409
 410   // Add memory operands.
 411   for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
 412        j = MI.memoperands_end(); i != j; ++i)
 413     addMemOperand(MF, *i);
 414
 415   // Set parent to null.
 416   Parent = 0;
 417
 418   LeakDetector::addGarbageObject(this);
 419 }
 420
 421 MachineInstr::~MachineInstr() {
 422   LeakDetector::removeGarbageObject(this);
 423   assert(MemOperands.empty() &&
 424          "MachineInstr being deleted with live memoperands!");
 425 #ifndef NDEBUG
 426   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 427     assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
 428     assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
 429            "Reg operand def/use list corrupted");
 430   }
 431 #endif
 432 }
 433
 434 /// getRegInfo - If this instruction is embedded into a MachineFunction,
 435 /// return the MachineRegisterInfo object for the current function, otherwise
 436 /// return null.
 437 MachineRegisterInfo *MachineInstr::getRegInfo() {
 438   if (MachineBasicBlock *MBB = getParent())
 439     return &MBB->getParent()->getRegInfo();
 440   return 0;
 441 }
 442
 443 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
 444 /// this instruction from their respective use lists.  This requires that the
 445 /// operands already be on their use lists.
 446 void MachineInstr::RemoveRegOperandsFromUseLists() {
 447   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 448     if (Operands[i].isReg())
 449       Operands[i].RemoveRegOperandFromRegInfo();
 450   }
 451 }
 452
 453 /// AddRegOperandsToUseLists - Add all of the register operands in
 454 /// this instruction from their respective use lists.  This requires that the
 455 /// operands not be on their use lists yet.
 456 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
 457   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 458     if (Operands[i].isReg())
 459       Operands[i].AddRegOperandToRegInfo(&RegInfo);
 460   }
 461 }
 462
 463
 464 /// addOperand - Add the specified operand to the instruction.  If it is an
 465 /// implicit operand, it is added to the end of the operand list.  If it is
 466 /// an explicit operand it is added at the end of the explicit operand list
 467 /// (before the first implicit operand).
 468 void MachineInstr::addOperand(const MachineOperand &Op) {
 469   bool isImpReg = Op.isReg() && Op.isImplicit();
 470   assert((isImpReg || !OperandsComplete()) &&
 471          "Trying to add an operand to a machine instr that is already done!");
 472
 473   MachineRegisterInfo *RegInfo = getRegInfo();
 474
 475   // If we are adding the operand to the end of the list, our job is simpler.
 476   // This is true most of the time, so this is a reasonable optimization.
 477   if (isImpReg || NumImplicitOps == 0) {
 478     // We can only do this optimization if we know that the operand list won't
 479     // reallocate.
 480     if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
 481       Operands.push_back(Op);
 482
 483       // Set the parent of the operand.
 484       Operands.back().ParentMI = this;
 485
 486       // If the operand is a register, update the operand's use list.
 487       if (Op.isReg())
 488         Operands.back().AddRegOperandToRegInfo(RegInfo);
 489       return;
 490     }
 491   }
 492
 493   // Otherwise, we have to insert a real operand before any implicit ones.
 494   unsigned OpNo = Operands.size()-NumImplicitOps;
 495
 496   // If this instruction isn't embedded into a function, then we don't need to
 497   // update any operand lists.
 498   if (RegInfo == 0) {
 499     // Simple insertion, no reginfo update needed for other register operands.
 500     Operands.insert(Operands.begin()+OpNo, Op);
 501     Operands[OpNo].ParentMI = this;
 502
 503     // Do explicitly set the reginfo for this operand though, to ensure the
 504     // next/prev fields are properly nulled out.
 505     if (Operands[OpNo].isReg())
 506       Operands[OpNo].AddRegOperandToRegInfo(0);
 507
 508   } else if (Operands.size()+1 <= Operands.capacity()) {
 509     // Otherwise, we have to remove register operands from their register use
 510     // list, add the operand, then add the register operands back to their use
 511     // list.  This also must handle the case when the operand list reallocates
 512     // to somewhere else.
 513
 514     // If insertion of this operand won't cause reallocation of the operand
 515     // list, just remove the implicit operands, add the operand, then re-add all
 516     // the rest of the operands.
 517     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 518       assert(Operands[i].isReg() && "Should only be an implicit reg!");
 519       Operands[i].RemoveRegOperandFromRegInfo();
 520     }
 521
 522     // Add the operand.  If it is a register, add it to the reg list.
 523     Operands.insert(Operands.begin()+OpNo, Op);
 524     Operands[OpNo].ParentMI = this;
 525
 526     if (Operands[OpNo].isReg())
 527       Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
 528
 529     // Re-add all the implicit ops.
 530     for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
 531       assert(Operands[i].isReg() && "Should only be an implicit reg!");
 532       Operands[i].AddRegOperandToRegInfo(RegInfo);
 533     }
 534   } else {
 535     // Otherwise, we will be reallocating the operand list.  Remove all reg
 536     // operands from their list, then readd them after the operand list is
 537     // reallocated.
 538     RemoveRegOperandsFromUseLists();
 539
 540     Operands.insert(Operands.begin()+OpNo, Op);
 541     Operands[OpNo].ParentMI = this;
 542
 543     // Re-add all the operands.
 544     AddRegOperandsToUseLists(*RegInfo);
 545   }
 546 }
 547
 548 /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
 549 /// fewer operand than it started with.
 550 ///
 551 void MachineInstr::RemoveOperand(unsigned OpNo) {
 552   assert(OpNo < Operands.size() && "Invalid operand number");
 553
 554   // Special case removing the last one.
 555   if (OpNo == Operands.size()-1) {
 556     // If needed, remove from the reg def/use list.
 557     if (Operands.back().isReg() && Operands.back().isOnRegUseList())
 558       Operands.back().RemoveRegOperandFromRegInfo();
 559
 560     Operands.pop_back();
 561     return;
 562   }
 563
 564   // Otherwise, we are removing an interior operand.  If we have reginfo to
 565   // update, remove all operands that will be shifted down from their reg lists,
 566   // move everything down, then re-add them.
 567   MachineRegisterInfo *RegInfo = getRegInfo();
 568   if (RegInfo) {
 569     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 570       if (Operands[i].isReg())
 571         Operands[i].RemoveRegOperandFromRegInfo();
 572     }
 573   }
 574
 575   Operands.erase(Operands.begin()+OpNo);
 576
 577   if (RegInfo) {
 578     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 579       if (Operands[i].isReg())
 580         Operands[i].AddRegOperandToRegInfo(RegInfo);
 581     }
 582   }
 583 }
 584
 585 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
 586 /// referencing arbitrary storage.
 587 void MachineInstr::addMemOperand(MachineFunction &MF,
 588                                  const MachineMemOperand &MO) {
 589   MemOperands.push_back(MO);
 590 }
 591
 592 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
 593 void MachineInstr::clearMemOperands(MachineFunction &MF) {
 594   MemOperands.clear();
 595 }
 596
 597
 598 /// removeFromParent - This method unlinks 'this' from the containing basic
 599 /// block, and returns it, but does not delete it.
 600 MachineInstr *MachineInstr::removeFromParent() {
 601   assert(getParent() && "Not embedded in a basic block!");
 602   getParent()->remove(this);
 603   return this;
 604 }
 605
 606
 607 /// eraseFromParent - This method unlinks 'this' from the containing basic
 608 /// block, and deletes it.
 609 void MachineInstr::eraseFromParent() {
 610   assert(getParent() && "Not embedded in a basic block!");
 611   getParent()->erase(this);
 612 }
 613
 614
 615 /// OperandComplete - Return true if it's illegal to add a new operand
 616 ///
 617 bool MachineInstr::OperandsComplete() const {
 618   unsigned short NumOperands = TID->getNumOperands();
 619   if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
 620     return true;  // Broken: we have all the operands of this instruction!
 621   return false;
 622 }
 623
 624 /// getNumExplicitOperands - Returns the number of non-implicit operands.
 625 ///
 626 unsigned MachineInstr::getNumExplicitOperands() const {
 627   unsigned NumOperands = TID->getNumOperands();
 628   if (!TID->isVariadic())
 629     return NumOperands;
 630
 631   for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
 632     const MachineOperand &MO = getOperand(i);
 633     if (!MO.isReg() || !MO.isImplicit())
 634       NumOperands++;
 635   }
 636   return NumOperands;
 637 }
 638
 639
 640 /// isLabel - Returns true if the MachineInstr represents a label.
 641 ///
 642 bool MachineInstr::isLabel() const {
 643   return getOpcode() == TargetInstrInfo::DBG_LABEL ||
 644          getOpcode() == TargetInstrInfo::EH_LABEL ||
 645          getOpcode() == TargetInstrInfo::GC_LABEL;
 646 }
 647
 648 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
 649 ///
 650 bool MachineInstr::isDebugLabel() const {
 651   return getOpcode() == TargetInstrInfo::DBG_LABEL;
 652 }
 653
 654 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
 655 /// the specific register or -1 if it is not found. It further tightening
 656 /// the search criteria to a use that kills the register if isKill is true.
 657 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
 658                                           const TargetRegisterInfo *TRI) const {
 659   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 660     const MachineOperand &MO = getOperand(i);
 661     if (!MO.isReg() || !MO.isUse())
 662       continue;
 663     unsigned MOReg = MO.getReg();
 664     if (!MOReg)
 665       continue;
 666     if (MOReg == Reg ||
 667         (TRI &&
 668          TargetRegisterInfo::isPhysicalRegister(MOReg) &&
 669          TargetRegisterInfo::isPhysicalRegister(Reg) &&
 670          TRI->isSubRegister(MOReg, Reg)))
 671       if (!isKill || MO.isKill())
 672         return i;
 673   }
 674   return -1;
 675 }
 676
 677 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
 678 /// the specified register or -1 if it is not found. If isDead is true, defs
 679 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
 680 /// also checks if there is a def of a super-register.
 681 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
 682                                           const TargetRegisterInfo *TRI) const {
 683   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 684     const MachineOperand &MO = getOperand(i);
 685     if (!MO.isReg() || !MO.isDef())
 686       continue;
 687     unsigned MOReg = MO.getReg();
 688     if (MOReg == Reg ||
 689         (TRI &&
 690          TargetRegisterInfo::isPhysicalRegister(MOReg) &&
 691          TargetRegisterInfo::isPhysicalRegister(Reg) &&
 692          TRI->isSubRegister(MOReg, Reg)))
 693       if (!isDead || MO.isDead())
 694         return i;
 695   }
 696   return -1;
 697 }
 698
 699 /// findFirstPredOperandIdx() - Find the index of the first operand in the
 700 /// operand list that is used to represent the predicate. It returns -1 if
 701 /// none is found.
 702 int MachineInstr::findFirstPredOperandIdx() const {
 703   const TargetInstrDesc &TID = getDesc();
 704   if (TID.isPredicable()) {
 705     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
 706       if (TID.OpInfo[i].isPredicate())
 707         return i;
 708   }
 709
 710   return -1;
 711 }
 712
 713 /// isRegTiedToUseOperand - Given the index of a register def operand,
 714 /// check if the register def is tied to a source operand, due to either
 715 /// two-address elimination or inline assembly constraints. Returns the
 716 /// first tied use operand index by reference is UseOpIdx is not null.
 717 bool MachineInstr::
 718 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
 719   if (getOpcode() == TargetInstrInfo::INLINEASM) {
 720     assert(DefOpIdx >= 2);
 721     const MachineOperand &MO = getOperand(DefOpIdx);
 722     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
 723       return false;
 724     // Determine the actual operand index that corresponds to this index.
 725     unsigned DefNo = 0;
 726     unsigned DefPart = 0;
 727     for (unsigned i = 1, e = getNumOperands(); i < e; ) {
 728       const MachineOperand &FMO = getOperand(i);
 729       // After the normal asm operands there may be additional imp-def regs.
 730       if (!FMO.isImm())
 731         return false;
 732       // Skip over this def.
 733       unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
 734       unsigned PrevDef = i + 1;
 735       i = PrevDef + NumOps;
 736       if (i > DefOpIdx) {
 737         DefPart = DefOpIdx - PrevDef;
 738         break;
 739       }
 740       ++DefNo;
 741     }
 742     for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
 743       const MachineOperand &FMO = getOperand(i);
 744       if (!FMO.isImm())
 745         continue;
 746       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
 747         continue;
 748       unsigned Idx;
 749       if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
 750           Idx == DefNo) {
 751         if (UseOpIdx)
 752           *UseOpIdx = (unsigned)i + 1 + DefPart;
 753         return true;
 754       }
 755     }
 756     return false;
 757   }
 758
 759   assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
 760   const TargetInstrDesc &TID = getDesc();
 761   for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
 762     const MachineOperand &MO = getOperand(i);
 763     if (MO.isReg() && MO.isUse() &&
 764         TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
 765       if (UseOpIdx)
 766         *UseOpIdx = (unsigned)i;
 767       return true;
 768     }
 769   }
 770   return false;
 771 }
 772
 773 /// isRegTiedToDefOperand - Return true if the operand of the specified index
 774 /// is a register use and it is tied to an def operand. It also returns the def
 775 /// operand index by reference.
 776 bool MachineInstr::
 777 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
 778   if (getOpcode() == TargetInstrInfo::INLINEASM) {
 779     const MachineOperand &MO = getOperand(UseOpIdx);
 780     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
 781       return false;
 782
 783     // Find the flag operand corresponding to UseOpIdx
 784     unsigned FlagIdx, NumOps=0;
 785     for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
 786       const MachineOperand &UFMO = getOperand(FlagIdx);
 787       // After the normal asm operands there may be additional imp-def regs.
 788       if (!UFMO.isImm())
 789         return false;
 790       NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
 791       assert(NumOps < getNumOperands() && "Invalid inline asm flag");
 792       if (UseOpIdx < FlagIdx+NumOps+1)
 793         break;
 794     }
 795     if (FlagIdx >= UseOpIdx)
 796       return false;
 797     const MachineOperand &UFMO = getOperand(FlagIdx);
 798     unsigned DefNo;
 799     if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
 800       if (!DefOpIdx)
 801         return true;
 802
 803       unsigned DefIdx = 1;
 804       // Remember to adjust the index. First operand is asm string, then there
 805       // is a flag for each.
 806       while (DefNo) {
 807         const MachineOperand &FMO = getOperand(DefIdx);
 808         assert(FMO.isImm());
 809         // Skip over this def.
 810         DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
 811         --DefNo;
 812       }
 813       *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
 814       return true;
 815     }
 816     return false;
 817   }
 818
 819   const TargetInstrDesc &TID = getDesc();
 820   if (UseOpIdx >= TID.getNumOperands())
 821     return false;
 822   const MachineOperand &MO = getOperand(UseOpIdx);
 823   if (!MO.isReg() || !MO.isUse())
 824     return false;
 825   int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
 826   if (DefIdx == -1)
 827     return false;
 828   if (DefOpIdx)
 829     *DefOpIdx = (unsigned)DefIdx;
 830   return true;
 831 }
 832
 833 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
 834 ///
 835 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
 836   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 837     const MachineOperand &MO = MI->getOperand(i);
 838     if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
 839       continue;
 840     for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
 841       MachineOperand &MOp = getOperand(j);
 842       if (!MOp.isIdenticalTo(MO))
 843         continue;
 844       if (MO.isKill())
 845         MOp.setIsKill();
 846       else
 847         MOp.setIsDead();
 848       break;
 849     }
 850   }
 851 }
 852
 853 /// copyPredicates - Copies predicate operand(s) from MI.
 854 void MachineInstr::copyPredicates(const MachineInstr *MI) {
 855   const TargetInstrDesc &TID = MI->getDesc();
 856   if (!TID.isPredicable())
 857     return;
 858   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 859     if (TID.OpInfo[i].isPredicate()) {
 860       // Predicated operands must be last operands.
 861       addOperand(MI->getOperand(i));
 862     }
 863   }
 864 }
 865
 866 /// isSafeToMove - Return true if it is safe to move this instruction. If
 867 /// SawStore is set to true, it means that there is a store (or call) between
 868 /// the instruction's location and its intended destination.
 869 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
 870                                 bool &SawStore) const {
 871   // Ignore stuff that we obviously can't move.
 872   if (TID->mayStore() || TID->isCall()) {
 873     SawStore = true;
 874     return false;
 875   }
 876   if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
 877     return false;
 878
 879   // See if this instruction does a load.  If so, we have to guarantee that the
 880   // loaded value doesn't change between the load and the its intended
 881   // destination. The check for isInvariantLoad gives the targe the chance to
 882   // classify the load as always returning a constant, e.g. a constant pool
 883   // load.
 884   if (TID->mayLoad() && !TII->isInvariantLoad(this))
 885     // Otherwise, this is a real load.  If there is a store between the load and
 886     // end of block, or if the load is volatile, we can't move it.
 887     return !SawStore && !hasVolatileMemoryRef();
 888
 889   return true;
 890 }
 891
 892 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
 893 /// instruction which defined the specified register instead of copying it.
 894 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
 895                                  unsigned DstReg) const {
 896   bool SawStore = false;
 897   if (!getDesc().isRematerializable() ||
 898       !TII->isTriviallyReMaterializable(this) ||
 899       !isSafeToMove(TII, SawStore))
 900     return false;
 901   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 902     const MachineOperand &MO = getOperand(i);
 903     if (!MO.isReg())
 904       continue;
 905     // FIXME: For now, do not remat any instruction with register operands.
 906     // Later on, we can loosen the restriction is the register operands have
 907     // not been modified between the def and use. Note, this is different from
 908     // MachineSink because the code is no longer in two-address form (at least
 909     // partially).
 910     if (MO.isUse())
 911       return false;
 912     else if (!MO.isDead() && MO.getReg() != DstReg)
 913       return false;
 914   }
 915   return true;
 916 }
 917
 918 /// hasVolatileMemoryRef - Return true if this instruction may have a
 919 /// volatile memory reference, or if the information describing the
 920 /// memory reference is not available. Return false if it is known to
 921 /// have no volatile memory references.
 922 bool MachineInstr::hasVolatileMemoryRef() const {
 923   // An instruction known never to access memory won't have a volatile access.
 924   if (!TID->mayStore() &&
 925       !TID->mayLoad() &&
 926       !TID->isCall() &&
 927       !TID->hasUnmodeledSideEffects())
 928     return false;
 929
 930   // Otherwise, if the instruction has no memory reference information,
 931   // conservatively assume it wasn't preserved.
 932   if (memoperands_empty())
 933     return true;
 934
 935   // Check the memory reference information for volatile references.
 936   for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
 937        E = memoperands_end(); I != E; ++I)
 938     if (I->isVolatile())
 939       return true;
 940
 941   return false;
 942 }
 943
 944 void MachineInstr::dump() const {
 945   errs() << "  " << *this;
 946 }
 947
 948 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
 949   // Specialize printing if op#0 is definition
 950   unsigned StartOp = 0;
 951   if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
 952     getOperand(0).print(OS, TM);
 953     OS << " = ";
 954     ++StartOp;   // Don't print this operand again!
 955   }
 956
 957   OS << getDesc().getName();
 958
 959   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
 960     if (i != StartOp)
 961       OS << ",";
 962     OS << " ";
 963     getOperand(i).print(OS, TM);
 964   }
 965
 966   if (!memoperands_empty()) {
 967     OS << ", Mem:";
 968     for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
 969          e = memoperands_end(); i != e; ++i) {
 970       const MachineMemOperand &MRO = *i;
 971       const Value *V = MRO.getValue();
 972
 973       assert((MRO.isLoad() || MRO.isStore()) &&
 974              "SV has to be a load, store or both.");
 975
 976       if (MRO.isVolatile())
 977         OS << "Volatile ";
 978
 979       if (MRO.isLoad())
 980         OS << "LD";
 981       if (MRO.isStore())
 982         OS << "ST";
 983
 984       OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
 985
 986       if (!V)
 987         OS << "<unknown>";
 988       else if (!V->getName().empty())
 989         OS << V->getName();
 990       else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
 991         PSV->print(OS);
 992       } else
 993         OS << V;
 994
 995       OS << " + " << MRO.getOffset() << "]";
 996     }
 997   }
 998
 999   if (!debugLoc.isUnknown()) {
1000     const MachineFunction *MF = getParent()->getParent();
1001     DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1002     DICompileUnit CU(DLT.CompileUnit);
1003     std::string Dir, Fn;
1004     OS << " [dbg: "
1005        << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
1006        << DLT.Line << ","
1007        << DLT.Col  << "]";
1008   }
1009
1010   OS << "\n";
1011 }
1012
1013 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1014                                      const TargetRegisterInfo *RegInfo,
1015                                      bool AddIfNotFound) {
1016   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1017   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1018   bool Found = false;
1019   SmallVector<unsigned,4> DeadOps;
1020   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1021     MachineOperand &MO = getOperand(i);
1022     if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1023       continue;
1024     unsigned Reg = MO.getReg();
1025     if (!Reg)
1026       continue;
1027
1028     if (Reg == IncomingReg) {
1029       if (!Found) {
1030         if (MO.isKill())
1031           // The register is already marked kill.
1032           return true;
1033         if (isPhysReg && isRegTiedToDefOperand(i))
1034           // Two-address uses of physregs must not be marked kill.
1035           return true;
1036         MO.setIsKill();
1037         Found = true;
1038       }
1039     } else if (hasAliases && MO.isKill() &&
1040                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1041       // A super-register kill already exists.
1042       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1043         return true;
1044       if (RegInfo->isSubRegister(IncomingReg, Reg))
1045         DeadOps.push_back(i);
1046     }
1047   }
1048
1049   // Trim unneeded kill operands.
1050   while (!DeadOps.empty()) {
1051     unsigned OpIdx = DeadOps.back();
1052     if (getOperand(OpIdx).isImplicit())
1053       RemoveOperand(OpIdx);
1054     else
1055       getOperand(OpIdx).setIsKill(false);
1056     DeadOps.pop_back();
1057   }
1058
1059   // If not found, this means an alias of one of the operands is killed. Add a
1060   // new implicit operand if required.
1061   if (!Found && AddIfNotFound) {
1062     addOperand(MachineOperand::CreateReg(IncomingReg,
1063                                          false /*IsDef*/,
1064                                          true  /*IsImp*/,
1065                                          true  /*IsKill*/));
1066     return true;
1067   }
1068   return Found;
1069 }
1070
1071 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1072                                    const TargetRegisterInfo *RegInfo,
1073                                    bool AddIfNotFound) {
1074   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1075   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1076   bool Found = false;
1077   SmallVector<unsigned,4> DeadOps;
1078   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1079     MachineOperand &MO = getOperand(i);
1080     if (!MO.isReg() || !MO.isDef())
1081       continue;
1082     unsigned Reg = MO.getReg();
1083     if (!Reg)
1084       continue;
1085
1086     if (Reg == IncomingReg) {
1087       if (!Found) {
1088         if (MO.isDead())
1089           // The register is already marked dead.
1090           return true;
1091         MO.setIsDead();
1092         Found = true;
1093       }
1094     } else if (hasAliases && MO.isDead() &&
1095                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1096       // There exists a super-register that's marked dead.
1097       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1098         return true;
1099       if (RegInfo->getSubRegisters(IncomingReg) &&
1100           RegInfo->getSuperRegisters(Reg) &&
1101           RegInfo->isSubRegister(IncomingReg, Reg))
1102         DeadOps.push_back(i);
1103     }
1104   }
1105
1106   // Trim unneeded dead operands.
1107   while (!DeadOps.empty()) {
1108     unsigned OpIdx = DeadOps.back();
1109     if (getOperand(OpIdx).isImplicit())
1110       RemoveOperand(OpIdx);
1111     else
1112       getOperand(OpIdx).setIsDead(false);
1113     DeadOps.pop_back();
1114   }
1115
1116   // If not found, this means an alias of one of the operands is dead. Add a
1117   // new implicit operand if required.
1118   if (Found || !AddIfNotFound)
1119     return Found;
1120
1121   addOperand(MachineOperand::CreateReg(IncomingReg,
1122                                        true  /*IsDef*/,
1123                                        true  /*IsImp*/,
1124                                        false /*IsKill*/,
1125                                        true  /*IsDead*/));
1126   return true;
1127 }