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13 Writing an LLVM Compiler Backend
14 </div>
16 <ol>
18 <ul>
23 </ul>
27 <ul>
31 </ul></li>
33 <ul>
37 </ul></li>
39 <ul>
41 <ul>
46 </ul></li>
48 </ul></li>
52 <ul>
55 </ul></li>
56 </ol>
61 </div>
63 <!-- *********************************************************************** -->
66 </div>
67 <!-- *********************************************************************** -->
71 <p>
72 This document describes techniques for writing compiler backends that convert
73 the LLVM Intermediate Representation (IR) to code for a specified machine or
74 other languages. Code intended for a specific machine can take the form of
75 either assembly code or binary code (usable for a JIT compiler).
76 </p>
78 <p>
79 The backend of LLVM features a target-independent code generator that may create
80 output for several types of target CPUs — including X86, PowerPC, Alpha,
81 and SPARC. The backend may also be used to generate code targeted at SPUs of the
82 Cell processor or GPUs to support the execution of compute kernels.
83 </p>
85 <p>
86 The document focuses on existing examples found in subdirectories
88 document focuses on the example of creating a static compiler (one that emits
89 text assembly) for a SPARC target, because SPARC has fairly standard
90 characteristics, such as a RISC instruction set and straightforward calling
91 conventions.
92 </p>
94 </div>
98 </div>
102 <p>
103 The audience for this document is anyone who needs to write an LLVM backend to
104 generate code for a specific hardware or software target.
105 </p>
107 </div>
111 </div>
115 <p>
116 These essential documents must be read before reading this document:
117 </p>
119 <ul>
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
135 support LLVM code generation. TableGen processes input from a target
137 used for code generation.</li>
141 several SelectionDAG processing steps.</li>
142 </ul>
144 <p>
145 To follow the SPARC examples in this document, have a copy of
149 Reference Manual</a></i>. For more about the GNU Assembler format
153 machine dependent features.
154 </p>
156 </div>
160 </div>
164 <p>
165 To write a compiler backend for LLVM that converts the LLVM IR to code for a
166 specified target (machine or other language), follow these steps:
167 </p>
169 <ul>
170 <li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
174 change the file names for your target. Similarly, change code that
177 <li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
184 <li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
190 <li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
198 data types that are not supported natively in a SelectionDAG. </li>
200 <li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
206 <li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
211 <li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
213 </ul>
215 <p>
217 then implement them later. Initially, you may not know which private members
218 that the class will need and which components will need to be subclassed.
219 </p>
221 </div>
225 </div>
229 <p>
230 To actually create your compiler backend, you need to create and modify a few
231 files. The absolute minimum is discussed here. But to actually use the LLVM
232 target-independent code generator, you must perform the steps described in
234 Target-Independent Code Generator</a> document.
235 </p>
237 <p>
239 the files related to your target. If your target is called "Dummy," create the
241 </p>
243 <p>
244 In this new
253 target).
254 </p>
256 <p>
260 </p>
262 <p>
263 To make your target actually do something, you need to implement a subclass of
267 target independent code generator, you should do what all current machine
270 </p>
272 <p>
273 To get LLVM to actually build and link your target, you need to add it to
277 target to the lists there (some creativity required), and then
280 </p>
282 </div>
284 <!-- *********************************************************************** -->
287 </div>
288 <!-- *********************************************************************** -->
292 <p>
295 class should be specialized by a concrete target class that implements the
299 processes numerous command-line options.
300 </p>
302 <p>
305 should name the files that you create to reflect your specific target. For
308 </p>
310 <p>
318 characteristics, such as data type size and alignment requirements.
319 </p>
321 <p>
322 For instance, for the SPARC target, the header file
325 </p>
328 <pre>
329 namespace llvm {
331 class Module;
333 class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size & alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
339 protected:
340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
342 public:
345 virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &InstrInfo.getRegisterInfo();
350 }
351 virtual const TargetData *getTargetData() const { return &DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &M);
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
357 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
358 std::ostream &Out);
359 };
361 } // end namespace llvm
362 </pre>
363 </div>
365 </div>
370 <ul>
376 </ul>
380 <ul>
383 </ul>
385 <p>
388 machine, including characteristics such as pointer size, alignment, and
389 endianness. For example, the constructor for SparcTargetMachine contains the
390 following:
391 </p>
394 <pre>
396 : DataLayout("E-p:32:32-f128:128:128"),
397 Subtarget(M, FS), InstrInfo(Subtarget),
399 }
400 </pre>
401 </div>
403 </div>
409 <ul>
414 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
415 first value is pointer size, and the second value is both ABI and preferred
416 alignment.</li>
421 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
422 by three values: the first indicates the size of a long double, then ABI
423 alignment, and then ABI preferred alignment.</li>
424 </ul>
426 </div>
428 <!-- *********************************************************************** -->
431 </div>
432 <!-- *********************************************************************** -->
436 <p>
438 what other LLVM tools use to be able to lookup and use your target at
440 there are helper templates which should take care of the work for you.</p>
442 <p>
444 represent the target during registration. Then, in the target's TargetInfo
445 library, the target should define that object and use
446 the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
447 </p>
450 <pre>
451 Target llvm::TheSparcTarget;
453 extern "C" void LLVMInitializeSparcTargetInfo() {
456 }
457 </pre>
458 </div>
460 <p>
462 target triple. In addition, most targets will also register additional features
463 which are available in separate libraries. These registration steps are
464 separate, because some clients may wish to only link in some parts of the target
465 -- the JIT code generator does not require the use of the assembler printer, for
466 example. Here is an example of registering the Sparc assembly printer:
467 </p>
470 <pre>
471 extern "C" void LLVMInitializeSparcAsmPrinter() {
473 }
474 </pre>
475 </div>
477 <p>
478 For more information, see
480 </p>
482 </div>
484 <!-- *********************************************************************** -->
487 </div>
488 <!-- *********************************************************************** -->
492 <p>
493 You should describe a concrete target-specific class that represents the
496 file data that is used for register allocation. It also describes the
497 interactions between registers.
498 </p>
500 <p>
501 You also need to define register classes to categorize related registers. A
502 register class should be added for groups of registers that are all treated the
503 same way for some instruction. Typical examples are register classes for
504 integer, floating-point, or vector registers. A register allocator allows an
505 instruction to use any register in a specified register class to perform the
506 instruction in a similar manner. Register classes allocate virtual registers to
507 instructions from these sets, and register classes let the target-independent
508 register allocator automatically choose the actual registers.
509 </p>
511 <p>
512 Much of the code for registers, including register definition, register aliases,
517 </p>
519 </div>
521 <!-- ======================================================================= -->
524 </div>
528 <p>
534 specify any aliases.
535 </p>
538 <pre>
540 string Namespace = "";
541 string AsmName = n;
542 string Name = n;
543 int SpillSize = 0;
544 int SpillAlignment = 0;
548 }
549 </pre>
550 </div>
552 <p>
554 definitions that utilize the Register class, such as:
555 </p>
558 <pre>
560 </pre>
561 </div>
563 <p>
569 different modes: the first element is for X86-64, the second for exception
571 that indicates the gcc number is undefined, and -2 indicates the register number
572 is invalid for this mode.
573 </p>
575 <p>
578 </p>
581 <pre>
582 static const unsigned GR8[] = { X86::AL, ... };
584 const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
586 const TargetRegisterDesc RegisterDescriptors[] = {
587 ...
589 </pre>
590 </div>
592 <p>
596 </p>
599 <pre>
600 struct TargetRegisterDesc {
601 const char *AsmName; // Assembly language name for the register
602 const char *Name; // Printable name for the reg (for debugging)
603 const unsigned *AliasSet; // Register Alias Set
604 const unsigned *SubRegs; // Sub-register set
605 const unsigned *ImmSubRegs; // Immediate sub-register set
606 const unsigned *SuperRegs; // Super-register set
607 };</pre>
608 </div>
610 <p>
615 example, other definitions establish the registers "<tt>AX</tt>",
618 set.
619 </p>
621 <p>
626 </p>
629 <pre>
630 class RegisterWithSubRegs<string n,
632 let SubRegs = subregs;
633 }
634 </pre>
635 </div>
637 <p>
641 numbers, which is a feature common to these subclasses. Note the use of
644 </p>
647 <pre>
650 let Namespace = "SP";
651 }
652 // Ri - 32-bit integer registers
655 let Num = num;
656 }
657 // Rf - 32-bit floating-point registers
660 let Num = num;
661 }
662 // Rd - Slots in the FP register file for 64-bit
663 floating-point values.
666 let Num = num;
667 let SubRegs = subregs;
668 }
669 </pre>
670 </div>
672 <p>
675 </p>
678 <pre>
682 ...
687 ...
692 </pre>
693 </div>
695 <p>
697 double-precision floating-point registers that are aliases for pairs of
698 single-precision floating-point sub-registers. In addition to aliases, the
699 sub-register and super-register relationships of the defined register are in
700 fields of a register's TargetRegisterDesc.
701 </p>
703 </div>
705 <!-- ======================================================================= -->
708 </div>
712 <p>
714 define an object that represents a group of related registers and also defines
715 the default allocation order of the registers. A target description file
717 classes using the following class:
718 </p>
721 <pre>
722 class RegisterClass<string namespace,
725 string Namespace = namespace;
727 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
728 int Alignment = alignment;
730 // CopyCost is the cost of copying a value between two registers
731 // default value 1 means a single instruction
732 // A negative value means copying is extremely expensive or impossible
733 int CopyCost = 1;
736 // for register classes that are subregisters of this class
739 code MethodProtos = [{}]; // to insert arbitrary code
740 code MethodBodies = [{}];
741 }
742 </pre>
743 </div>
747 <ul>
757 data in different configurations. For example a register that can process a
762 alignment required of the registers when they are stored or loaded to
763 memory.</li>
768 register allocator.</li>
769 </ul>
771 <p>
774 classes, the first argument defines the namespace with the string
777 a group of 16 double-precision registers
780 code into generated output.
781 </p>
784 <pre>
786 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
787 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
790 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>;
791
793 [L0, L1, L2, L3, L4, L5, L6, L7,
794 I0, I1, I2, I3, I4, I5,
795 O0, O1, O2, O3, O4, O5, O7,
796 G1,
797 // Non-allocatable regs:
798 G2, G3, G4,
799 O6, // stack ptr
800 I6, // frame ptr
801 I7, // return address
802 G0, // constant zero
803 G5, G6, G7 // reserved for kernel
804 ]> {
805 let MethodProtos = [{
806 iterator allocation_order_end(const MachineFunction &MF) const;
807 }];
808 let MethodBodies = [{
809 IntRegsClass::iterator
810 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
811 return end() - 10 // Don't allocate special registers
812 -1;
813 }
814 }];
815 }
816 </pre>
817 </div>
819 <p>
821 that are intended for inclusion in other source code that you write.
823 which should be included in the header file for the implementation of the SPARC
827 base. It also specifies types, based upon the defined register
829 </p>
831 <p>
834 register implementation. The code below shows only the generated integer
835 registers and associated register classes. The order of registers
837 the target description file. Take special note of the use
841 </p>
844 <pre> // IntRegs Register Class...
845 static const unsigned IntRegs[] = {
846 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
847 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
848 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
849 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
850 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
851 SP::G6, SP::G7,
852 };
854 // IntRegsVTs Register Class Value Types...
855 static const MVT::ValueType IntRegsVTs[] = {
856 MVT::i32, MVT::Other
857 };
859 namespace SP { // Register class instances
860 DFPRegsClass DFPRegsRegClass;
861 FPRegsClass FPRegsRegClass;
862 IntRegsClass IntRegsRegClass;
863 ...
864 // IntRegs Sub-register Classess...
865 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
866 NULL
867 };
868 ...
869 // IntRegs Super-register Classess...
870 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
871 NULL
872 };
873 ...
874 // IntRegs Register Class sub-classes...
875 static const TargetRegisterClass* const IntRegsSubclasses [] = {
876 NULL
877 };
878 ...
879 // IntRegs Register Class super-classes...
880 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
881 NULL
882 };
883 ...
884 IntRegsClass::iterator
885 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
886 return end()-10 // Don't allocate special registers
887 -1;
888 }
890 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
891 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
893 }
894 </pre>
895 </div>
897 </div>
899 <!-- ======================================================================= -->
903 </div>
907 <p>
911 overridden. Here is a list of functions that are overridden for the SPARC
913 </p>
915 <ul>
917 in the order of the desired callee-save stack frame offset.</li>
920 register classes with which to spill each callee saved register.</li>
923 register numbers, indicating if a particular register is unavailable.</li>
926 a dedicated frame pointer register.</li>
929 destroy pseudo instructions are used, this can be called to eliminate
930 them.</li>
933 instructions that may use them.</li>
938 </ul>
940 </div>
942 <!-- *********************************************************************** -->
945 </div>
947 <!-- *********************************************************************** -->
950 <p>
951 During the early stages of code generation, the LLVM IR code is converted to a
954 requirements, and operation properties. For example, is an operation
955 commutative, does an operation load from memory. The various operation node
958 </p>
960 <p>
962 generate much of the code for instruction definition:
963 </p>
965 <ul>
977 target-specific instructions.</li>
980 templates, condition codes, and instructions of an instruction set. For
981 architecture modifications, a different file name may be used. For example,
984 </ul>
986 <p>
989 input files, but its contents are only directly important for subtargets.
990 </p>
992 <p>
994 represents machine instructions supported by a target machine.
996 each of which describes one instruction. An instruction descriptor defines:</p>
998 <ul>
1008 </ul>
1010 <p>
1012 for more complex instruction classes.
1013 </p>
1016 <pre>class Instruction {
1017 string Namespace = "";
1018 dag OutOperandList; // An dag containing the MI def operand list.
1019 dag InOperandList; // An dag containing the MI use operand list.
1020 string AsmString = ""; // The .s format to print the instruction with.
1025 ... remainder not shown for space ...
1026 }
1027 </pre>
1028 </div>
1030 <p>
1032 representing a target-specific instruction that is defined
1034 instructions from the architecture manual of the target machine (such as the
1035 SPARC Architecture Manual for the SPARC target).
1036 </p>
1038 <p>
1039 A single instruction from the architecture manual is often modeled as multiple
1040 target instructions, depending upon its operands. For example, a manual might
1041 describe an add instruction that takes a register or an immediate operand. An
1044 </p>
1046 <p>
1047 You should define a class for each instruction category and define each opcode
1048 as a subclass of the category with appropriate parameters such as the fixed
1049 binary encoding of opcodes and extended opcodes. You should map the register
1050 bits to the bits of the instruction in which they are encoded (for the
1051 JIT). Also you should specify how the instruction should be printed when the
1052 automatic assembly printer is used.
1053 </p>
1055 <p>
1056 As is described in the SPARC Architecture Manual, Version 8, there are three
1059 high bits of a register) instructions. Format 3 is for other instructions.
1060 </p>
1062 <p>
1065 classes are specified for more precise formats: for example
1071 synthetic SPARC instructions.
1072 </p>
1074 <p>
1080 operation value for this category of operation. The second parameter
1085 </p>
1089 "ld [$addr], $dst",
1090 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
1091 </pre>
1092 </div>
1094 <p>
1095 The fourth parameter is the input source, which uses the address
1097 </p>
1101 let PrintMethod = "printMemOperand";
1102 let MIOperandInfo = (ops IntRegs, IntRegs);
1103 }
1104 </pre>
1105 </div>
1107 <p>
1108 The fifth parameter is a string that is used by the assembly printer and can be
1109 left as an empty string until the assembly printer interface is implemented. The
1110 sixth and final parameter is the pattern used to match the instruction during
1111 the SelectionDAG Select Phase described in
1113 Target-Independent Code Generator</a>). This parameter is detailed in the next
1115 </p>
1117 <p>
1118 Instruction class definitions are not overloaded for different operand types, so
1119 separate versions of instructions are needed for register, memory, or immediate
1120 value operands. For example, to perform a Load Integer instruction for a Word
1121 from an immediate operand to a register, the following instruction class is
1122 defined:
1123 </p>
1127 "ld [$addr], $dst",
1128 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
1129 </pre>
1130 </div>
1132 <p>
1133 Writing these definitions for so many similar instructions can involve a lot of
1135 creation of templates to define several instruction classes at once (using
1139 </p>
1144 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1145 !strconcat(OpcStr, " $b, $c, $dst"),
1146 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
1148 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
1149 !strconcat(OpcStr, " $b, $c, $dst"),
1150 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
1151 }
1152 </pre>
1153 </div>
1155 <p>
1159 </p>
1162 <pre>
1165 </pre>
1166 </div>
1168 <p>
1170 are referenced by branch instructions. The following definitions
1174 than' condition for floats.
1175 </p>
1178 <pre>
1182 ...
1186 ...
1187 </pre>
1188 </div>
1190 <p>
1195 </p>
1197 </div>
1199 <!-- ======================================================================= -->
1202 </div>
1206 <p>
1207 The code generator backend maps instruction operands to fields in the
1208 instruction. Operands are assigned to unbound fields in the instruction in the
1209 order they are defined. Fields are bound when they are assigned a value. For
1212 </p>
1215 <pre>
1217 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1218 "xnor $b, $c, $dst",
1219 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
1220 </pre>
1221 </div>
1223 <p>
1226 </p>
1229 <pre>
1232 let Namespace = "SP";
1235 dag OutOperandList = outs;
1236 dag InOperandList = ins;
1237 let AsmString = asmstr;
1238 let Pattern = pattern;
1239 }
1240 </pre>
1241 </div>
1246 <pre>
1256 }
1257 </pre>
1258 </div>
1260 <p>
1264 </p>
1267 <pre>
1272 let op = opVal;
1273 let op3 = op3val;
1277 }
1278 </pre>
1279 </div>
1281 <p>
1287 </p>
1289 </div>
1291 <!-- ======================================================================= -->
1295 </div>
1299 <p>
1303 overridden. Here's a list of functions that are overridden for the SPARC
1305 </p>
1307 <ul>
1309 register move; false, otherwise.</li>
1312 a direct load from a stack slot, return the register number of the
1316 a direct store to a stack slot, return the register number of the
1322 slot.</li>
1325 slot.</li>
1332 load or store instruction for the specified operand(s).</li>
1333 </ul>
1335 </div>
1337 <!-- ======================================================================= -->
1340 </div>
1343 <p>
1344 Performance can be improved by combining instructions or by eliminating
1348 a machine basic block (MBB) for opportunities for improvement, such as branch
1353 instructions.
1354 </p>
1356 <p>
1360 implementation is shown below.
1361 </p>
1365 <ul>
1367 examined.</li>
1371 the destination.</li>
1377 operands to evaluate a condition for a conditional branch.</li>
1378 </ul>
1380 <p>
1381 In the simplest case, if a block ends without a branch, then it falls through to
1385 function parameters and the code for the simplest case.
1386 </p>
1392 {
1393 MachineBasicBlock::iterator I = MBB.end();
1394 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1395 return false;
1396 </pre>
1397 </div>
1399 <p>
1400 If a block ends with a single unconditional branch instruction, then
1403 </p>
1406 <pre>
1407 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1409 return false;
1410 }
1411 </pre>
1412 </div>
1414 <p>
1415 If a block ends with two unconditional branches, then the second branch is never
1416 reached. In that situation, as shown below, remove the last branch instruction
1418 </p>
1421 <pre>
1422 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
1423 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1425 I = LastInst;
1426 I->eraseFromParent();
1427 return false;
1428 }
1429 </pre>
1430 </div>
1432 <p>
1433 A block may end with a single conditional branch instruction that falls through
1434 to successor block if the condition evaluates to false. In that case,
1438 </p>
1441 <pre>
1442 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1443 // Block ends with fall-through condbranch.
1447 return false;
1448 }
1449 </pre>
1450 </div>
1452 <p>
1453 If a block ends with both a conditional branch and an ensuing unconditional
1455 branch destination (assuming it corresponds to a conditional evaluation of
1460 </p>
1463 <pre>
1464 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1466 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
1467 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
1472 return false;
1473 }
1474 </pre>
1475 </div>
1477 <p>
1478 For the last two cases (ending with a single conditional branch or ending with
1479 one conditional and one unconditional branch), the operands returned in
1481 create new branches or perform other operations. An implementation
1484 </p>
1486 <p>
1490 return true if it encounters a terminator it cannot handle, such as an indirect
1491 branch.
1492 </p>
1494 </div>
1496 <!-- *********************************************************************** -->
1499 </div>
1500 <!-- *********************************************************************** -->
1504 <p>
1507 instructions. During code generation, instruction selection passes are performed
1508 to convert non-native DAG instructions into native target-specific
1510 match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1512 operations for branch instructions. Later, the code in
1515 </p>
1517 <p>
1518 TableGen generates code for instruction selection using the following target
1519 description input files:
1520 </p>
1522 <ul>
1528 conventions for the target architecture, and it generates
1531 </ul>
1533 <p>
1534 The implementation of an instruction selection pass must include a header that
1537 selection pass into the queue of passes to run.
1538 </p>
1540 <p>
1545 SelectionDAG Instruction Selection Process</a>.
1546 </p>
1548 <p>
1549 To describe instruction selector behavior, you should add patterns for lowering
1553 the last parameter describes a pattern with the store DAG operator.
1554 </p>
1557 <pre>
1560 </pre>
1561 </div>
1563 <p>
1566 </p>
1569 <pre>
1571 </pre>
1572 </div>
1574 <p>
1576 function defined in an implementation of the Instructor Selector (such
1578 </p>
1580 <p>
1582 defined below:
1583 </p>
1586 <pre>
1587 def store : PatFrag<(ops node:$val, node:$ptr),
1588 (st node:$val, node:$ptr), [{
1591 ST->getAddressingMode() == ISD::UNINDEXED;
1592 return false;
1593 }]>;
1594 </pre>
1595 </div>
1597 <p>
1602 </p>
1605 <pre>
1606 SDNode *SelectCode(SDValue N) {
1607 ...
1609 switch (N.getOpcode()) {
1610 case ISD::STORE: {
1611 switch (NVT) {
1612 default:
1613 return Select_ISD_STORE(N);
1614 break;
1615 }
1616 break;
1617 }
1618 ...
1619 </pre>
1620 </div>
1622 <p>
1627 instruction.
1628 </p>
1631 <pre>
1632 SDNode *Select_ISD_STORE(const SDValue &N) {
1633 SDValue Chain = N.getOperand(0);
1634 if (Predicate_store(N.getNode())) {
1635 SDValue N1 = N.getOperand(1);
1636 SDValue N2 = N.getOperand(2);
1637 SDValue CPTmp0;
1638 SDValue CPTmp1;
1640 // Pattern: (st:void IntRegs:i32:$src,
1642 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1644 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
1647 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1648 }
1649 ...
1650 </pre>
1651 </div>
1653 </div>
1655 <!-- ======================================================================= -->
1658 </div>
1662 <p>
1663 The Legalize phase converts a DAG to use types and operations that are natively
1664 supported by the target. For natively unsupported types and operations, you need
1665 to add code to the target-specific XXXTargetLowering implementation to convert
1666 unsupported types and operations to supported ones.
1667 </p>
1669 <p>
1672 register classes are associated with them. The code for the register classes are
1675 constructor for the SparcTargetLowering class (in
1677 </p>
1680 <pre>
1681 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1682 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1683 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1684 </pre>
1685 </div>
1687 <p>
1691 native support, add a callback to the constructor for the XXXTargetLowering
1692 class, so the instruction selection process knows what to do. The TargetLowering
1694 </p>
1696 <ul>
1710 </ul>
1712 <p>
1716 to see what methods are specifically supported.
1717 </p>
1719 <p>
1720 These callbacks are used to determine that an operation does or does not work
1721 with a specified type (or types). And in all cases, the third parameter is
1725 </p>
1727 </div>
1729 <!-- _______________________________________________________________________ -->
1732 </div>
1736 <p>
1737 For an operation without native support for a given type, the specified type may
1738 be promoted to a larger type that is supported. For example, SPARC does not
1742 </p>
1745 <pre>
1746 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1747 </pre>
1748 </div>
1750 </div>
1752 <!-- _______________________________________________________________________ -->
1755 </div>
1759 <p>
1760 For a type without native support, a value may need to be broken down further,
1761 rather than promoted. For an operation without native support, a combination of
1762 other operations may be used to similar effect. In SPARC, the floating-point
1763 sine and cosine trig operations are supported by expansion to other operations,
1766 </p>
1769 <pre>
1770 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1771 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1772 </pre>
1773 </div>
1775 </div>
1777 <!-- _______________________________________________________________________ -->
1780 </div>
1784 <p>
1785 For some operations, simple type promotion or operation expansion may be
1786 insufficient. In some cases, a special intrinsic function must be implemented.
1787 </p>
1789 <p>
1790 For example, a constant value may require special treatment, or an operation may
1791 require spilling and restoring registers in the stack and working with register
1792 allocators.
1793 </p>
1795 <p>
1797 conversion from a floating point value to a signed integer, first the
1799 parameter:
1800 </p>
1803 <pre>
1804 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1805 </pre>
1806 </div>
1808 <p>
1810 case statement should be added to indicate what function to call. In the
1813 </p>
1816 <pre>
1817 SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1818 switch (Op.getOpcode()) {
1819 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1820 ...
1821 }
1822 }
1823 </pre>
1824 </div>
1826 <p>
1828 register to convert the floating-point value to an integer.
1829 </p>
1832 <pre>
1833 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1834 assert(Op.getValueType() == MVT::i32);
1835 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1836 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1837 }
1838 </pre>
1839 </div>
1841 </div>
1843 <!-- _______________________________________________________________________ -->
1846 </div>
1850 <p>
1855 natively supported only for SPARC v9. The following code enables
1857 </p>
1860 <pre>
1861 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1862 ...
1864 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1865 case ISD::SETULT: return SPCC::ICC_CS;
1866 case ISD::SETULE: return SPCC::ICC_LEU;
1867 case ISD::SETUGT: return SPCC::ICC_GU;
1868 case ISD::SETUGE: return SPCC::ICC_CC;
1869 }
1870 }
1871 </pre>
1872 </div>
1874 </div>
1876 <!-- ======================================================================= -->
1879 </div>
1883 <p>
1885 uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
1891 </p>
1893 <ul>
1896 <li>Where parameters and return values are placed (that is, on the stack or in
1897 registers).</li>
1902 </ul>
1904 <p>
1911 </p>
1914 <pre>
1916 </pre>
1917 </div>
1919 <p>
1921 return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1923 (shown below) indicates which registers are used for specified scalar return
1927 </p>
1930 <pre>
1931 def RetCC_Sparc32 : CallingConv<[
1935 ]>;
1936 </pre>
1937 </div>
1939 <p>
1942 specified size and alignment. In the example below, the first parameter, 4,
1943 indicates the size of the slot, and the second parameter, also 4, indicates the
1944 stack alignment along 4-byte units. (Special cases: if size is zero, then the
1945 ABI size is used; if alignment is zero, then the ABI alignment is used.)
1946 </p>
1949 <pre>
1950 def CC_Sparc32 : CallingConv<[
1951 // All arguments get passed in integer registers if there is space.
1954 ]>;
1955 </pre>
1956 </div>
1958 <p>
1960 specified sub-calling convention, and, if a match is found, it is invoked. In
1965 </p>
1968 <pre>
1969 def RetCC_X86_32_C : CallingConv<[
1973 ]>;
1974 </pre>
1975 </div>
1977 <p>
1979 current calling convention. If the name identifies the current calling
1980 convention, then a specified action is invoked. In the following example (in
1984 </p>
1987 <pre>
1988 def RetCC_X86_32 : CallingConv<[
1992 ]>;
1993 </pre>
1994 </div>
1998 <ul>
2000 apply the action.</li>
2009 not take a variable number of arguments, apply the action.</li>
2015 slot with the minimum specified size and alignment.</li>
2018 the specified type.</li>
2021 convention that is supported.</li>
2022 </ul>
2024 </div>
2026 <!-- *********************************************************************** -->
2029 </div>
2030 <!-- *********************************************************************** -->
2034 <p>
2035 During the code emission stage, the code generator may utilize an LLVM pass to
2036 produce assembly output. To do this, you want to implement the code for a
2037 printer that converts LLVM IR to a GAS-format assembly language for your target
2038 machine, using the following steps:
2039 </p>
2041 <ul>
2042 <li>Define all the assembly strings for your target, adding them to the
2054 methods.</li>
2057 class that performs the LLVM-to-assembly conversion.</li>
2058 </ul>
2060 <p>
2066 </p>
2069 <pre>
2070 SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
2071 Data16bitsDirective = "\t.half\t";
2072 Data32bitsDirective = "\t.word\t";
2073 Data64bitsDirective = 0; // .xword is only supported by V9.
2074 ZeroDirective = "\t.skip\t";
2075 CommentString = "!";
2077 }
2078 </pre>
2079 </div>
2081 <p>
2085 </p>
2087 <p>
2088 A target-specific implementation of AsmPrinter is written in
2090 converts the LLVM to printable assembly. The implementation must include the
2094 </p>
2097 <pre>
2098 #include "llvm/CodeGen/AsmPrinter.h"
2099 #include "llvm/CodeGen/MachineFunctionPass.h"
2100 </pre>
2101 </div>
2103 <p>
2107 variable names.
2108 </p>
2110 <p>
2116 generally do the following to process each machine function:
2117 </p>
2119 <ul>
2123 which have been spilled to memory.</li>
2126 function.</li>
2130 <li>Print out the code for the function, including basic block labels and the
2132 </ul>
2134 <p>
2139 </p>
2141 <ul>
2161 </ul>
2163 <p>
2166 generally adequate for printing assembly and do not need to be
2167 overridden.
2168 </p>
2170 <p>
2172 statement for the type of operand: register, immediate, basic block, external
2173 symbol, global address, constant pool index, or jump table index. For an
2175 should be implemented to generate the proper output. Similarly,
2177 </p>
2180 it should be called to shut down the assembly printer. During
2182 output.
2183 </p>
2185 </div>
2187 <!-- *********************************************************************** -->
2190 </div>
2191 <!-- *********************************************************************** -->
2195 <p>
2196 Subtarget support is used to inform the code generation process of instruction
2197 set variations for a given chip set. For example, the LLVM SPARC implementation
2198 provided covers three major versions of the SPARC microprocessor architecture:
2200 architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2202 quad-precision registers. V8 is also purely big-endian. V9 has 32
2203 double-precision floating-point registers that are also usable as 16
2204 quad-precision registers, but cannot be used as single-precision registers. The
2205 UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
2206 extensions.
2207 </p>
2209 <p>
2210 If subtarget support is needed, you should implement a target-specific
2211 XXXSubtarget class for your architecture. This class should process the
2213 </p>
2215 <p>
2220 attribute set by the feature, the value of the attribute, and a description of
2221 the feature. (The fifth parameter is a list of features whose presence is
2222 implied, and its default value is an empty array.)
2223 </p>
2226 <pre>
2227 class SubtargetFeature<string n, string a, string v, string d,
2229 string Name = n;
2230 string Attribute = a;
2231 string Value = v;
2232 string Desc = d;
2234 }
2235 </pre>
2236 </div>
2238 <p>
2240 following features.
2241 </p>
2244 <pre>
2252 </pre>
2253 </div>
2255 <p>
2257 define particular SPARC processor subtypes that may have the previously
2258 described features.
2259 </p>
2262 <pre>
2265
2279 </pre>
2280 </div>
2282 <p>
2284 SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2285 constants to represent the CPU features and CPU subtypes, and the
2286 ParseSubtargetFeatures method that parses the features string that sets
2289 implementation of the XXXSubtarget method should follow this pseudocode:
2290 </p>
2293 <pre>
2295 // Set the default features
2296 // Determine default and user specified characteristics of the CPU
2297 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2298 // Perform any additional operations
2299 }
2300 </pre>
2301 </div>
2303 </div>
2305 <!-- *********************************************************************** -->
2308 </div>
2309 <!-- *********************************************************************** -->
2313 <p>
2314 The implementation of a target machine optionally includes a Just-In-Time (JIT)
2315 code generator that emits machine code and auxiliary structures as binary output
2316 that can be written directly to memory. To do this, implement JIT code
2317 generation by performing the following steps:
2318 </p>
2320 <ul>
2322 pass that transforms target-machine instructions into relocatable machine
2323 code.</li>
2326 target-specific code-generation activities, such as emitting machine code
2327 and stubs.</li>
2331 </ul>
2333 <p>
2334 There are several different approaches to writing the JIT support code. For
2335 instance, TableGen and target descriptor files may be used for creating a JIT
2336 code generator, but are not mandatory. For the Alpha and PowerPC target
2338 contains the binary coding of machine instructions and the
2340 implementations do not.
2341 </p>
2343 <p>
2347 that write data (in bytes, words, strings, etc.) to the output stream.
2348 </p>
2350 </div>
2352 <!-- ======================================================================= -->
2355 </div>
2359 <p>
2361 is implemented as a function pass (subclass
2367 implemented with case statements on the instruction types defined in
2370 statements:
2371 </p>
2374 <pre>
2376 case X86II::Pseudo: // for not yet implemented instructions
2377 ... // or pseudo-instructions
2378 break;
2379 case X86II::RawFrm: // for instructions with a fixed opcode value
2380 ...
2381 break;
2382 case X86II::AddRegFrm: // for instructions that have one register operand
2383 ... // added to their opcode
2384 break;
2385 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2386 ... // to specify a destination (register)
2387 break;
2388 case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2389 ... // to specify a destination (memory)
2390 break;
2391 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2392 ... // to specify a source (register)
2393 break;
2394 case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2395 ... // to specify a source (memory)
2396 break;
2397 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2398 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2399 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2400 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2401 ...
2402 break;
2403 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2404 case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2405 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2406 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2407 ...
2408 break;
2409 case X86II::MRMInitReg: // for instructions whose source and
2410 ... // destination are the same register
2411 break;
2412 }
2413 </pre>
2414 </div>
2416 <p>
2417 The implementations of these case statements often first emit the opcode and
2418 then get the operand(s). Then depending upon the operand, helper methods may be
2430 </p>
2433 <pre>
2434 case X86II::AddRegFrm:
2435 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2437 if (CurOp != NumOps) {
2438 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2439 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2440 if (MO1.isImmediate())
2441 emitConstant(MO1.getImm(), Size);
2442 else {
2443 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2444 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2445 if (Opcode == X86::MOV64ri)
2446 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2447 if (MO1.isGlobalAddress()) {
2449 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2450 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2451 NeedStub, isLazy);
2452 } else if (MO1.isExternalSymbol())
2453 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2454 else if (MO1.isConstantPoolIndex())
2455 emitConstPoolAddress(MO1.getIndex(), rt);
2456 else if (MO1.isJumpTableIndex())
2457 emitJumpTableAddress(MO1.getIndex(), rt);
2458 }
2459 }
2460 break;
2461 </pre>
2462 </div>
2464 <p>
2467 relocate addresses (for example, a global address with a PIC base offset). The
2471 addresses for referenced global symbols.
2472 </p>
2474 <p>
2476 for the X86 addresses. In all four cases, the relocated value is added to the
2479 </p>
2482 <pre>
2483 enum RelocationType {
2484 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2485 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
2486 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2487 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2488 };
2489 </pre>
2490 </div>
2492 </div>
2494 <!-- ======================================================================= -->
2497 </div>
2501 <p>
2503 code-generation activities, such as emitting machine code and stubs. At minimum,
2505 </p>
2507 <ul>
2509 target a function that is used for compilation.</li>
2512 address for a callback function.</li>
2515 on relocation types.</li>
2517 <li>Callback function that are wrappers to a function stub that is used when the
2518 real target is not initially known.</li>
2519 </ul>
2521 <p>
2524 callback function that will be used a function wrapper. For the Alpha target
2526 implementation is simply:
2527 </p>
2530 <pre>
2531 TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2532 JITCompilerFn F) {
2533 JITCompilerFunction = F;
2534 return AlphaCompilationCallback;
2535 }
2536 </pre>
2537 </div>
2539 <p>
2541 little more complication, because it returns a different callback function for
2542 processors with SSE instructions and XMM registers.
2543 </p>
2545 <p>
2546 The callback function initially saves and later restores the callee register
2547 values, incoming arguments, and frame and return address. The callback function
2548 needs low-level access to the registers or stack, so it is typically implemented
2549 with assembler.
2550 </p>
2552 </div>
2554 <!-- *********************************************************************** -->
2556 <hr>
2557 <address>
2563 <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
2565 <br>
2566 Last modified: $Date$
2567 </address>
2569 </body>
2570 </html>