lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/CodeGen/AsmPrinter.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/GCStrategy.h"
  21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  22 #include "llvm/Target/TargetOptions.h"
  23 #include "llvm/MC/MCAsmInfo.h"
  24 #include "llvm/Target/TargetRegistry.h"
  25 #include "llvm/Transforms/Scalar.h"
  26 #include "llvm/Support/CommandLine.h"
  27 #include "llvm/Support/FormattedStream.h"
  28 using namespace llvm;
  29
  30 namespace llvm {
  31   bool EnableFastISel;
  32 }
  33
  34 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  35     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  36 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  37     cl::desc("Print LLVM IR input to isel pass"));
  38 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  39     cl::desc("Dump emitter generated instructions as assembly"));
  40 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  41     cl::desc("Dump garbage collector data"));
  42 static cl::opt<bool> HoistConstants("hoist-constants", cl::Hidden,
  43     cl::desc("Hoist constants out of loops"));
  44 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
  45     cl::desc("Verify generated machine code"),
  46     cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
  47
  48 // When this works it will be on by default.
  49 static cl::opt<bool>
  50 DisablePostRAScheduler("disable-post-RA-scheduler",
  51                        cl::desc("Disable scheduling after register allocation"),
  52                        cl::init(true));
  53
  54 // Enable or disable FastISel. Both options are needed, because
  55 // FastISel is enabled by default with -fast, and we wish to be
  56 // able to enable or disable fast-isel independently from -O0.
  57 static cl::opt<cl::boolOrDefault>
  58 EnableFastISelOption("fast-isel", cl::Hidden,
  59   cl::desc("Enable the \"fast\" instruction selector"));
  60
  61
  62 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
  63                                      const std::string &TargetTriple)
  64   : TargetMachine(T) {
  65   AsmInfo = T.createAsmInfo(TargetTriple);
  66 }
  67
  68
  69
  70 FileModel::Model
  71 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  72                                        formatted_raw_ostream &Out,
  73                                        CodeGenFileType FileType,
  74                                        CodeGenOpt::Level OptLevel) {
  75   // Add common CodeGen passes.
  76   if (addCommonCodeGenPasses(PM, OptLevel))
  77     return FileModel::Error;
  78
  79   // Fold redundant debug labels.
  80   PM.add(createDebugLabelFoldingPass());
  81
  82   if (PrintMachineCode)
  83     PM.add(createMachineFunctionPrinterPass(errs()));
  84
  85   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
  86     PM.add(createMachineFunctionPrinterPass(errs()));
  87
  88   if (OptLevel != CodeGenOpt::None)
  89     PM.add(createCodePlacementOptPass());
  90
  91   switch (FileType) {
  92   default:
  93     break;
  94   case TargetMachine::AssemblyFile:
  95     if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
  96       return FileModel::Error;
  97     return FileModel::AsmFile;
  98   case TargetMachine::ObjectFile:
  99     if (getMachOWriterInfo())
 100       return FileModel::MachOFile;
 101     else if (getELFWriterInfo())
 102       return FileModel::ElfFile;
 103   }
 104
 105   return FileModel::Error;
 106 }
 107
 108 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
 109                                            CodeGenOpt::Level OptLevel,
 110                                            bool Verbose,
 111                                            formatted_raw_ostream &Out) {
 112   FunctionPass *Printer =
 113     getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
 114   if (!Printer)
 115     return true;
 116
 117   PM.add(Printer);
 118   return false;
 119 }
 120
 121 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 122 /// be split up (e.g., to add an object writer pass), this method can be used to
 123 /// finish up adding passes to emit the file, if necessary.
 124 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 125                                                   MachineCodeEmitter *MCE,
 126                                                   CodeGenOpt::Level OptLevel) {
 127   if (MCE)
 128     addSimpleCodeEmitter(PM, OptLevel, *MCE);
 129   if (PrintEmittedAsm)
 130     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 131
 132   PM.add(createGCInfoDeleter());
 133
 134   return false; // success!
 135 }
 136
 137 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 138 /// be split up (e.g., to add an object writer pass), this method can be used to
 139 /// finish up adding passes to emit the file, if necessary.
 140 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 141                                                   JITCodeEmitter *JCE,
 142                                                   CodeGenOpt::Level OptLevel) {
 143   if (JCE)
 144     addSimpleCodeEmitter(PM, OptLevel, *JCE);
 145   if (PrintEmittedAsm)
 146     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 147
 148   PM.add(createGCInfoDeleter());
 149
 150   return false; // success!
 151 }
 152
 153 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 154 /// be split up (e.g., to add an object writer pass), this method can be used to
 155 /// finish up adding passes to emit the file, if necessary.
 156 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 157                                                   ObjectCodeEmitter *OCE,
 158                                                   CodeGenOpt::Level OptLevel) {
 159   if (OCE)
 160     addSimpleCodeEmitter(PM, OptLevel, *OCE);
 161   if (PrintEmittedAsm)
 162     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 163
 164   PM.add(createGCInfoDeleter());
 165
 166   return false; // success!
 167 }
 168
 169 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 170 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 171 /// actually outputting the machine code and resolving things like the address
 172 /// of functions.  This method should returns true if machine code emission is
 173 /// not supported.
 174 ///
 175 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 176                                                    MachineCodeEmitter &MCE,
 177                                                    CodeGenOpt::Level OptLevel) {
 178   // Add common CodeGen passes.
 179   if (addCommonCodeGenPasses(PM, OptLevel))
 180     return true;
 181
 182   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
 183     PM.add(createMachineFunctionPrinterPass(errs()));
 184
 185   addCodeEmitter(PM, OptLevel, MCE);
 186   if (PrintEmittedAsm)
 187     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 188
 189   PM.add(createGCInfoDeleter());
 190
 191   return false; // success!
 192 }
 193
 194 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 195 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 196 /// actually outputting the machine code and resolving things like the address
 197 /// of functions.  This method should returns true if machine code emission is
 198 /// not supported.
 199 ///
 200 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 201                                                    JITCodeEmitter &JCE,
 202                                                    CodeGenOpt::Level OptLevel) {
 203   // Add common CodeGen passes.
 204   if (addCommonCodeGenPasses(PM, OptLevel))
 205     return true;
 206
 207   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
 208     PM.add(createMachineFunctionPrinterPass(errs()));
 209
 210   addCodeEmitter(PM, OptLevel, JCE);
 211   if (PrintEmittedAsm)
 212     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 213
 214   PM.add(createGCInfoDeleter());
 215
 216   return false; // success!
 217 }
 218
 219 static void printAndVerify(PassManagerBase &PM,
 220                            bool allowDoubleDefs = false) {
 221   if (PrintMachineCode)
 222     PM.add(createMachineFunctionPrinterPass(errs()));
 223
 224   if (VerifyMachineCode)
 225     PM.add(createMachineVerifierPass(allowDoubleDefs));
 226 }
 227
 228 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
 229 /// emitting to assembly files or machine code output.
 230 ///
 231 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
 232                                                CodeGenOpt::Level OptLevel) {
 233   // Standard LLVM-Level Passes.
 234
 235   // Run loop strength reduction before anything else.
 236   if (OptLevel != CodeGenOpt::None) {
 237     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 238     if (PrintLSR)
 239       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
 240   }
 241
 242   // Turn exception handling constructs into something the code generators can
 243   // handle.
 244   switch (getMCAsmInfo()->getExceptionHandlingType())
 245   {
 246   case ExceptionHandling::SjLj:
 247     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
 248     PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
 249     PM.add(createSjLjEHPass(getTargetLowering()));
 250     break;
 251   case ExceptionHandling::Dwarf:
 252     PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
 253     break;
 254   case ExceptionHandling::None:
 255     PM.add(createLowerInvokePass(getTargetLowering()));
 256     break;
 257   }
 258
 259   PM.add(createGCLoweringPass());
 260
 261   // Make sure that no unreachable blocks are instruction selected.
 262   PM.add(createUnreachableBlockEliminationPass());
 263
 264   if (OptLevel != CodeGenOpt::None) {
 265     if (HoistConstants)
 266       PM.add(createCodeGenLICMPass());
 267     PM.add(createCodeGenPreparePass(getTargetLowering()));
 268   }
 269
 270   PM.add(createStackProtectorPass(getTargetLowering()));
 271
 272   if (PrintISelInput)
 273     PM.add(createPrintFunctionPass("\n\n"
 274                                    "*** Final LLVM Code input to ISel ***\n",
 275                                    &errs()));
 276
 277   // Standard Lower-Level Passes.
 278
 279   // Set up a MachineFunction for the rest of CodeGen to work on.
 280   PM.add(new MachineFunctionAnalysis(*this, OptLevel));
 281
 282   // Enable FastISel with -fast, but allow that to be overridden.
 283   if (EnableFastISelOption == cl::BOU_TRUE ||
 284       (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
 285     EnableFastISel = true;
 286
 287   // Ask the target for an isel.
 288   if (addInstSelector(PM, OptLevel))
 289     return true;
 290
 291   // Print the instruction selected machine code...
 292   printAndVerify(PM, /* allowDoubleDefs= */ true);
 293
 294   if (OptLevel != CodeGenOpt::None) {
 295     PM.add(createMachineLICMPass());
 296     PM.add(createMachineSinkingPass());
 297     printAndVerify(PM, /* allowDoubleDefs= */ true);
 298   }
 299
 300   // Run pre-ra passes.
 301   if (addPreRegAlloc(PM, OptLevel))
 302     printAndVerify(PM, /* allowDoubleDefs= */ true);
 303
 304   // Perform register allocation.
 305   PM.add(createRegisterAllocator());
 306
 307   // Perform stack slot coloring.
 308   if (OptLevel != CodeGenOpt::None)
 309     // FIXME: Re-enable coloring with register when it's capable of adding
 310     // kill markers.
 311     PM.add(createStackSlotColoringPass(false));
 312
 313   printAndVerify(PM);           // Print the register-allocated code
 314
 315   // Run post-ra passes.
 316   if (addPostRegAlloc(PM, OptLevel))
 317     printAndVerify(PM);
 318
 319   PM.add(createLowerSubregsPass());
 320   printAndVerify(PM);
 321
 322   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 323   PM.add(createPrologEpilogCodeInserter());
 324   printAndVerify(PM);
 325
 326   // Second pass scheduler.
 327   if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
 328     PM.add(createPostRAScheduler());
 329     printAndVerify(PM);
 330   }
 331
 332   // Branch folding must be run after regalloc and prolog/epilog insertion.
 333   if (OptLevel != CodeGenOpt::None) {
 334     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 335     printAndVerify(PM);
 336   }
 337
 338   PM.add(createGCMachineCodeAnalysisPass());
 339   printAndVerify(PM);
 340
 341   if (PrintGCInfo)
 342     PM.add(createGCInfoPrinter(errs()));
 343
 344   return false;
 345 }