lib/Target/ARM/ARMISelLowering.h

   1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that ARM uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef ARMISELLOWERING_H
  16 #define ARMISELLOWERING_H
  17
  18 #include "ARMSubtarget.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/CodeGen/CallingConvLower.h"
  22 #include <vector>
  23
  24 namespace llvm {
  25   class ARMConstantPoolValue;
  26
  27   namespace ARMISD {
  28     // ARM Specific DAG Nodes
  29     enum NodeType {
  30       // Start the numbering where the builtin ops and target ops leave off.
  31       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  32
  33       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
  34                     // TargetExternalSymbol, and TargetGlobalAddress.
  35       WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
  36
  37       CALL,         // Function call.
  38       CALL_PRED,    // Function call that's predicable.
  39       CALL_NOLINK,  // Function call with branch not branch-and-link.
  40       tCALL,        // Thumb function call.
  41       BRCOND,       // Conditional branch.
  42       BR_JT,        // Jumptable branch.
  43       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
  44       RET_FLAG,     // Return with a flag operand.
  45
  46       PIC_ADD,      // Add with a PC operand and a PIC label.
  47
  48       CMP,          // ARM compare instructions.
  49       CMPZ,         // ARM compare that sets only Z flag.
  50       CMPFP,        // ARM VFP compare instruction, sets FPSCR.
  51       CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
  52       FMSTAT,       // ARM fmstat instruction.
  53       CMOV,         // ARM conditional move instructions.
  54       CNEG,         // ARM conditional negate instructions.
  55
  56       FTOSI,        // FP to sint within a FP register.
  57       FTOUI,        // FP to uint within a FP register.
  58       SITOF,        // sint to FP within a FP register.
  59       UITOF,        // uint to FP within a FP register.
  60
  61       SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
  62       SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
  63       RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
  64
  65       FMRRD,        // double to two gprs.
  66       FMDRR,        // Two gprs to double.
  67
  68       EH_SJLJ_SETJMP,    // SjLj exception handling setjmp.
  69       EH_SJLJ_LONGJMP,   // SjLj exception handling longjmp.
  70
  71       THREAD_POINTER,
  72
  73       DYN_ALLOC,    // Dynamic allocation on the stack.
  74
  75       VCEQ,         // Vector compare equal.
  76       VCGE,         // Vector compare greater than or equal.
  77       VCGEU,        // Vector compare unsigned greater than or equal.
  78       VCGT,         // Vector compare greater than.
  79       VCGTU,        // Vector compare unsigned greater than.
  80       VTST,         // Vector test bits.
  81
  82       // Vector shift by immediate:
  83       VSHL,         // ...left
  84       VSHRs,        // ...right (signed)
  85       VSHRu,        // ...right (unsigned)
  86       VSHLLs,       // ...left long (signed)
  87       VSHLLu,       // ...left long (unsigned)
  88       VSHLLi,       // ...left long (with maximum shift count)
  89       VSHRN,        // ...right narrow
  90
  91       // Vector rounding shift by immediate:
  92       VRSHRs,       // ...right (signed)
  93       VRSHRu,       // ...right (unsigned)
  94       VRSHRN,       // ...right narrow
  95
  96       // Vector saturating shift by immediate:
  97       VQSHLs,       // ...left (signed)
  98       VQSHLu,       // ...left (unsigned)
  99       VQSHLsu,      // ...left (signed to unsigned)
 100       VQSHRNs,      // ...right narrow (signed)
 101       VQSHRNu,      // ...right narrow (unsigned)
 102       VQSHRNsu,     // ...right narrow (signed to unsigned)
 103
 104       // Vector saturating rounding shift by immediate:
 105       VQRSHRNs,     // ...right narrow (signed)
 106       VQRSHRNu,     // ...right narrow (unsigned)
 107       VQRSHRNsu,    // ...right narrow (signed to unsigned)
 108
 109       // Vector shift and insert:
 110       VSLI,         // ...left
 111       VSRI,         // ...right
 112
 113       // Vector get lane (VMOV scalar to ARM core register)
 114       // (These are used for 8- and 16-bit element types only.)
 115       VGETLANEu,    // zero-extend vector extract element
 116       VGETLANEs,    // sign-extend vector extract element
 117
 118       // Vector duplicate:
 119       VDUP,
 120       VDUPLANE,
 121
 122       // Vector shuffles:
 123       VEXT,         // extract
 124       VREV64,       // reverse elements within 64-bit doublewords
 125       VREV32,       // reverse elements within 32-bit words
 126       VREV16,       // reverse elements within 16-bit halfwords
 127       VZIP,         // zip (interleave)
 128       VUZP,         // unzip (deinterleave)
 129       VTRN          // transpose
 130     };
 131   }
 132
 133   /// Define some predicates that are used for node matching.
 134   namespace ARM {
 135     /// getVMOVImm - If this is a build_vector of constants which can be
 136     /// formed by using a VMOV instruction of the specified element size,
 137     /// return the constant being splatted.  The ByteSize field indicates the
 138     /// number of bytes of each element [1248].
 139     SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
 140   }
 141
 142   //===--------------------------------------------------------------------===//
 143   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
 144
 145   class ARMTargetLowering : public TargetLowering {
 146     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
 147   public:
 148     explicit ARMTargetLowering(TargetMachine &TM);
 149
 150     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
 151
 152     /// ReplaceNodeResults - Replace the results of node with an illegal result
 153     /// type with new values built out of custom code.
 154     ///
 155     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 156                                     SelectionDAG &DAG);
 157
 158     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 159
 160     virtual const char *getTargetNodeName(unsigned Opcode) const;
 161
 162     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
 163                                                   MachineBasicBlock *MBB) const;
 164
 165     /// allowsUnalignedMemoryAccesses - Returns true if the target allows
 166     /// unaligned memory accesses. of the specified type.
 167     /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
 168     virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
 169
 170     /// isLegalAddressingMode - Return true if the addressing mode represented
 171     /// by AM is legal for this target, for a load/store of the specified type.
 172     virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
 173     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 174
 175     /// getPreIndexedAddressParts - returns true by value, base pointer and
 176     /// offset pointer and addressing mode by reference if the node's address
 177     /// can be legally represented as pre-indexed load / store address.
 178     virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
 179                                            SDValue &Offset,
 180                                            ISD::MemIndexedMode &AM,
 181                                            SelectionDAG &DAG) const;
 182
 183     /// getPostIndexedAddressParts - returns true by value, base pointer and
 184     /// offset pointer and addressing mode by reference if this node can be
 185     /// combined with a load / store to form a post-indexed load / store.
 186     virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
 187                                             SDValue &Base, SDValue &Offset,
 188                                             ISD::MemIndexedMode &AM,
 189                                             SelectionDAG &DAG) const;
 190
 191     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 192                                                 const APInt &Mask,
 193                                                 APInt &KnownZero,
 194                                                 APInt &KnownOne,
 195                                                 const SelectionDAG &DAG,
 196                                                 unsigned Depth) const;
 197
 198
 199     ConstraintType getConstraintType(const std::string &Constraint) const;
 200     std::pair<unsigned, const TargetRegisterClass*>
 201       getRegForInlineAsmConstraint(const std::string &Constraint,
 202                                    EVT VT) const;
 203     std::vector<unsigned>
 204     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 205                                       EVT VT) const;
 206
 207     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 208     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 209     /// true it means one of the asm constraint of the inline asm instruction
 210     /// being processed is 'm'.
 211     virtual void LowerAsmOperandForConstraint(SDValue Op,
 212                                               char ConstraintLetter,
 213                                               bool hasMemory,
 214                                               std::vector<SDValue> &Ops,
 215                                               SelectionDAG &DAG) const;
 216
 217     virtual const ARMSubtarget* getSubtarget() {
 218       return Subtarget;
 219     }
 220
 221     /// getFunctionAlignment - Return the Log2 alignment of this function.
 222     virtual unsigned getFunctionAlignment(const Function *F) const;
 223
 224     bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
 225   private:
 226     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
 227     /// make the right decision when generating code for different targets.
 228     const ARMSubtarget *Subtarget;
 229
 230     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
 231     ///
 232     unsigned ARMPCLabelIndex;
 233
 234     void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
 235     void addDRTypeForNEON(EVT VT);
 236     void addQRTypeForNEON(EVT VT);
 237
 238     typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
 239     void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
 240                           SDValue Chain, SDValue &Arg,
 241                           RegsToPassVector &RegsToPass,
 242                           CCValAssign &VA, CCValAssign &NextVA,
 243                           SDValue &StackPtr,
 244                           SmallVector<SDValue, 8> &MemOpChains,
 245                           ISD::ArgFlagsTy Flags);
 246     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
 247                                  SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
 248
 249     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
 250     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
 251                              DebugLoc dl, SelectionDAG &DAG,
 252                              const CCValAssign &VA,
 253                              ISD::ArgFlagsTy Flags);
 254     SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
 255     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
 256     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
 257     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
 258     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
 259     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
 260                                             SelectionDAG &DAG);
 261     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
 262                                    SelectionDAG &DAG);
 263     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
 264     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
 265     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
 266     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
 267
 268     SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
 269                                       SDValue Chain,
 270                                       SDValue Dst, SDValue Src,
 271                                       SDValue Size, unsigned Align,
 272                                       bool AlwaysInline,
 273                                       const Value *DstSV, uint64_t DstSVOff,
 274                                       const Value *SrcSV, uint64_t SrcSVOff);
 275     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 276                             CallingConv::ID CallConv, bool isVarArg,
 277                             const SmallVectorImpl<ISD::InputArg> &Ins,
 278                             DebugLoc dl, SelectionDAG &DAG,
 279                             SmallVectorImpl<SDValue> &InVals);
 280
 281     virtual SDValue
 282       LowerFormalArguments(SDValue Chain,
 283                            CallingConv::ID CallConv, bool isVarArg,
 284                            const SmallVectorImpl<ISD::InputArg> &Ins,
 285                            DebugLoc dl, SelectionDAG &DAG,
 286                            SmallVectorImpl<SDValue> &InVals);
 287
 288     virtual SDValue
 289       LowerCall(SDValue Chain, SDValue Callee,
 290                 CallingConv::ID CallConv, bool isVarArg,
 291                 bool isTailCall,
 292                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 293                 const SmallVectorImpl<ISD::InputArg> &Ins,
 294                 DebugLoc dl, SelectionDAG &DAG,
 295                 SmallVectorImpl<SDValue> &InVals);
 296
 297     virtual SDValue
 298       LowerReturn(SDValue Chain,
 299                   CallingConv::ID CallConv, bool isVarArg,
 300                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 301                   DebugLoc dl, SelectionDAG &DAG);
 302   };
 303 }
 304
 305 #endif  // ARMISELLOWERING_H