lib/Target/ARM/ARMTargetMachine.h

   1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file declares the ARM specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMTARGETMACHINE_H
  15 #define ARMTARGETMACHINE_H
  16
  17 #include "llvm/Target/TargetMachine.h"
  18 #include "llvm/Target/TargetData.h"
  19 #include "ARMInstrInfo.h"
  20 #include "ARMFrameInfo.h"
  21 #include "ARMJITInfo.h"
  22 #include "ARMSubtarget.h"
  23 #include "ARMISelLowering.h"
  24 #include "Thumb1InstrInfo.h"
  25 #include "Thumb2InstrInfo.h"
  26
  27 namespace llvm {
  28
  29 class ARMBaseTargetMachine : public LLVMTargetMachine {
  30 protected:
  31   ARMSubtarget        Subtarget;
  32
  33 private:
  34   ARMFrameInfo        FrameInfo;
  35   ARMJITInfo          JITInfo;
  36   InstrItineraryData  InstrItins;
  37   Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
  38
  39 public:
  40   ARMBaseTargetMachine(const Target &T, const std::string &TT,
  41                        const std::string &FS, bool isThumb);
  42
  43   virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
  44   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
  45   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
  46   virtual const InstrItineraryData getInstrItineraryData() const {
  47     return InstrItins;
  48   }
  49
  50   // Pass Pipeline Configuration
  51   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  52   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  53   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  54   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
  55                               MachineCodeEmitter &MCE);
  56   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
  57                               JITCodeEmitter &MCE);
  58   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
  59                               ObjectCodeEmitter &OCE);
  60   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
  61                                     CodeGenOpt::Level OptLevel,
  62                                     MachineCodeEmitter &MCE);
  63   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
  64                                     CodeGenOpt::Level OptLevel,
  65                                     JITCodeEmitter &MCE);
  66   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
  67                                     CodeGenOpt::Level OptLevel,
  68                                     ObjectCodeEmitter &OCE);
  69 };
  70
  71 /// ARMTargetMachine - ARM target machine.
  72 ///
  73 class ARMTargetMachine : public ARMBaseTargetMachine {
  74   ARMInstrInfo        InstrInfo;
  75   const TargetData    DataLayout;       // Calculates type size & alignment
  76   ARMTargetLowering   TLInfo;
  77 public:
  78   ARMTargetMachine(const Target &T, const std::string &TT,
  79                    const std::string &FS);
  80
  81   virtual const ARMRegisterInfo  *getRegisterInfo() const {
  82     return &InstrInfo.getRegisterInfo();
  83   }
  84
  85   virtual       ARMTargetLowering *getTargetLowering() const {
  86     return const_cast<ARMTargetLowering*>(&TLInfo);
  87   }
  88
  89   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
  90   virtual const TargetData       *getTargetData() const { return &DataLayout; }
  91 };
  92
  93 /// ThumbTargetMachine - Thumb target machine.
  94 /// Due to the way architectures are handled, this represents both
  95 ///   Thumb-1 and Thumb-2.
  96 ///
  97 class ThumbTargetMachine : public ARMBaseTargetMachine {
  98   ARMBaseInstrInfo    *InstrInfo;   // either Thumb1InstrInfo or Thumb2InstrInfo
  99   const TargetData    DataLayout;   // Calculates type size & alignment
 100   ARMTargetLowering   TLInfo;
 101 public:
 102   ThumbTargetMachine(const Target &T, const std::string &TT,
 103                      const std::string &FS);
 104
 105   /// returns either Thumb1RegisterInfo of Thumb2RegisterInfo
 106   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
 107     return &InstrInfo->getRegisterInfo();
 108   }
 109
 110   virtual ARMTargetLowering *getTargetLowering() const {
 111     return const_cast<ARMTargetLowering*>(&TLInfo);
 112   }
 113
 114   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
 115   virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo; }
 116   virtual const TargetData       *getTargetData() const { return &DataLayout; }
 117 };
 118
 119 } // end namespace llvm
 120
 121 #endif