lib/Target/ARM/NEONPreAllocPass.cpp

   1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "neon-prealloc"
  11 #include "ARM.h"
  12 #include "ARMInstrInfo.h"
  13 #include "llvm/CodeGen/MachineInstr.h"
  14 #include "llvm/CodeGen/MachineInstrBuilder.h"
  15 #include "llvm/CodeGen/MachineFunctionPass.h"
  16 using namespace llvm;
  17
  18 namespace {
  19   class VISIBILITY_HIDDEN NEONPreAllocPass : public MachineFunctionPass {
  20     const TargetInstrInfo *TII;
  21
  22   public:
  23     static char ID;
  24     NEONPreAllocPass() : MachineFunctionPass(&ID) {}
  25
  26     virtual bool runOnMachineFunction(MachineFunction &MF);
  27
  28     virtual const char *getPassName() const {
  29       return "NEON register pre-allocation pass";
  30     }
  31
  32   private:
  33     bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
  34   };
  35
  36   char NEONPreAllocPass::ID = 0;
  37 }
  38
  39 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
  40                              unsigned &NumRegs) {
  41   switch (Opcode) {
  42   default:
  43     break;
  44
  45   case ARM::VLD2d8:
  46   case ARM::VLD2d16:
  47   case ARM::VLD2d32:
  48   case ARM::VLD2LNd8:
  49   case ARM::VLD2LNd16:
  50   case ARM::VLD2LNd32:
  51     FirstOpnd = 0;
  52     NumRegs = 2;
  53     return true;
  54
  55   case ARM::VLD3d8:
  56   case ARM::VLD3d16:
  57   case ARM::VLD3d32:
  58   case ARM::VLD3LNd8:
  59   case ARM::VLD3LNd16:
  60   case ARM::VLD3LNd32:
  61     FirstOpnd = 0;
  62     NumRegs = 3;
  63     return true;
  64
  65   case ARM::VLD4d8:
  66   case ARM::VLD4d16:
  67   case ARM::VLD4d32:
  68   case ARM::VLD4LNd8:
  69   case ARM::VLD4LNd16:
  70   case ARM::VLD4LNd32:
  71     FirstOpnd = 0;
  72     NumRegs = 4;
  73     return true;
  74
  75   case ARM::VST2d8:
  76   case ARM::VST2d16:
  77   case ARM::VST2d32:
  78   case ARM::VST2LNd8:
  79   case ARM::VST2LNd16:
  80   case ARM::VST2LNd32:
  81     FirstOpnd = 3;
  82     NumRegs = 2;
  83     return true;
  84
  85   case ARM::VST3d8:
  86   case ARM::VST3d16:
  87   case ARM::VST3d32:
  88   case ARM::VST3LNd8:
  89   case ARM::VST3LNd16:
  90   case ARM::VST3LNd32:
  91     FirstOpnd = 3;
  92     NumRegs = 3;
  93     return true;
  94
  95   case ARM::VST4d8:
  96   case ARM::VST4d16:
  97   case ARM::VST4d32:
  98   case ARM::VST4LNd8:
  99   case ARM::VST4LNd16:
 100   case ARM::VST4LNd32:
 101     FirstOpnd = 3;
 102     NumRegs = 4;
 103     return true;
 104
 105   case ARM::VTBL2:
 106     FirstOpnd = 1;
 107     NumRegs = 2;
 108     return true;
 109
 110   case ARM::VTBL3:
 111     FirstOpnd = 1;
 112     NumRegs = 3;
 113     return true;
 114
 115   case ARM::VTBL4:
 116     FirstOpnd = 1;
 117     NumRegs = 4;
 118     return true;
 119
 120   case ARM::VTBX2:
 121     FirstOpnd = 2;
 122     NumRegs = 2;
 123     return true;
 124
 125   case ARM::VTBX3:
 126     FirstOpnd = 2;
 127     NumRegs = 3;
 128     return true;
 129
 130   case ARM::VTBX4:
 131     FirstOpnd = 2;
 132     NumRegs = 4;
 133     return true;
 134   }
 135
 136   return false;
 137 }
 138
 139 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
 140   bool Modified = false;
 141
 142   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
 143   for (; MBBI != E; ++MBBI) {
 144     MachineInstr *MI = &*MBBI;
 145     unsigned FirstOpnd, NumRegs;
 146     if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs))
 147       continue;
 148
 149     MachineBasicBlock::iterator NextI = next(MBBI);
 150     for (unsigned R = 0; R < NumRegs; ++R) {
 151       MachineOperand &MO = MI->getOperand(FirstOpnd + R);
 152       assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
 153       unsigned VirtReg = MO.getReg();
 154       assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
 155              "expected a virtual register");
 156
 157       // For now, just assign a fixed set of adjacent registers.
 158       // This leaves plenty of room for future improvements.
 159       static const unsigned NEONDRegs[] = {
 160         ARM::D0, ARM::D1, ARM::D2, ARM::D3
 161       };
 162       MO.setReg(NEONDRegs[R]);
 163
 164       if (MO.isUse()) {
 165         // Insert a copy from VirtReg.
 166         AddDefaultPred(BuildMI(MBB, MBBI, MI->getDebugLoc(),
 167                                TII->get(ARM::FCPYD), MO.getReg())
 168                        .addReg(VirtReg));
 169         if (MO.isKill()) {
 170           MachineInstr *CopyMI = prior(MBBI);
 171           CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
 172         }
 173         MO.setIsKill();
 174       } else if (MO.isDef() && !MO.isDead()) {
 175         // Add a copy to VirtReg.
 176         AddDefaultPred(BuildMI(MBB, NextI, MI->getDebugLoc(),
 177                                TII->get(ARM::FCPYD), VirtReg)
 178                        .addReg(MO.getReg()));
 179       }
 180     }
 181   }
 182
 183   return Modified;
 184 }
 185
 186 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
 187   TII = MF.getTarget().getInstrInfo();
 188
 189   bool Modified = false;
 190   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
 191        ++MFI) {
 192     MachineBasicBlock &MBB = *MFI;
 193     Modified |= PreAllocNEONRegisters(MBB);
 194   }
 195
 196   return Modified;
 197 }
 198
 199 /// createNEONPreAllocPass - returns an instance of the NEON register
 200 /// pre-allocation pass.
 201 FunctionPass *llvm::createNEONPreAllocPass() {
 202   return new NEONPreAllocPass();
 203 }