1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Type profiles and SelectionDAG nodes used by CellSPU
12 //===----------------------------------------------------------------------===//
14 // Type profile for a call sequence
15 def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
17 // SPU_GenControl: Type profile for generating control words for insertions
18 def SPU_GenControl : SDTypeProfile<1, 1, []>;
19 def SPUshufmask : SDNode<"SPUISD::SHUFFLE_MASK", SPU_GenControl, []>;
21 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
22 [SDNPHasChain, SDNPOutFlag]>;
23 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
24 [SDNPHasChain, SDNPOutFlag]>;
25 //===----------------------------------------------------------------------===//
26 // Operand constraints:
27 //===----------------------------------------------------------------------===//
29 def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
30 def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
31 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
33 // Operand type constraints for vector shuffle/permute operations
34 def SDT_SPUshuffle : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
38 // Vector binary operator type constraints (needs a further constraint to
39 // ensure that operand 0 is a vector...):
41 def SPUVecBinop: SDTypeProfile<1, 2, [
42 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
45 // Trinary operators, e.g., addx, carry generate
46 def SPUIntTrinaryOp : SDTypeProfile<1, 3, [
47 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>
50 // SELECT_MASK type constraints: There are several variations for the various
51 // vector types (this avoids having to bit_convert all over the place.)
52 def SPUselmask_type: SDTypeProfile<1, 1, [
56 // SELB type constraints:
57 def SPUselb_type: SDTypeProfile<1, 3, [
58 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>;
60 // SPU Vector shift pseudo-instruction type constraints
61 def SPUvecshift_type: SDTypeProfile<1, 2, [
62 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
64 // "marker" type for i64 operators that need a shuffle mask
65 // (i.e., uses cg or bg or another instruction that needs to
66 // use shufb to get things in the right place.)
69 // Op3: Carry-generate shuffle mask
71 def SPUmarker_type : SDTypeProfile<1, 3, [
72 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> ]>;
74 //===----------------------------------------------------------------------===//
75 // Synthetic/pseudo-instructions
76 //===----------------------------------------------------------------------===//
79 def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>;
81 // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
82 // SPUISelLowering.h):
83 def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
85 // Shift left quadword by bits and bytes
86 def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>;
87 def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>;
89 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
90 def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>;
91 def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>;
92 def SPUvec_sra: SDNode<"ISD::SRA", SPUvecshift_type, []>;
94 def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>;
95 def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>;
97 // Vector rotate left, bits shifted out of the left are rotated in on the right
98 def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
99 SPUvecshift_type, []>;
101 // Vector rotate left by bytes, but the count is given in bits and the SPU
102 // internally converts it to bytes (saves an instruction to mask off lower
104 def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS",
107 // SPU form select mask for bytes, immediate
108 def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>;
110 // SPU select bits instruction
111 def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>;
113 def SDTprefslot2vec: SDTypeProfile<1, 1, []>;
114 def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>;
116 def SPU_vec_demote : SDTypeProfile<1, 1, []>;
117 def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
119 // Address high and low components, used for [r+r] type addressing
120 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
121 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
123 // PC-relative address
124 def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
126 // A-Form local store addresses
127 def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
129 // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses
130 def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>;
132 // i64 markers: supplies extra operands used to generate the i64 operator
133 // instruction sequences
134 def SPUadd64 : SDNode<"SPUISD::ADD64_MARKER", SPUmarker_type, []>;
135 def SPUsub64 : SDNode<"SPUISD::SUB64_MARKER", SPUmarker_type, []>;
136 def SPUmul64 : SDNode<"SPUISD::MUL64_MARKER", SPUmarker_type, []>;
138 //===----------------------------------------------------------------------===//
139 // Constraints: (taken from PPCInstrInfo.td)
140 //===----------------------------------------------------------------------===//
142 class RegConstraint<string C> {
143 string Constraints = C;
146 class NoEncode<string E> {
147 string DisableEncoding = E;
150 //===----------------------------------------------------------------------===//
151 // Return (flag isn't quite what it means: the operations are flagged so that
152 // instruction scheduling doesn't disassociate them.)
153 //===----------------------------------------------------------------------===//
155 def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
156 [SDNPHasChain, SDNPOptInFlag]>;