lib/Target/PowerPC/PPCInstrInfo.cpp

   1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PPCInstrInfo.h"
  15 #include "PPCInstrBuilder.h"
  16 #include "PPCMachineFunctionInfo.h"
  17 #include "PPCPredicates.h"
  18 #include "PPCGenInstrInfo.inc"
  19 #include "PPCTargetMachine.h"
  20 #include "llvm/ADT/STLExtras.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/Support/CommandLine.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24 #include "llvm/Support/raw_ostream.h"
  25 #include "llvm/MC/MCAsmInfo.h"
  26 using namespace llvm;
  27
  28 extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
  29 extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
  30
  31 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
  32   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
  33     RI(*TM.getSubtargetImpl(), *this) {}
  34
  35 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
  36                                unsigned& sourceReg,
  37                                unsigned& destReg,
  38                                unsigned& sourceSubIdx,
  39                                unsigned& destSubIdx) const {
  40   sourceSubIdx = destSubIdx = 0; // No sub-registers.
  41
  42   unsigned oc = MI.getOpcode();
  43   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
  44       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
  45     assert(MI.getNumOperands() >= 3 &&
  46            MI.getOperand(0).isReg() &&
  47            MI.getOperand(1).isReg() &&
  48            MI.getOperand(2).isReg() &&
  49            "invalid PPC OR instruction!");
  50     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
  51       sourceReg = MI.getOperand(1).getReg();
  52       destReg = MI.getOperand(0).getReg();
  53       return true;
  54     }
  55   } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
  56     assert(MI.getNumOperands() >= 3 &&
  57            MI.getOperand(0).isReg() &&
  58            MI.getOperand(2).isImm() &&
  59            "invalid PPC ADDI instruction!");
  60     if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
  61       sourceReg = MI.getOperand(1).getReg();
  62       destReg = MI.getOperand(0).getReg();
  63       return true;
  64     }
  65   } else if (oc == PPC::ORI) {             // ori r1, r2, 0
  66     assert(MI.getNumOperands() >= 3 &&
  67            MI.getOperand(0).isReg() &&
  68            MI.getOperand(1).isReg() &&
  69            MI.getOperand(2).isImm() &&
  70            "invalid PPC ORI instruction!");
  71     if (MI.getOperand(2).getImm() == 0) {
  72       sourceReg = MI.getOperand(1).getReg();
  73       destReg = MI.getOperand(0).getReg();
  74       return true;
  75     }
  76   } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
  77              oc == PPC::FMRSD) {      // fmr r1, r2
  78     assert(MI.getNumOperands() >= 2 &&
  79            MI.getOperand(0).isReg() &&
  80            MI.getOperand(1).isReg() &&
  81            "invalid PPC FMR instruction");
  82     sourceReg = MI.getOperand(1).getReg();
  83     destReg = MI.getOperand(0).getReg();
  84     return true;
  85   } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
  86     assert(MI.getNumOperands() >= 2 &&
  87            MI.getOperand(0).isReg() &&
  88            MI.getOperand(1).isReg() &&
  89            "invalid PPC MCRF instruction");
  90     sourceReg = MI.getOperand(1).getReg();
  91     destReg = MI.getOperand(0).getReg();
  92     return true;
  93   }
  94   return false;
  95 }
  96
  97 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  98                                            int &FrameIndex) const {
  99   switch (MI->getOpcode()) {
 100   default: break;
 101   case PPC::LD:
 102   case PPC::LWZ:
 103   case PPC::LFS:
 104   case PPC::LFD:
 105     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
 106         MI->getOperand(2).isFI()) {
 107       FrameIndex = MI->getOperand(2).getIndex();
 108       return MI->getOperand(0).getReg();
 109     }
 110     break;
 111   }
 112   return 0;
 113 }
 114
 115 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
 116                                           int &FrameIndex) const {
 117   switch (MI->getOpcode()) {
 118   default: break;
 119   case PPC::STD:
 120   case PPC::STW:
 121   case PPC::STFS:
 122   case PPC::STFD:
 123     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
 124         MI->getOperand(2).isFI()) {
 125       FrameIndex = MI->getOperand(2).getIndex();
 126       return MI->getOperand(0).getReg();
 127     }
 128     break;
 129   }
 130   return 0;
 131 }
 132
 133 // commuteInstruction - We can commute rlwimi instructions, but only if the
 134 // rotate amt is zero.  We also have to munge the immediates a bit.
 135 MachineInstr *
 136 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
 137   MachineFunction &MF = *MI->getParent()->getParent();
 138
 139   // Normal instructions can be commuted the obvious way.
 140   if (MI->getOpcode() != PPC::RLWIMI)
 141     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
 142
 143   // Cannot commute if it has a non-zero rotate count.
 144   if (MI->getOperand(3).getImm() != 0)
 145     return 0;
 146
 147   // If we have a zero rotate count, we have:
 148   //   M = mask(MB,ME)
 149   //   Op0 = (Op1 & ~M) | (Op2 & M)
 150   // Change this to:
 151   //   M = mask((ME+1)&31, (MB-1)&31)
 152   //   Op0 = (Op2 & ~M) | (Op1 & M)
 153
 154   // Swap op1/op2
 155   unsigned Reg0 = MI->getOperand(0).getReg();
 156   unsigned Reg1 = MI->getOperand(1).getReg();
 157   unsigned Reg2 = MI->getOperand(2).getReg();
 158   bool Reg1IsKill = MI->getOperand(1).isKill();
 159   bool Reg2IsKill = MI->getOperand(2).isKill();
 160   bool ChangeReg0 = false;
 161   // If machine instrs are no longer in two-address forms, update
 162   // destination register as well.
 163   if (Reg0 == Reg1) {
 164     // Must be two address instruction!
 165     assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
 166            "Expecting a two-address instruction!");
 167     Reg2IsKill = false;
 168     ChangeReg0 = true;
 169   }
 170
 171   // Masks.
 172   unsigned MB = MI->getOperand(4).getImm();
 173   unsigned ME = MI->getOperand(5).getImm();
 174
 175   if (NewMI) {
 176     // Create a new instruction.
 177     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
 178     bool Reg0IsDead = MI->getOperand(0).isDead();
 179     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
 180       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
 181       .addReg(Reg2, getKillRegState(Reg2IsKill))
 182       .addReg(Reg1, getKillRegState(Reg1IsKill))
 183       .addImm((ME+1) & 31)
 184       .addImm((MB-1) & 31);
 185   }
 186
 187   if (ChangeReg0)
 188     MI->getOperand(0).setReg(Reg2);
 189   MI->getOperand(2).setReg(Reg1);
 190   MI->getOperand(1).setReg(Reg2);
 191   MI->getOperand(2).setIsKill(Reg1IsKill);
 192   MI->getOperand(1).setIsKill(Reg2IsKill);
 193
 194   // Swap the mask around.
 195   MI->getOperand(4).setImm((ME+1) & 31);
 196   MI->getOperand(5).setImm((MB-1) & 31);
 197   return MI;
 198 }
 199
 200 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
 201                               MachineBasicBlock::iterator MI) const {
 202   DebugLoc DL = DebugLoc::getUnknownLoc();
 203   if (MI != MBB.end()) DL = MI->getDebugLoc();
 204
 205   BuildMI(MBB, MI, DL, get(PPC::NOP));
 206 }
 207
 208
 209 // Branch analysis.
 210 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 211                                  MachineBasicBlock *&FBB,
 212                                  SmallVectorImpl<MachineOperand> &Cond,
 213                                  bool AllowModify) const {
 214   // If the block has no terminators, it just falls into the block after it.
 215   MachineBasicBlock::iterator I = MBB.end();
 216   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 217     return false;
 218
 219   // Get the last instruction in the block.
 220   MachineInstr *LastInst = I;
 221
 222   // If there is only one terminator instruction, process it.
 223   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 224     if (LastInst->getOpcode() == PPC::B) {
 225       if (!LastInst->getOperand(0).isMBB())
 226         return true;
 227       TBB = LastInst->getOperand(0).getMBB();
 228       return false;
 229     } else if (LastInst->getOpcode() == PPC::BCC) {
 230       if (!LastInst->getOperand(2).isMBB())
 231         return true;
 232       // Block ends with fall-through condbranch.
 233       TBB = LastInst->getOperand(2).getMBB();
 234       Cond.push_back(LastInst->getOperand(0));
 235       Cond.push_back(LastInst->getOperand(1));
 236       return false;
 237     }
 238     // Otherwise, don't know what this is.
 239     return true;
 240   }
 241
 242   // Get the instruction before it if it's a terminator.
 243   MachineInstr *SecondLastInst = I;
 244
 245   // If there are three terminators, we don't know what sort of block this is.
 246   if (SecondLastInst && I != MBB.begin() &&
 247       isUnpredicatedTerminator(--I))
 248     return true;
 249
 250   // If the block ends with PPC::B and PPC:BCC, handle it.
 251   if (SecondLastInst->getOpcode() == PPC::BCC &&
 252       LastInst->getOpcode() == PPC::B) {
 253     if (!SecondLastInst->getOperand(2).isMBB() ||
 254         !LastInst->getOperand(0).isMBB())
 255       return true;
 256     TBB =  SecondLastInst->getOperand(2).getMBB();
 257     Cond.push_back(SecondLastInst->getOperand(0));
 258     Cond.push_back(SecondLastInst->getOperand(1));
 259     FBB = LastInst->getOperand(0).getMBB();
 260     return false;
 261   }
 262
 263   // If the block ends with two PPC:Bs, handle it.  The second one is not
 264   // executed, so remove it.
 265   if (SecondLastInst->getOpcode() == PPC::B &&
 266       LastInst->getOpcode() == PPC::B) {
 267     if (!SecondLastInst->getOperand(0).isMBB())
 268       return true;
 269     TBB = SecondLastInst->getOperand(0).getMBB();
 270     I = LastInst;
 271     if (AllowModify)
 272       I->eraseFromParent();
 273     return false;
 274   }
 275
 276   // Otherwise, can't handle this.
 277   return true;
 278 }
 279
 280 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 281   MachineBasicBlock::iterator I = MBB.end();
 282   if (I == MBB.begin()) return 0;
 283   --I;
 284   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
 285     return 0;
 286
 287   // Remove the branch.
 288   I->eraseFromParent();
 289
 290   I = MBB.end();
 291
 292   if (I == MBB.begin()) return 1;
 293   --I;
 294   if (I->getOpcode() != PPC::BCC)
 295     return 1;
 296
 297   // Remove the branch.
 298   I->eraseFromParent();
 299   return 2;
 300 }
 301
 302 unsigned
 303 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 304                            MachineBasicBlock *FBB,
 305                            const SmallVectorImpl<MachineOperand> &Cond) const {
 306   // FIXME this should probably have a DebugLoc argument
 307   DebugLoc dl = DebugLoc::getUnknownLoc();
 308   // Shouldn't be a fall through.
 309   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 310   assert((Cond.size() == 2 || Cond.size() == 0) &&
 311          "PPC branch conditions have two components!");
 312
 313   // One-way branch.
 314   if (FBB == 0) {
 315     if (Cond.empty())   // Unconditional branch
 316       BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
 317     else                // Conditional branch
 318       BuildMI(&MBB, dl, get(PPC::BCC))
 319         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 320     return 1;
 321   }
 322
 323   // Two-way Conditional Branch.
 324   BuildMI(&MBB, dl, get(PPC::BCC))
 325     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 326   BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
 327   return 2;
 328 }
 329
 330 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 331                                    MachineBasicBlock::iterator MI,
 332                                    unsigned DestReg, unsigned SrcReg,
 333                                    const TargetRegisterClass *DestRC,
 334                                    const TargetRegisterClass *SrcRC) const {
 335   if (DestRC != SrcRC) {
 336     // Not yet supported!
 337     return false;
 338   }
 339
 340   DebugLoc DL = DebugLoc::getUnknownLoc();
 341   if (MI != MBB.end()) DL = MI->getDebugLoc();
 342
 343   if (DestRC == PPC::GPRCRegisterClass) {
 344     BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
 345   } else if (DestRC == PPC::G8RCRegisterClass) {
 346     BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
 347   } else if (DestRC == PPC::F4RCRegisterClass) {
 348     BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
 349   } else if (DestRC == PPC::F8RCRegisterClass) {
 350     BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
 351   } else if (DestRC == PPC::CRRCRegisterClass) {
 352     BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
 353   } else if (DestRC == PPC::VRRCRegisterClass) {
 354     BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
 355   } else if (DestRC == PPC::CRBITRCRegisterClass) {
 356     BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
 357   } else {
 358     // Attempt to copy register that is not GPR or FPR
 359     return false;
 360   }
 361
 362   return true;
 363 }
 364
 365 bool
 366 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
 367                                   unsigned SrcReg, bool isKill,
 368                                   int FrameIdx,
 369                                   const TargetRegisterClass *RC,
 370                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
 371   DebugLoc DL = DebugLoc::getUnknownLoc();
 372   if (RC == PPC::GPRCRegisterClass) {
 373     if (SrcReg != PPC::LR) {
 374       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
 375                                          .addReg(SrcReg,
 376                                                  getKillRegState(isKill)),
 377                                          FrameIdx));
 378     } else {
 379       // FIXME: this spills LR immediately to memory in one step.  To do this,
 380       // we use R11, which we know cannot be used in the prolog/epilog.  This is
 381       // a hack.
 382       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
 383       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
 384                                          .addReg(PPC::R11,
 385                                                  getKillRegState(isKill)),
 386                                          FrameIdx));
 387     }
 388   } else if (RC == PPC::G8RCRegisterClass) {
 389     if (SrcReg != PPC::LR8) {
 390       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
 391                                          .addReg(SrcReg,
 392                                                  getKillRegState(isKill)),
 393                                          FrameIdx));
 394     } else {
 395       // FIXME: this spills LR immediately to memory in one step.  To do this,
 396       // we use R11, which we know cannot be used in the prolog/epilog.  This is
 397       // a hack.
 398       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
 399       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
 400                                          .addReg(PPC::X11,
 401                                                  getKillRegState(isKill)),
 402                                          FrameIdx));
 403     }
 404   } else if (RC == PPC::F8RCRegisterClass) {
 405     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
 406                                        .addReg(SrcReg,
 407                                                getKillRegState(isKill)),
 408                                        FrameIdx));
 409   } else if (RC == PPC::F4RCRegisterClass) {
 410     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
 411                                        .addReg(SrcReg,
 412                                                getKillRegState(isKill)),
 413                                        FrameIdx));
 414   } else if (RC == PPC::CRRCRegisterClass) {
 415     if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
 416         (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
 417       // FIXME (64-bit): Enable
 418       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
 419                                          .addReg(SrcReg,
 420                                                  getKillRegState(isKill)),
 421                                          FrameIdx));
 422       return true;
 423     } else {
 424       // FIXME: We use R0 here, because it isn't available for RA.  We need to
 425       // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
 426       // to save all of the CRBits.
 427       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
 428
 429       // If the saved register wasn't CR0, shift the bits left so that they are
 430       // in CR0's slot.
 431       if (SrcReg != PPC::CR0) {
 432         unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
 433         // rlwinm r0, r0, ShiftBits, 0, 31.
 434         NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
 435                        .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
 436       }
 437
 438       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
 439                                          .addReg(PPC::R0,
 440                                                  getKillRegState(isKill)),
 441                                          FrameIdx));
 442     }
 443   } else if (RC == PPC::CRBITRCRegisterClass) {
 444     // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
 445     // backend currently only uses CR1EQ as an individual bit, this should
 446     // not cause any bug. If we need other uses of CR bits, the following
 447     // code may be invalid.
 448     unsigned Reg = 0;
 449     if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
 450         SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
 451       Reg = PPC::CR0;
 452     else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
 453              SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
 454       Reg = PPC::CR1;
 455     else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
 456              SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
 457       Reg = PPC::CR2;
 458     else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
 459              SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
 460       Reg = PPC::CR3;
 461     else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
 462              SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
 463       Reg = PPC::CR4;
 464     else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
 465              SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
 466       Reg = PPC::CR5;
 467     else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
 468              SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
 469       Reg = PPC::CR6;
 470     else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
 471              SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
 472       Reg = PPC::CR7;
 473
 474     return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
 475                                PPC::CRRCRegisterClass, NewMIs);
 476
 477   } else if (RC == PPC::VRRCRegisterClass) {
 478     // We don't have indexed addressing for vector loads.  Emit:
 479     // R0 = ADDI FI#
 480     // STVX VAL, 0, R0
 481     //
 482     // FIXME: We use R0 here, because it isn't available for RA.
 483     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
 484                                        FrameIdx, 0, 0));
 485     NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
 486                      .addReg(SrcReg, getKillRegState(isKill))
 487                      .addReg(PPC::R0)
 488                      .addReg(PPC::R0));
 489   } else {
 490     llvm_unreachable("Unknown regclass!");
 491   }
 492
 493   return false;
 494 }
 495
 496 void
 497 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 498                                   MachineBasicBlock::iterator MI,
 499                                   unsigned SrcReg, bool isKill, int FrameIdx,
 500                                   const TargetRegisterClass *RC) const {
 501   MachineFunction &MF = *MBB.getParent();
 502   SmallVector<MachineInstr*, 4> NewMIs;
 503
 504   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
 505     PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
 506     FuncInfo->setSpillsCR();
 507   }
 508
 509   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
 510     MBB.insert(MI, NewMIs[i]);
 511 }
 512
 513 void
 514 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
 515                                    unsigned DestReg, int FrameIdx,
 516                                    const TargetRegisterClass *RC,
 517                                    SmallVectorImpl<MachineInstr*> &NewMIs)const{
 518   if (RC == PPC::GPRCRegisterClass) {
 519     if (DestReg != PPC::LR) {
 520       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
 521                                                  DestReg), FrameIdx));
 522     } else {
 523       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
 524                                                  PPC::R11), FrameIdx));
 525       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
 526     }
 527   } else if (RC == PPC::G8RCRegisterClass) {
 528     if (DestReg != PPC::LR8) {
 529       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
 530                                          FrameIdx));
 531     } else {
 532       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
 533                                                  PPC::R11), FrameIdx));
 534       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
 535     }
 536   } else if (RC == PPC::F8RCRegisterClass) {
 537     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
 538                                        FrameIdx));
 539   } else if (RC == PPC::F4RCRegisterClass) {
 540     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
 541                                        FrameIdx));
 542   } else if (RC == PPC::CRRCRegisterClass) {
 543     // FIXME: We use R0 here, because it isn't available for RA.
 544     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
 545                                        FrameIdx));
 546
 547     // If the reloaded register isn't CR0, shift the bits right so that they are
 548     // in the right CR's slot.
 549     if (DestReg != PPC::CR0) {
 550       unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
 551       // rlwinm r11, r11, 32-ShiftBits, 0, 31.
 552       NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
 553                     .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
 554     }
 555
 556     NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
 557   } else if (RC == PPC::CRBITRCRegisterClass) {
 558
 559     unsigned Reg = 0;
 560     if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
 561         DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
 562       Reg = PPC::CR0;
 563     else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
 564              DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
 565       Reg = PPC::CR1;
 566     else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
 567              DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
 568       Reg = PPC::CR2;
 569     else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
 570              DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
 571       Reg = PPC::CR3;
 572     else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
 573              DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
 574       Reg = PPC::CR4;
 575     else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
 576              DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
 577       Reg = PPC::CR5;
 578     else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
 579              DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
 580       Reg = PPC::CR6;
 581     else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
 582              DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
 583       Reg = PPC::CR7;
 584
 585     return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
 586                                 PPC::CRRCRegisterClass, NewMIs);
 587
 588   } else if (RC == PPC::VRRCRegisterClass) {
 589     // We don't have indexed addressing for vector loads.  Emit:
 590     // R0 = ADDI FI#
 591     // Dest = LVX 0, R0
 592     //
 593     // FIXME: We use R0 here, because it isn't available for RA.
 594     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
 595                                        FrameIdx, 0, 0));
 596     NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
 597                      .addReg(PPC::R0));
 598   } else {
 599     llvm_unreachable("Unknown regclass!");
 600   }
 601 }
 602
 603 void
 604 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 605                                    MachineBasicBlock::iterator MI,
 606                                    unsigned DestReg, int FrameIdx,
 607                                    const TargetRegisterClass *RC) const {
 608   MachineFunction &MF = *MBB.getParent();
 609   SmallVector<MachineInstr*, 4> NewMIs;
 610   DebugLoc DL = DebugLoc::getUnknownLoc();
 611   if (MI != MBB.end()) DL = MI->getDebugLoc();
 612   LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
 613   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
 614     MBB.insert(MI, NewMIs[i]);
 615 }
 616
 617 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
 618 /// copy instructions, turning them into load/store instructions.
 619 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 620                                                   MachineInstr *MI,
 621                                            const SmallVectorImpl<unsigned> &Ops,
 622                                                   int FrameIndex) const {
 623   if (Ops.size() != 1) return NULL;
 624
 625   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
 626   // it takes more than one instruction to store it.
 627   unsigned Opc = MI->getOpcode();
 628   unsigned OpNum = Ops[0];
 629
 630   MachineInstr *NewMI = NULL;
 631   if ((Opc == PPC::OR &&
 632        MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
 633     if (OpNum == 0) {  // move -> store
 634       unsigned InReg = MI->getOperand(1).getReg();
 635       bool isKill = MI->getOperand(1).isKill();
 636       bool isUndef = MI->getOperand(1).isUndef();
 637       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
 638                                 .addReg(InReg,
 639                                         getKillRegState(isKill) |
 640                                         getUndefRegState(isUndef)),
 641                                 FrameIndex);
 642     } else {           // move -> load
 643       unsigned OutReg = MI->getOperand(0).getReg();
 644       bool isDead = MI->getOperand(0).isDead();
 645       bool isUndef = MI->getOperand(0).isUndef();
 646       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
 647                                 .addReg(OutReg,
 648                                         RegState::Define |
 649                                         getDeadRegState(isDead) |
 650                                         getUndefRegState(isUndef)),
 651                                 FrameIndex);
 652     }
 653   } else if ((Opc == PPC::OR8 &&
 654               MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
 655     if (OpNum == 0) {  // move -> store
 656       unsigned InReg = MI->getOperand(1).getReg();
 657       bool isKill = MI->getOperand(1).isKill();
 658       bool isUndef = MI->getOperand(1).isUndef();
 659       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
 660                                 .addReg(InReg,
 661                                         getKillRegState(isKill) |
 662                                         getUndefRegState(isUndef)),
 663                                 FrameIndex);
 664     } else {           // move -> load
 665       unsigned OutReg = MI->getOperand(0).getReg();
 666       bool isDead = MI->getOperand(0).isDead();
 667       bool isUndef = MI->getOperand(0).isUndef();
 668       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
 669                                 .addReg(OutReg,
 670                                         RegState::Define |
 671                                         getDeadRegState(isDead) |
 672                                         getUndefRegState(isUndef)),
 673                                 FrameIndex);
 674     }
 675   } else if (Opc == PPC::FMRD) {
 676     if (OpNum == 0) {  // move -> store
 677       unsigned InReg = MI->getOperand(1).getReg();
 678       bool isKill = MI->getOperand(1).isKill();
 679       bool isUndef = MI->getOperand(1).isUndef();
 680       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
 681                                 .addReg(InReg,
 682                                         getKillRegState(isKill) |
 683                                         getUndefRegState(isUndef)),
 684                                 FrameIndex);
 685     } else {           // move -> load
 686       unsigned OutReg = MI->getOperand(0).getReg();
 687       bool isDead = MI->getOperand(0).isDead();
 688       bool isUndef = MI->getOperand(0).isUndef();
 689       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
 690                                 .addReg(OutReg,
 691                                         RegState::Define |
 692                                         getDeadRegState(isDead) |
 693                                         getUndefRegState(isUndef)),
 694                                 FrameIndex);
 695     }
 696   } else if (Opc == PPC::FMRS) {
 697     if (OpNum == 0) {  // move -> store
 698       unsigned InReg = MI->getOperand(1).getReg();
 699       bool isKill = MI->getOperand(1).isKill();
 700       bool isUndef = MI->getOperand(1).isUndef();
 701       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
 702                                 .addReg(InReg,
 703                                         getKillRegState(isKill) |
 704                                         getUndefRegState(isUndef)),
 705                                 FrameIndex);
 706     } else {           // move -> load
 707       unsigned OutReg = MI->getOperand(0).getReg();
 708       bool isDead = MI->getOperand(0).isDead();
 709       bool isUndef = MI->getOperand(0).isUndef();
 710       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
 711                                 .addReg(OutReg,
 712                                         RegState::Define |
 713                                         getDeadRegState(isDead) |
 714                                         getUndefRegState(isUndef)),
 715                                 FrameIndex);
 716     }
 717   }
 718
 719   return NewMI;
 720 }
 721
 722 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
 723                                   const SmallVectorImpl<unsigned> &Ops) const {
 724   if (Ops.size() != 1) return false;
 725
 726   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
 727   // it takes more than one instruction to store it.
 728   unsigned Opc = MI->getOpcode();
 729
 730   if ((Opc == PPC::OR &&
 731        MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
 732     return true;
 733   else if ((Opc == PPC::OR8 &&
 734               MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
 735     return true;
 736   else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
 737     return true;
 738
 739   return false;
 740 }
 741
 742
 743 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 744   if (MBB.empty()) return false;
 745
 746   switch (MBB.back().getOpcode()) {
 747   case PPC::BLR:   // Return.
 748   case PPC::B:     // Uncond branch.
 749   case PPC::BCTR:  // Indirect branch.
 750     return true;
 751   default: return false;
 752   }
 753 }
 754
 755 bool PPCInstrInfo::
 756 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 757   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
 758   // Leave the CR# the same, but invert the condition.
 759   Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
 760   return false;
 761 }
 762
 763 /// GetInstSize - Return the number of bytes of code the specified
 764 /// instruction may be.  This returns the maximum number of bytes.
 765 ///
 766 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
 767   switch (MI->getOpcode()) {
 768   case PPC::INLINEASM: {       // Inline Asm: Variable size.
 769     const MachineFunction *MF = MI->getParent()->getParent();
 770     const char *AsmStr = MI->getOperand(0).getSymbolName();
 771     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
 772   }
 773   case PPC::DBG_LABEL:
 774   case PPC::EH_LABEL:
 775   case PPC::GC_LABEL:
 776     return 0;
 777   default:
 778     return 4; // PowerPC instructions are all 4 bytes
 779   }
 780 }