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pass machinemoduleinfo down into getSymbolForDwarfGlobalReference,
[llvm/avr.git] / lib / Target / X86 / X86FloatingPoint.cpp
blobd9a05a83b9e56e1f595cecba3a4a79fb2a7ed1d8
1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
13 // lifetimes.
14 //
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
20 //
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
25 //
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
27 // basic blocks.
28 //
29 //===----------------------------------------------------------------------===//
30
31 #define DEBUG_TYPE "x86-codegen"
32 #include "X86.h"
33 #include "X86InstrInfo.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/CodeGen/MachineFunctionPass.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/Passes.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include <algorithm>
50 using namespace llvm;
51
52 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
53 STATISTIC(NumFP , "Number of floating point instructions");
54
55 namespace {
56 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
57 static char ID;
58 FPS() : MachineFunctionPass(&ID) {}
59
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.setPreservesCFG();
62 AU.addPreservedID(MachineLoopInfoID);
63 AU.addPreservedID(MachineDominatorsID);
64 MachineFunctionPass::getAnalysisUsage(AU);
65 }
66
67 virtual bool runOnMachineFunction(MachineFunction &MF);
68
69 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
70
71 private:
72 const TargetInstrInfo *TII; // Machine instruction info.
73 MachineBasicBlock *MBB; // Current basic block
74 unsigned Stack[8]; // FP<n> Registers in each stack slot...
75 unsigned RegMap[8]; // Track which stack slot contains each register
76 unsigned StackTop; // The current top of the FP stack.
77
78 void dumpStack() const {
79 errs() << "Stack contents:";
80 for (unsigned i = 0; i != StackTop; ++i) {
81 errs() << " FP" << Stack[i];
82 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
83 }
84 errs() << "\n";
85 }
86 private:
87 /// isStackEmpty - Return true if the FP stack is empty.
88 bool isStackEmpty() const {
89 return StackTop == 0;
90 }
91
92 // getSlot - Return the stack slot number a particular register number is
93 // in.
94 unsigned getSlot(unsigned RegNo) const {
95 assert(RegNo < 8 && "Regno out of range!");
96 return RegMap[RegNo];
97 }
98
99 // getStackEntry - Return the X86::FP<n> register in register ST(i).
100 unsigned getStackEntry(unsigned STi) const {
101 assert(STi < StackTop && "Access past stack top!");
102 return Stack[StackTop-1-STi];
103 }
104
105 // getSTReg - Return the X86::ST(i) register which contains the specified
106 // FP<RegNo> register.
107 unsigned getSTReg(unsigned RegNo) const {
108 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
109 }
110
111 // pushReg - Push the specified FP<n> register onto the stack.
112 void pushReg(unsigned Reg) {
113 assert(Reg < 8 && "Register number out of range!");
114 assert(StackTop < 8 && "Stack overflow!");
115 Stack[StackTop] = Reg;
116 RegMap[Reg] = StackTop++;
117 }
118
119 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
120 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
121 MachineInstr *MI = I;
122 DebugLoc dl = MI->getDebugLoc();
123 if (isAtTop(RegNo)) return;
124
125 unsigned STReg = getSTReg(RegNo);
126 unsigned RegOnTop = getStackEntry(0);
127
128 // Swap the slots the regs are in.
129 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
130
131 // Swap stack slot contents.
132 assert(RegMap[RegOnTop] < StackTop);
133 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
134
135 // Emit an fxch to update the runtime processors version of the state.
136 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
137 NumFXCH++;
138 }
139
140 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
141 DebugLoc dl = I->getDebugLoc();
142 unsigned STReg = getSTReg(RegNo);
143 pushReg(AsReg); // New register on top of stack
144
145 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
146 }
147
148 // popStackAfter - Pop the current value off of the top of the FP stack
149 // after the specified instruction.
150 void popStackAfter(MachineBasicBlock::iterator &I);
151
152 // freeStackSlotAfter - Free the specified register from the register stack,
153 // so that it is no longer in a register. If the register is currently at
154 // the top of the stack, we just pop the current instruction, otherwise we
155 // store the current top-of-stack into the specified slot, then pop the top
156 // of stack.
157 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
158
159 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
160
161 void handleZeroArgFP(MachineBasicBlock::iterator &I);
162 void handleOneArgFP(MachineBasicBlock::iterator &I);
163 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
164 void handleTwoArgFP(MachineBasicBlock::iterator &I);
165 void handleCompareFP(MachineBasicBlock::iterator &I);
166 void handleCondMovFP(MachineBasicBlock::iterator &I);
167 void handleSpecialFP(MachineBasicBlock::iterator &I);
168 };
169 char FPS::ID = 0;
170 }
171
172 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
173
174 /// getFPReg - Return the X86::FPx register number for the specified operand.
175 /// For example, this returns 3 for X86::FP3.
176 static unsigned getFPReg(const MachineOperand &MO) {
177 assert(MO.isReg() && "Expected an FP register!");
178 unsigned Reg = MO.getReg();
179 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
180 return Reg - X86::FP0;
181 }
182
183
184 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
185 /// register references into FP stack references.
186 ///
187 bool FPS::runOnMachineFunction(MachineFunction &MF) {
188 // We only need to run this pass if there are any FP registers used in this
189 // function. If it is all integer, there is nothing for us to do!
190 bool FPIsUsed = false;
191
192 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
193 for (unsigned i = 0; i <= 6; ++i)
194 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
195 FPIsUsed = true;
196 break;
197 }
198
199 // Early exit.
200 if (!FPIsUsed) return false;
201
202 TII = MF.getTarget().getInstrInfo();
203 StackTop = 0;
204
205 // Process the function in depth first order so that we process at least one
206 // of the predecessors for every reachable block in the function.
207 SmallPtrSet<MachineBasicBlock*, 8> Processed;
208 MachineBasicBlock *Entry = MF.begin();
209
210 bool Changed = false;
211 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
212 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
213 I != E; ++I)
214 Changed |= processBasicBlock(MF, **I);
215
216 // Process any unreachable blocks in arbitrary order now.
217 if (MF.size() == Processed.size())
218 return Changed;
219
220 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
221 if (Processed.insert(BB))
222 Changed |= processBasicBlock(MF, *BB);
223
224 return Changed;
225 }
226
227 /// processBasicBlock - Loop over all of the instructions in the basic block,
228 /// transforming FP instructions into their stack form.
229 ///
230 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
231 bool Changed = false;
232 MBB = &BB;
233
234 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
235 MachineInstr *MI = I;
236 unsigned Flags = MI->getDesc().TSFlags;
237
238 unsigned FPInstClass = Flags & X86II::FPTypeMask;
239 if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
240 FPInstClass = X86II::SpecialFP;
241
242 if (FPInstClass == X86II::NotFP)
243 continue; // Efficiently ignore non-fp insts!
244
245 MachineInstr *PrevMI = 0;
246 if (I != BB.begin())
247 PrevMI = prior(I);
248
249 ++NumFP; // Keep track of # of pseudo instrs
250 DEBUG(errs() << "\nFPInst:\t" << *MI);
251
252 // Get dead variables list now because the MI pointer may be deleted as part
253 // of processing!
254 SmallVector<unsigned, 8> DeadRegs;
255 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
256 const MachineOperand &MO = MI->getOperand(i);
257 if (MO.isReg() && MO.isDead())
258 DeadRegs.push_back(MO.getReg());
259 }
260
261 switch (FPInstClass) {
262 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
263 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
264 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
265 case X86II::TwoArgFP: handleTwoArgFP(I); break;
266 case X86II::CompareFP: handleCompareFP(I); break;
267 case X86II::CondMovFP: handleCondMovFP(I); break;
268 case X86II::SpecialFP: handleSpecialFP(I); break;
269 default: llvm_unreachable("Unknown FP Type!");
270 }
271
272 // Check to see if any of the values defined by this instruction are dead
273 // after definition. If so, pop them.
274 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
275 unsigned Reg = DeadRegs[i];
276 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
277 DEBUG(errs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
278 freeStackSlotAfter(I, Reg-X86::FP0);
279 }
280 }
281
282 // Print out all of the instructions expanded to if -debug
283 DEBUG(
284 MachineBasicBlock::iterator PrevI(PrevMI);
285 if (I == PrevI) {
286 errs() << "Just deleted pseudo instruction\n";
287 } else {
288 MachineBasicBlock::iterator Start = I;
289 // Rewind to first instruction newly inserted.
290 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
291 errs() << "Inserted instructions:\n\t";
292 Start->print(errs(), &MF.getTarget());
293 while (++Start != next(I)) {}
294 }
295 dumpStack();
296 );
297
298 Changed = true;
299 }
300
301 assert(isStackEmpty() && "Stack not empty at end of basic block?");
302 return Changed;
303 }
304
305 //===----------------------------------------------------------------------===//
306 // Efficient Lookup Table Support
307 //===----------------------------------------------------------------------===//
308
309 namespace {
310 struct TableEntry {
311 unsigned from;
312 unsigned to;
313 bool operator<(const TableEntry &TE) const { return from < TE.from; }
314 friend bool operator<(const TableEntry &TE, unsigned V) {
315 return TE.from < V;
316 }
317 friend bool operator<(unsigned V, const TableEntry &TE) {
318 return V < TE.from;
319 }
320 };
321 }
322
323 #ifndef NDEBUG
324 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
325 for (unsigned i = 0; i != NumEntries-1; ++i)
326 if (!(Table[i] < Table[i+1])) return false;
327 return true;
328 }
329 #endif
330
331 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
332 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
333 if (I != Table+N && I->from == Opcode)
334 return I->to;
335 return -1;
336 }
337
338 #ifdef NDEBUG
339 #define ASSERT_SORTED(TABLE)
340 #else
341 #define ASSERT_SORTED(TABLE) \
342 { static bool TABLE##Checked = false; \
343 if (!TABLE##Checked) { \
344 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
345 "All lookup tables must be sorted for efficient access!"); \
346 TABLE##Checked = true; \
347 } \
348 }
349 #endif
350
351 //===----------------------------------------------------------------------===//
352 // Register File -> Register Stack Mapping Methods
353 //===----------------------------------------------------------------------===//
354
355 // OpcodeTable - Sorted map of register instructions to their stack version.
356 // The first element is an register file pseudo instruction, the second is the
357 // concrete X86 instruction which uses the register stack.
358 //
359 static const TableEntry OpcodeTable[] = {
360 { X86::ABS_Fp32 , X86::ABS_F },
361 { X86::ABS_Fp64 , X86::ABS_F },
362 { X86::ABS_Fp80 , X86::ABS_F },
363 { X86::ADD_Fp32m , X86::ADD_F32m },
364 { X86::ADD_Fp64m , X86::ADD_F64m },
365 { X86::ADD_Fp64m32 , X86::ADD_F32m },
366 { X86::ADD_Fp80m32 , X86::ADD_F32m },
367 { X86::ADD_Fp80m64 , X86::ADD_F64m },
368 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
369 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
370 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
371 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
372 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
373 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
374 { X86::CHS_Fp32 , X86::CHS_F },
375 { X86::CHS_Fp64 , X86::CHS_F },
376 { X86::CHS_Fp80 , X86::CHS_F },
377 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
378 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
379 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
380 { X86::CMOVB_Fp32 , X86::CMOVB_F },
381 { X86::CMOVB_Fp64 , X86::CMOVB_F },
382 { X86::CMOVB_Fp80 , X86::CMOVB_F },
383 { X86::CMOVE_Fp32 , X86::CMOVE_F },
384 { X86::CMOVE_Fp64 , X86::CMOVE_F },
385 { X86::CMOVE_Fp80 , X86::CMOVE_F },
386 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
387 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
388 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
389 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
390 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
391 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
392 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
393 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
394 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
395 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
396 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
397 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
398 { X86::CMOVP_Fp32 , X86::CMOVP_F },
399 { X86::CMOVP_Fp64 , X86::CMOVP_F },
400 { X86::CMOVP_Fp80 , X86::CMOVP_F },
401 { X86::COS_Fp32 , X86::COS_F },
402 { X86::COS_Fp64 , X86::COS_F },
403 { X86::COS_Fp80 , X86::COS_F },
404 { X86::DIVR_Fp32m , X86::DIVR_F32m },
405 { X86::DIVR_Fp64m , X86::DIVR_F64m },
406 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
407 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
408 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
409 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
410 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
411 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
412 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
413 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
414 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
415 { X86::DIV_Fp32m , X86::DIV_F32m },
416 { X86::DIV_Fp64m , X86::DIV_F64m },
417 { X86::DIV_Fp64m32 , X86::DIV_F32m },
418 { X86::DIV_Fp80m32 , X86::DIV_F32m },
419 { X86::DIV_Fp80m64 , X86::DIV_F64m },
420 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
421 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
422 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
423 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
424 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
425 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
426 { X86::ILD_Fp16m32 , X86::ILD_F16m },
427 { X86::ILD_Fp16m64 , X86::ILD_F16m },
428 { X86::ILD_Fp16m80 , X86::ILD_F16m },
429 { X86::ILD_Fp32m32 , X86::ILD_F32m },
430 { X86::ILD_Fp32m64 , X86::ILD_F32m },
431 { X86::ILD_Fp32m80 , X86::ILD_F32m },
432 { X86::ILD_Fp64m32 , X86::ILD_F64m },
433 { X86::ILD_Fp64m64 , X86::ILD_F64m },
434 { X86::ILD_Fp64m80 , X86::ILD_F64m },
435 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
436 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
437 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
438 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
439 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
440 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
441 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
442 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
443 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
444 { X86::IST_Fp16m32 , X86::IST_F16m },
445 { X86::IST_Fp16m64 , X86::IST_F16m },
446 { X86::IST_Fp16m80 , X86::IST_F16m },
447 { X86::IST_Fp32m32 , X86::IST_F32m },
448 { X86::IST_Fp32m64 , X86::IST_F32m },
449 { X86::IST_Fp32m80 , X86::IST_F32m },
450 { X86::IST_Fp64m32 , X86::IST_FP64m },
451 { X86::IST_Fp64m64 , X86::IST_FP64m },
452 { X86::IST_Fp64m80 , X86::IST_FP64m },
453 { X86::LD_Fp032 , X86::LD_F0 },
454 { X86::LD_Fp064 , X86::LD_F0 },
455 { X86::LD_Fp080 , X86::LD_F0 },
456 { X86::LD_Fp132 , X86::LD_F1 },
457 { X86::LD_Fp164 , X86::LD_F1 },
458 { X86::LD_Fp180 , X86::LD_F1 },
459 { X86::LD_Fp32m , X86::LD_F32m },
460 { X86::LD_Fp32m64 , X86::LD_F32m },
461 { X86::LD_Fp32m80 , X86::LD_F32m },
462 { X86::LD_Fp64m , X86::LD_F64m },
463 { X86::LD_Fp64m80 , X86::LD_F64m },
464 { X86::LD_Fp80m , X86::LD_F80m },
465 { X86::MUL_Fp32m , X86::MUL_F32m },
466 { X86::MUL_Fp64m , X86::MUL_F64m },
467 { X86::MUL_Fp64m32 , X86::MUL_F32m },
468 { X86::MUL_Fp80m32 , X86::MUL_F32m },
469 { X86::MUL_Fp80m64 , X86::MUL_F64m },
470 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
471 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
472 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
473 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
474 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
475 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
476 { X86::SIN_Fp32 , X86::SIN_F },
477 { X86::SIN_Fp64 , X86::SIN_F },
478 { X86::SIN_Fp80 , X86::SIN_F },
479 { X86::SQRT_Fp32 , X86::SQRT_F },
480 { X86::SQRT_Fp64 , X86::SQRT_F },
481 { X86::SQRT_Fp80 , X86::SQRT_F },
482 { X86::ST_Fp32m , X86::ST_F32m },
483 { X86::ST_Fp64m , X86::ST_F64m },
484 { X86::ST_Fp64m32 , X86::ST_F32m },
485 { X86::ST_Fp80m32 , X86::ST_F32m },
486 { X86::ST_Fp80m64 , X86::ST_F64m },
487 { X86::ST_FpP80m , X86::ST_FP80m },
488 { X86::SUBR_Fp32m , X86::SUBR_F32m },
489 { X86::SUBR_Fp64m , X86::SUBR_F64m },
490 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
491 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
492 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
493 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
494 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
495 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
496 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
497 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
498 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
499 { X86::SUB_Fp32m , X86::SUB_F32m },
500 { X86::SUB_Fp64m , X86::SUB_F64m },
501 { X86::SUB_Fp64m32 , X86::SUB_F32m },
502 { X86::SUB_Fp80m32 , X86::SUB_F32m },
503 { X86::SUB_Fp80m64 , X86::SUB_F64m },
504 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
505 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
506 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
507 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
508 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
509 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
510 { X86::TST_Fp32 , X86::TST_F },
511 { X86::TST_Fp64 , X86::TST_F },
512 { X86::TST_Fp80 , X86::TST_F },
513 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
514 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
515 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
516 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
517 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
518 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
519 };
520
521 static unsigned getConcreteOpcode(unsigned Opcode) {
522 ASSERT_SORTED(OpcodeTable);
523 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
524 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
525 return Opc;
526 }
527
528 //===----------------------------------------------------------------------===//
529 // Helper Methods
530 //===----------------------------------------------------------------------===//
531
532 // PopTable - Sorted map of instructions to their popping version. The first
533 // element is an instruction, the second is the version which pops.
534 //
535 static const TableEntry PopTable[] = {
536 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
537
538 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
539 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
540
541 { X86::IST_F16m , X86::IST_FP16m },
542 { X86::IST_F32m , X86::IST_FP32m },
543
544 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
545
546 { X86::ST_F32m , X86::ST_FP32m },
547 { X86::ST_F64m , X86::ST_FP64m },
548 { X86::ST_Frr , X86::ST_FPrr },
549
550 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
551 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
552
553 { X86::UCOM_FIr , X86::UCOM_FIPr },
554
555 { X86::UCOM_FPr , X86::UCOM_FPPr },
556 { X86::UCOM_Fr , X86::UCOM_FPr },
557 };
558
559 /// popStackAfter - Pop the current value off of the top of the FP stack after
560 /// the specified instruction. This attempts to be sneaky and combine the pop
561 /// into the instruction itself if possible. The iterator is left pointing to
562 /// the last instruction, be it a new pop instruction inserted, or the old
563 /// instruction if it was modified in place.
564 ///
565 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
566 MachineInstr* MI = I;
567 DebugLoc dl = MI->getDebugLoc();
568 ASSERT_SORTED(PopTable);
569 assert(StackTop > 0 && "Cannot pop empty stack!");
570 RegMap[Stack[--StackTop]] = ~0; // Update state
571
572 // Check to see if there is a popping version of this instruction...
573 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
574 if (Opcode != -1) {
575 I->setDesc(TII->get(Opcode));
576 if (Opcode == X86::UCOM_FPPr)
577 I->RemoveOperand(0);
578 } else { // Insert an explicit pop
579 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
580 }
581 }
582
583 /// freeStackSlotAfter - Free the specified register from the register stack, so
584 /// that it is no longer in a register. If the register is currently at the top
585 /// of the stack, we just pop the current instruction, otherwise we store the
586 /// current top-of-stack into the specified slot, then pop the top of stack.
587 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
588 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
589 popStackAfter(I);
590 return;
591 }
592
593 // Otherwise, store the top of stack into the dead slot, killing the operand
594 // without having to add in an explicit xchg then pop.
595 //
596 unsigned STReg = getSTReg(FPRegNo);
597 unsigned OldSlot = getSlot(FPRegNo);
598 unsigned TopReg = Stack[StackTop-1];
599 Stack[OldSlot] = TopReg;
600 RegMap[TopReg] = OldSlot;
601 RegMap[FPRegNo] = ~0;
602 Stack[--StackTop] = ~0;
603 MachineInstr *MI = I;
604 DebugLoc dl = MI->getDebugLoc();
605 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
606 }
607
608
609 //===----------------------------------------------------------------------===//
610 // Instruction transformation implementation
611 //===----------------------------------------------------------------------===//
612
613 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
614 ///
615 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
616 MachineInstr *MI = I;
617 unsigned DestReg = getFPReg(MI->getOperand(0));
618
619 // Change from the pseudo instruction to the concrete instruction.
620 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
621 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
622
623 // Result gets pushed on the stack.
624 pushReg(DestReg);
625 }
626
627 /// handleOneArgFP - fst <mem>, ST(0)
628 ///
629 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
630 MachineInstr *MI = I;
631 unsigned NumOps = MI->getDesc().getNumOperands();
632 assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) &&
633 "Can only handle fst* & ftst instructions!");
634
635 // Is this the last use of the source register?
636 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
637 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
638
639 // FISTP64m is strange because there isn't a non-popping versions.
640 // If we have one _and_ we don't want to pop the operand, duplicate the value
641 // on the stack instead of moving it. This ensure that popping the value is
642 // always ok.
643 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
644 //
645 if (!KillsSrc &&
646 (MI->getOpcode() == X86::IST_Fp64m32 ||
647 MI->getOpcode() == X86::ISTT_Fp16m32 ||
648 MI->getOpcode() == X86::ISTT_Fp32m32 ||
649 MI->getOpcode() == X86::ISTT_Fp64m32 ||
650 MI->getOpcode() == X86::IST_Fp64m64 ||
651 MI->getOpcode() == X86::ISTT_Fp16m64 ||
652 MI->getOpcode() == X86::ISTT_Fp32m64 ||
653 MI->getOpcode() == X86::ISTT_Fp64m64 ||
654 MI->getOpcode() == X86::IST_Fp64m80 ||
655 MI->getOpcode() == X86::ISTT_Fp16m80 ||
656 MI->getOpcode() == X86::ISTT_Fp32m80 ||
657 MI->getOpcode() == X86::ISTT_Fp64m80 ||
658 MI->getOpcode() == X86::ST_FpP80m)) {
659 duplicateToTop(Reg, 7 /*temp register*/, I);
660 } else {
661 moveToTop(Reg, I); // Move to the top of the stack...
662 }
663
664 // Convert from the pseudo instruction to the concrete instruction.
665 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
666 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
667
668 if (MI->getOpcode() == X86::IST_FP64m ||
669 MI->getOpcode() == X86::ISTT_FP16m ||
670 MI->getOpcode() == X86::ISTT_FP32m ||
671 MI->getOpcode() == X86::ISTT_FP64m ||
672 MI->getOpcode() == X86::ST_FP80m) {
673 assert(StackTop > 0 && "Stack empty??");
674 --StackTop;
675 } else if (KillsSrc) { // Last use of operand?
676 popStackAfter(I);
677 }
678 }
679
680
681 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
682 /// replace the value with a newly computed value. These instructions may have
683 /// non-fp operands after their FP operands.
684 ///
685 /// Examples:
686 /// R1 = fchs R2
687 /// R1 = fadd R2, [mem]
688 ///
689 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
690 MachineInstr *MI = I;
691 #ifndef NDEBUG
692 unsigned NumOps = MI->getDesc().getNumOperands();
693 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
694 #endif
695
696 // Is this the last use of the source register?
697 unsigned Reg = getFPReg(MI->getOperand(1));
698 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
699
700 if (KillsSrc) {
701 // If this is the last use of the source register, just make sure it's on
702 // the top of the stack.
703 moveToTop(Reg, I);
704 assert(StackTop > 0 && "Stack cannot be empty!");
705 --StackTop;
706 pushReg(getFPReg(MI->getOperand(0)));
707 } else {
708 // If this is not the last use of the source register, _copy_ it to the top
709 // of the stack.
710 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
711 }
712
713 // Change from the pseudo instruction to the concrete instruction.
714 MI->RemoveOperand(1); // Drop the source operand.
715 MI->RemoveOperand(0); // Drop the destination operand.
716 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
717 }
718
719
720 //===----------------------------------------------------------------------===//
721 // Define tables of various ways to map pseudo instructions
722 //
723
724 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
725 static const TableEntry ForwardST0Table[] = {
726 { X86::ADD_Fp32 , X86::ADD_FST0r },
727 { X86::ADD_Fp64 , X86::ADD_FST0r },
728 { X86::ADD_Fp80 , X86::ADD_FST0r },
729 { X86::DIV_Fp32 , X86::DIV_FST0r },
730 { X86::DIV_Fp64 , X86::DIV_FST0r },
731 { X86::DIV_Fp80 , X86::DIV_FST0r },
732 { X86::MUL_Fp32 , X86::MUL_FST0r },
733 { X86::MUL_Fp64 , X86::MUL_FST0r },
734 { X86::MUL_Fp80 , X86::MUL_FST0r },
735 { X86::SUB_Fp32 , X86::SUB_FST0r },
736 { X86::SUB_Fp64 , X86::SUB_FST0r },
737 { X86::SUB_Fp80 , X86::SUB_FST0r },
738 };
739
740 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
741 static const TableEntry ReverseST0Table[] = {
742 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
743 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
744 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
745 { X86::DIV_Fp32 , X86::DIVR_FST0r },
746 { X86::DIV_Fp64 , X86::DIVR_FST0r },
747 { X86::DIV_Fp80 , X86::DIVR_FST0r },
748 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
749 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
750 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
751 { X86::SUB_Fp32 , X86::SUBR_FST0r },
752 { X86::SUB_Fp64 , X86::SUBR_FST0r },
753 { X86::SUB_Fp80 , X86::SUBR_FST0r },
754 };
755
756 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
757 static const TableEntry ForwardSTiTable[] = {
758 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
759 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
760 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
761 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
762 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
763 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
764 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
765 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
766 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
767 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
768 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
769 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
770 };
771
772 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
773 static const TableEntry ReverseSTiTable[] = {
774 { X86::ADD_Fp32 , X86::ADD_FrST0 },
775 { X86::ADD_Fp64 , X86::ADD_FrST0 },
776 { X86::ADD_Fp80 , X86::ADD_FrST0 },
777 { X86::DIV_Fp32 , X86::DIV_FrST0 },
778 { X86::DIV_Fp64 , X86::DIV_FrST0 },
779 { X86::DIV_Fp80 , X86::DIV_FrST0 },
780 { X86::MUL_Fp32 , X86::MUL_FrST0 },
781 { X86::MUL_Fp64 , X86::MUL_FrST0 },
782 { X86::MUL_Fp80 , X86::MUL_FrST0 },
783 { X86::SUB_Fp32 , X86::SUB_FrST0 },
784 { X86::SUB_Fp64 , X86::SUB_FrST0 },
785 { X86::SUB_Fp80 , X86::SUB_FrST0 },
786 };
787
788
789 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
790 /// instructions which need to be simplified and possibly transformed.
791 ///
792 /// Result: ST(0) = fsub ST(0), ST(i)
793 /// ST(i) = fsub ST(0), ST(i)
794 /// ST(0) = fsubr ST(0), ST(i)
795 /// ST(i) = fsubr ST(0), ST(i)
796 ///
797 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
798 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
799 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
800 MachineInstr *MI = I;
801
802 unsigned NumOperands = MI->getDesc().getNumOperands();
803 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
804 unsigned Dest = getFPReg(MI->getOperand(0));
805 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
806 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
807 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
808 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
809 DebugLoc dl = MI->getDebugLoc();
810
811 unsigned TOS = getStackEntry(0);
812
813 // One of our operands must be on the top of the stack. If neither is yet, we
814 // need to move one.
815 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
816 // We can choose to move either operand to the top of the stack. If one of
817 // the operands is killed by this instruction, we want that one so that we
818 // can update right on top of the old version.
819 if (KillsOp0) {
820 moveToTop(Op0, I); // Move dead operand to TOS.
821 TOS = Op0;
822 } else if (KillsOp1) {
823 moveToTop(Op1, I);
824 TOS = Op1;
825 } else {
826 // All of the operands are live after this instruction executes, so we
827 // cannot update on top of any operand. Because of this, we must
828 // duplicate one of the stack elements to the top. It doesn't matter
829 // which one we pick.
830 //
831 duplicateToTop(Op0, Dest, I);
832 Op0 = TOS = Dest;
833 KillsOp0 = true;
834 }
835 } else if (!KillsOp0 && !KillsOp1) {
836 // If we DO have one of our operands at the top of the stack, but we don't
837 // have a dead operand, we must duplicate one of the operands to a new slot
838 // on the stack.
839 duplicateToTop(Op0, Dest, I);
840 Op0 = TOS = Dest;
841 KillsOp0 = true;
842 }
843
844 // Now we know that one of our operands is on the top of the stack, and at
845 // least one of our operands is killed by this instruction.
846 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
847 "Stack conditions not set up right!");
848
849 // We decide which form to use based on what is on the top of the stack, and
850 // which operand is killed by this instruction.
851 const TableEntry *InstTable;
852 bool isForward = TOS == Op0;
853 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
854 if (updateST0) {
855 if (isForward)
856 InstTable = ForwardST0Table;
857 else
858 InstTable = ReverseST0Table;
859 } else {
860 if (isForward)
861 InstTable = ForwardSTiTable;
862 else
863 InstTable = ReverseSTiTable;
864 }
865
866 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
867 MI->getOpcode());
868 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
869
870 // NotTOS - The register which is not on the top of stack...
871 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
872
873 // Replace the old instruction with a new instruction
874 MBB->remove(I++);
875 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
876
877 // If both operands are killed, pop one off of the stack in addition to
878 // overwriting the other one.
879 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
880 assert(!updateST0 && "Should have updated other operand!");
881 popStackAfter(I); // Pop the top of stack
882 }
883
884 // Update stack information so that we know the destination register is now on
885 // the stack.
886 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
887 assert(UpdatedSlot < StackTop && Dest < 7);
888 Stack[UpdatedSlot] = Dest;
889 RegMap[Dest] = UpdatedSlot;
890 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
891 }
892
893 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
894 /// register arguments and no explicit destinations.
895 ///
896 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
897 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
898 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
899 MachineInstr *MI = I;
900
901 unsigned NumOperands = MI->getDesc().getNumOperands();
902 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
903 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
904 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
905 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
906 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
907
908 // Make sure the first operand is on the top of stack, the other one can be
909 // anywhere.
910 moveToTop(Op0, I);
911
912 // Change from the pseudo instruction to the concrete instruction.
913 MI->getOperand(0).setReg(getSTReg(Op1));
914 MI->RemoveOperand(1);
915 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
916
917 // If any of the operands are killed by this instruction, free them.
918 if (KillsOp0) freeStackSlotAfter(I, Op0);
919 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
920 }
921
922 /// handleCondMovFP - Handle two address conditional move instructions. These
923 /// instructions move a st(i) register to st(0) iff a condition is true. These
924 /// instructions require that the first operand is at the top of the stack, but
925 /// otherwise don't modify the stack at all.
926 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
927 MachineInstr *MI = I;
928
929 unsigned Op0 = getFPReg(MI->getOperand(0));
930 unsigned Op1 = getFPReg(MI->getOperand(2));
931 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
932
933 // The first operand *must* be on the top of the stack.
934 moveToTop(Op0, I);
935
936 // Change the second operand to the stack register that the operand is in.
937 // Change from the pseudo instruction to the concrete instruction.
938 MI->RemoveOperand(0);
939 MI->RemoveOperand(1);
940 MI->getOperand(0).setReg(getSTReg(Op1));
941 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
942
943 // If we kill the second operand, make sure to pop it from the stack.
944 if (Op0 != Op1 && KillsOp1) {
945 // Get this value off of the register stack.
946 freeStackSlotAfter(I, Op1);
947 }
948 }
949
950
951 /// handleSpecialFP - Handle special instructions which behave unlike other
952 /// floating point instructions. This is primarily intended for use by pseudo
953 /// instructions.
954 ///
955 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
956 MachineInstr *MI = I;
957 DebugLoc dl = MI->getDebugLoc();
958 switch (MI->getOpcode()) {
959 default: llvm_unreachable("Unknown SpecialFP instruction!");
960 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
961 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
962 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
963 assert(StackTop == 0 && "Stack should be empty after a call!");
964 pushReg(getFPReg(MI->getOperand(0)));
965 break;
966 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
967 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
968 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
969 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
970 // The pattern we expect is:
971 // CALL
972 // FP1 = FpGET_ST0
973 // FP4 = FpGET_ST1
974 //
975 // At this point, we've pushed FP1 on the top of stack, so it should be
976 // present if it isn't dead. If it was dead, we already emitted a pop to
977 // remove it from the stack and StackTop = 0.
978
979 // Push FP4 as top of stack next.
980 pushReg(getFPReg(MI->getOperand(0)));
981
982 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
983 // dead. In this case, the ST(1) value is the only thing that is live, so
984 // it should be on the TOS (after the pop that was emitted) and is. Just
985 // continue in this case.
986 if (StackTop == 1)
987 break;
988
989 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
990 // elements so that our accounting is correct.
991 unsigned RegOnTop = getStackEntry(0);
992 unsigned RegNo = getStackEntry(1);
993
994 // Swap the slots the regs are in.
995 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
996
997 // Swap stack slot contents.
998 assert(RegMap[RegOnTop] < StackTop);
999 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
1000 break;
1001 }
1002 case X86::FpSET_ST0_32:
1003 case X86::FpSET_ST0_64:
1004 case X86::FpSET_ST0_80: {
1005 unsigned Op0 = getFPReg(MI->getOperand(0));
1006
1007 // FpSET_ST0_80 is generated by copyRegToReg for both function return
1008 // and inline assembly with the "st" constrain. In the latter case,
1009 // it is possible for ST(0) to be alive after this instruction.
1010 if (!MI->killsRegister(X86::FP0 + Op0)) {
1011 // Duplicate Op0
1012 duplicateToTop(0, 7 /*temp register*/, I);
1013 } else {
1014 moveToTop(Op0, I);
1015 }
1016 --StackTop; // "Forget" we have something on the top of stack!
1017 break;
1018 }
1019 case X86::FpSET_ST1_32:
1020 case X86::FpSET_ST1_64:
1021 case X86::FpSET_ST1_80:
1022 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1023 if (StackTop == 1) {
1024 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1025 NumFXCH++;
1026 StackTop = 0;
1027 break;
1028 }
1029 assert(StackTop == 2 && "Stack should have two element on it to return!");
1030 --StackTop; // "Forget" we have something on the top of stack!
1031 break;
1032 case X86::MOV_Fp3232:
1033 case X86::MOV_Fp3264:
1034 case X86::MOV_Fp6432:
1035 case X86::MOV_Fp6464:
1036 case X86::MOV_Fp3280:
1037 case X86::MOV_Fp6480:
1038 case X86::MOV_Fp8032:
1039 case X86::MOV_Fp8064:
1040 case X86::MOV_Fp8080: {
1041 const MachineOperand &MO1 = MI->getOperand(1);
1042 unsigned SrcReg = getFPReg(MO1);
1043
1044 const MachineOperand &MO0 = MI->getOperand(0);
1045 // These can be created due to inline asm. Two address pass can introduce
1046 // copies from RFP registers to virtual registers.
1047 if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
1048 assert(MO1.isKill());
1049 // Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
1050 // like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
1051 assert((StackTop == 1 || StackTop == 2)
1052 && "Stack should have one or two element on it to return!");
1053 --StackTop; // "Forget" we have something on the top of stack!
1054 break;
1055 } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
1056 assert(MO1.isKill());
1057 // Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
1058 // like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
1059 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1060 if (StackTop == 1) {
1061 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1062 NumFXCH++;
1063 StackTop = 0;
1064 break;
1065 }
1066 assert(StackTop == 2 && "Stack should have two element on it to return!");
1067 --StackTop; // "Forget" we have something on the top of stack!
1068 break;
1069 }
1070
1071 unsigned DestReg = getFPReg(MO0);
1072 if (MI->killsRegister(X86::FP0+SrcReg)) {
1073 // If the input operand is killed, we can just change the owner of the
1074 // incoming stack slot into the result.
1075 unsigned Slot = getSlot(SrcReg);
1076 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1077 Stack[Slot] = DestReg;
1078 RegMap[DestReg] = Slot;
1079
1080 } else {
1081 // For FMOV we just duplicate the specified value to a new stack slot.
1082 // This could be made better, but would require substantial changes.
1083 duplicateToTop(SrcReg, DestReg, I);
1084 }
1085 }
1086 break;
1087 case TargetInstrInfo::INLINEASM: {
1088 // The inline asm MachineInstr currently only *uses* FP registers for the
1089 // 'f' constraint. These should be turned into the current ST(x) register
1090 // in the machine instr. Also, any kills should be explicitly popped after
1091 // the inline asm.
1092 unsigned Kills[7];
1093 unsigned NumKills = 0;
1094 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1095 MachineOperand &Op = MI->getOperand(i);
1096 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1097 continue;
1098 assert(Op.isUse() && "Only handle inline asm uses right now");
1099
1100 unsigned FPReg = getFPReg(Op);
1101 Op.setReg(getSTReg(FPReg));
1102
1103 // If we kill this operand, make sure to pop it from the stack after the
1104 // asm. We just remember it for now, and pop them all off at the end in
1105 // a batch.
1106 if (Op.isKill())
1107 Kills[NumKills++] = FPReg;
1108 }
1109
1110 // If this asm kills any FP registers (is the last use of them) we must
1111 // explicitly emit pop instructions for them. Do this now after the asm has
1112 // executed so that the ST(x) numbers are not off (which would happen if we
1113 // did this inline with operand rewriting).
1114 //
1115 // Note: this might be a non-optimal pop sequence. We might be able to do
1116 // better by trying to pop in stack order or something.
1117 MachineBasicBlock::iterator InsertPt = MI;
1118 while (NumKills)
1119 freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1120
1121 // Don't delete the inline asm!
1122 return;
1123 }
1124
1125 case X86::RET:
1126 case X86::RETI:
1127 // If RET has an FP register use operand, pass the first one in ST(0) and
1128 // the second one in ST(1).
1129 if (isStackEmpty()) return; // Quick check to see if any are possible.
1130
1131 // Find the register operands.
1132 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1133
1134 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1135 MachineOperand &Op = MI->getOperand(i);
1136 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1137 continue;
1138 // FP Register uses must be kills unless there are two uses of the same
1139 // register, in which case only one will be a kill.
1140 assert(Op.isUse() &&
1141 (Op.isKill() || // Marked kill.
1142 getFPReg(Op) == FirstFPRegOp || // Second instance.
1143 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1144 "Ret only defs operands, and values aren't live beyond it");
1145
1146 if (FirstFPRegOp == ~0U)
1147 FirstFPRegOp = getFPReg(Op);
1148 else {
1149 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1150 SecondFPRegOp = getFPReg(Op);
1151 }
1152
1153 // Remove the operand so that later passes don't see it.
1154 MI->RemoveOperand(i);
1155 --i, --e;
1156 }
1157
1158 // There are only four possibilities here:
1159 // 1) we are returning a single FP value. In this case, it has to be in
1160 // ST(0) already, so just declare success by removing the value from the
1161 // FP Stack.
1162 if (SecondFPRegOp == ~0U) {
1163 // Assert that the top of stack contains the right FP register.
1164 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1165 "Top of stack not the right register for RET!");
1166
1167 // Ok, everything is good, mark the value as not being on the stack
1168 // anymore so that our assertion about the stack being empty at end of
1169 // block doesn't fire.
1170 StackTop = 0;
1171 return;
1172 }
1173
1174 // Otherwise, we are returning two values:
1175 // 2) If returning the same value for both, we only have one thing in the FP
1176 // stack. Consider: RET FP1, FP1
1177 if (StackTop == 1) {
1178 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1179 "Stack misconfiguration for RET!");
1180
1181 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1182 // register to hold it.
1183 unsigned NewReg = (FirstFPRegOp+1)%7;
1184 duplicateToTop(FirstFPRegOp, NewReg, MI);
1185 FirstFPRegOp = NewReg;
1186 }
1187
1188 /// Okay we know we have two different FPx operands now:
1189 assert(StackTop == 2 && "Must have two values live!");
1190
1191 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1192 /// in ST(1). In this case, emit an fxch.
1193 if (getStackEntry(0) == SecondFPRegOp) {
1194 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1195 moveToTop(FirstFPRegOp, MI);
1196 }
1197
1198 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1199 /// ST(1). Just remove both from our understanding of the stack and return.
1200 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1201 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1202 StackTop = 0;
1203 return;
1204 }
1205
1206 I = MBB->erase(I); // Remove the pseudo instruction
1207 --I;
1208 }
AVR Backend for LLVM