lib/Target/XCore/XCoreInstrInfo.h

   1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the XCore implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef XCOREINSTRUCTIONINFO_H
  15 #define XCOREINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "XCoreRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 class XCoreInstrInfo : public TargetInstrInfoImpl {
  23   const XCoreRegisterInfo RI;
  24 public:
  25   XCoreInstrInfo();
  26
  27   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  28   /// such, whenever a client has an instance of instruction info, it should
  29   /// always be able to get register info as well (through this method).
  30   ///
  31   virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
  32
  33   /// Return true if the instruction is a register to register move and return
  34   /// the source and dest operands and their sub-register indices by reference.
  35   virtual bool isMoveInstr(const MachineInstr &MI,
  36                            unsigned &SrcReg, unsigned &DstReg,
  37                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  38
  39   /// isLoadFromStackSlot - If the specified machine instruction is a direct
  40   /// load from a stack slot, return the virtual or physical register number of
  41   /// the destination along with the FrameIndex of the loaded stack slot.  If
  42   /// not, return 0.  This predicate must return 0 if the instruction has
  43   /// any side effects other than loading from the stack slot.
  44   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  45                                        int &FrameIndex) const;
  46
  47   /// isStoreToStackSlot - If the specified machine instruction is a direct
  48   /// store to a stack slot, return the virtual or physical register number of
  49   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  50   /// not, return 0.  This predicate must return 0 if the instruction has
  51   /// any side effects other than storing to the stack slot.
  52   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  53                                       int &FrameIndex) const;
  54
  55   virtual bool isInvariantLoad(const MachineInstr *MI) const;
  56
  57   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  58                              MachineBasicBlock *&FBB,
  59                              SmallVectorImpl<MachineOperand> &Cond,
  60                              bool AllowModify) const;
  61
  62   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  63                              MachineBasicBlock *FBB,
  64                              const SmallVectorImpl<MachineOperand> &Cond) const;
  65
  66   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  67
  68   virtual bool copyRegToReg(MachineBasicBlock &MBB,
  69                             MachineBasicBlock::iterator I,
  70                             unsigned DestReg, unsigned SrcReg,
  71                             const TargetRegisterClass *DestRC,
  72                             const TargetRegisterClass *SrcRC) const;
  73
  74   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  75                                    MachineBasicBlock::iterator MI,
  76                                    unsigned SrcReg, bool isKill, int FrameIndex,
  77                                    const TargetRegisterClass *RC) const;
  78
  79   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  80                                     MachineBasicBlock::iterator MI,
  81                                     unsigned DestReg, int FrameIndex,
  82                                     const TargetRegisterClass *RC) const;
  83
  84   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
  85                                         MachineBasicBlock::iterator MI,
  86                                 const std::vector<CalleeSavedInfo> &CSI) const;
  87
  88   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
  89                                          MachineBasicBlock::iterator MI,
  90                                const std::vector<CalleeSavedInfo> &CSI) const;
  91
  92   virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
  93
  94   virtual bool ReverseBranchCondition(
  95                             SmallVectorImpl<MachineOperand> &Cond) const;
  96 };
  97
  98 }
  99
 100 #endif