lib/Target/ARM/Thumb2SizeReduction.cpp

   1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "t2-reduce-size"
  11 #include "ARM.h"
  12 #include "ARMAddressingModes.h"
  13 #include "ARMBaseRegisterInfo.h"
  14 #include "ARMBaseInstrInfo.h"
  15 #include "Thumb2InstrInfo.h"
  16 #include "llvm/CodeGen/MachineInstr.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunctionPass.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/Compiler.h"
  21 #include "llvm/Support/Debug.h"
  22 #include "llvm/ADT/DenseMap.h"
  23 #include "llvm/ADT/Statistic.h"
  24 using namespace llvm;
  25
  26 STATISTIC(NumNarrows,  "Number of 32-bit instrs reduced to 16-bit ones");
  27 STATISTIC(Num2Addrs,   "Number of 32-bit instrs reduced to 2addr 16-bit ones");
  28 STATISTIC(NumLdSts,    "Number of 32-bit load / store reduced to 16-bit ones");
  29
  30 static cl::opt<int> ReduceLimit("t2-reduce-limit",
  31                                 cl::init(-1), cl::Hidden);
  32 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
  33                                      cl::init(-1), cl::Hidden);
  34 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
  35                                      cl::init(-1), cl::Hidden);
  36
  37 namespace {
  38   /// ReduceTable - A static table with information on mapping from wide
  39   /// opcodes to narrow
  40   struct ReduceEntry {
  41     unsigned WideOpc;      // Wide opcode
  42     unsigned NarrowOpc1;   // Narrow opcode to transform to
  43     unsigned NarrowOpc2;   // Narrow opcode when it's two-address
  44     uint8_t  Imm1Limit;    // Limit of immediate field (bits)
  45     uint8_t  Imm2Limit;    // Limit of immediate field when it's two-address
  46     unsigned LowRegs1 : 1; // Only possible if low-registers are used
  47     unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
  48     unsigned PredCC1  : 2; // 0 - If predicated, cc is on and vice versa.
  49                            // 1 - No cc field.
  50                            // 2 - Always set CPSR.
  51     unsigned PredCC2  : 1;
  52     unsigned Special  : 1; // Needs to be dealt with specially
  53   };
  54
  55   static const ReduceEntry ReduceTable[] = {
  56     // Wide,        Narrow1,      Narrow2,     imm1,imm2,  lo1, lo2, P/C, S
  57     { ARM::t2ADCrr, 0,            ARM::tADC,     0,   0,    0,   1,  0,0, 0 },
  58     { ARM::t2ADDri, ARM::tADDi3,  ARM::tADDi8,   3,   8,    1,   1,  0,0, 0 },
  59     { ARM::t2ADDrr, ARM::tADDrr,  ARM::tADDhirr, 0,   0,    1,   0,  0,1, 0 },
  60     // Note: immediate scale is 4.
  61     { ARM::t2ADDrSPi,ARM::tADDrSPi,0,            8,   0,    1,   0,  1,0, 0 },
  62     { ARM::t2ADDSri,ARM::tADDi3,  ARM::tADDi8,   3,   8,    1,   1,  2,2, 1 },
  63     { ARM::t2ADDSrr,ARM::tADDrr,  0,             0,   0,    1,   0,  2,0, 1 },
  64     { ARM::t2ANDrr, 0,            ARM::tAND,     0,   0,    0,   1,  0,0, 0 },
  65     { ARM::t2ASRri, ARM::tASRri,  0,             5,   0,    1,   0,  0,0, 0 },
  66     { ARM::t2ASRrr, 0,            ARM::tASRrr,   0,   0,    0,   1,  0,0, 0 },
  67     { ARM::t2BICrr, 0,            ARM::tBIC,     0,   0,    0,   1,  0,0, 0 },
  68     { ARM::t2CMNrr, ARM::tCMN,    0,             0,   0,    1,   0,  2,0, 0 },
  69     { ARM::t2CMPri, ARM::tCMPi8,  0,             8,   0,    1,   0,  2,0, 0 },
  70     { ARM::t2CMPrr, ARM::tCMPhir, 0,             0,   0,    0,   0,  2,0, 0 },
  71     { ARM::t2CMPzri,ARM::tCMPzi8, 0,             8,   0,    1,   0,  2,0, 0 },
  72     { ARM::t2CMPzrr,ARM::tCMPzhir,0,             0,   0,    0,   0,  2,0, 0 },
  73     { ARM::t2EORrr, 0,            ARM::tEOR,     0,   0,    0,   1,  0,0, 0 },
  74     { ARM::t2LSLri, ARM::tLSLri,  0,             5,   0,    1,   0,  0,0, 0 },
  75     { ARM::t2LSLrr, 0,            ARM::tLSLrr,   0,   0,    0,   1,  0,0, 0 },
  76     { ARM::t2LSRri, ARM::tLSRri,  0,             5,   0,    1,   0,  0,0, 0 },
  77     { ARM::t2LSRrr, 0,            ARM::tLSRrr,   0,   0,    0,   1,  0,0, 0 },
  78     { ARM::t2MOVi,  ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0 },
  79     // FIXME: Do we need the 16-bit 'S' variant?
  80     { ARM::t2MOVr,ARM::tMOVgpr2gpr,0,            0,   0,    0,   0,  1,0, 0 },
  81     { ARM::t2MOVCCr,0,            ARM::tMOVCCr,  0,   0,    0,   0,  0,1, 0 },
  82     { ARM::t2MOVCCi,0,            ARM::tMOVCCi,  0,   8,    0,   0,  0,1, 0 },
  83     { ARM::t2MUL,   0,            ARM::tMUL,     0,   0,    0,   1,  0,0, 0 },
  84     { ARM::t2MVNr,  ARM::tMVN,    0,             0,   0,    1,   0,  0,0, 0 },
  85     { ARM::t2ORRrr, 0,            ARM::tORR,     0,   0,    0,   1,  0,0, 0 },
  86     { ARM::t2REV,   ARM::tREV,    0,             0,   0,    1,   0,  1,0, 0 },
  87     { ARM::t2REV16, ARM::tREV16,  0,             0,   0,    1,   0,  1,0, 0 },
  88     { ARM::t2REVSH, ARM::tREVSH,  0,             0,   0,    1,   0,  1,0, 0 },
  89     { ARM::t2RORrr, 0,            ARM::tROR,     0,   0,    0,   1,  0,0, 0 },
  90     { ARM::t2RSBri, ARM::tRSB,    0,             0,   0,    1,   0,  0,0, 1 },
  91     { ARM::t2RSBSri,ARM::tRSB,    0,             0,   0,    1,   0,  2,0, 1 },
  92     { ARM::t2SBCrr, 0,            ARM::tSBC,     0,   0,    0,   1,  0,0, 0 },
  93     { ARM::t2SUBri, ARM::tSUBi3,  ARM::tSUBi8,   3,   8,    1,   1,  0,0, 0 },
  94     { ARM::t2SUBrr, ARM::tSUBrr,  0,             0,   0,    1,   0,  0,0, 0 },
  95     { ARM::t2SUBSri,ARM::tSUBi3,  ARM::tSUBi8,   3,   8,    1,   1,  2,2, 0 },
  96     { ARM::t2SUBSrr,ARM::tSUBrr,  0,             0,   0,    1,   0,  2,0, 0 },
  97     { ARM::t2SXTBr, ARM::tSXTB,   0,             0,   0,    1,   0,  1,0, 0 },
  98     { ARM::t2SXTHr, ARM::tSXTH,   0,             0,   0,    1,   0,  1,0, 0 },
  99     { ARM::t2TSTrr, ARM::tTST,    0,             0,   0,    1,   0,  2,0, 0 },
 100     { ARM::t2UXTBr, ARM::tUXTB,   0,             0,   0,    1,   0,  1,0, 0 },
 101     { ARM::t2UXTHr, ARM::tUXTH,   0,             0,   0,    1,   0,  1,0, 0 },
 102
 103     // FIXME: Clean this up after splitting each Thumb load / store opcode
 104     // into multiple ones.
 105     { ARM::t2LDRi12,ARM::tLDR,    0,             5,   0,    1,   0,  0,0, 1 },
 106     { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
 107     { ARM::t2LDRBi12,ARM::tLDRB,  0,             5,   0,    1,   0,  0,0, 1 },
 108     { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
 109     { ARM::t2LDRHi12,ARM::tLDRH,  0,             5,   0,    1,   0,  0,0, 1 },
 110     { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
 111     { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
 112     { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
 113     { ARM::t2STRi12,ARM::tSTR,    0,             5,   0,    1,   0,  0,0, 1 },
 114     { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
 115     { ARM::t2STRBi12,ARM::tSTRB,  0,             5,   0,    1,   0,  0,0, 1 },
 116     { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
 117     { ARM::t2STRHi12,ARM::tSTRH,  0,             5,   0,    1,   0,  0,0, 1 },
 118     { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
 119
 120     { ARM::t2LDM_RET,0,           ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
 121     { ARM::t2LDM,   ARM::tLDM,    ARM::tPOP,     0,   0,    1,   1,  1,1, 1 },
 122     { ARM::t2STM,   ARM::tSTM,    ARM::tPUSH,    0,   0,    1,   1,  1,1, 1 },
 123   };
 124
 125   class VISIBILITY_HIDDEN Thumb2SizeReduce : public MachineFunctionPass {
 126   public:
 127     static char ID;
 128     Thumb2SizeReduce();
 129
 130     const TargetInstrInfo *TII;
 131
 132     virtual bool runOnMachineFunction(MachineFunction &MF);
 133
 134     virtual const char *getPassName() const {
 135       return "Thumb2 instruction size reduction pass";
 136     }
 137
 138   private:
 139     /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
 140     DenseMap<unsigned, unsigned> ReduceOpcodeMap;
 141
 142     bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
 143                          bool is2Addr, ARMCC::CondCodes Pred,
 144                          bool LiveCPSR, bool &HasCC, bool &CCDead);
 145
 146     bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
 147                          const ReduceEntry &Entry);
 148
 149     bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
 150                        const ReduceEntry &Entry, bool LiveCPSR);
 151
 152     /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
 153     /// instruction.
 154     bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
 155                        const ReduceEntry &Entry,
 156                        bool LiveCPSR);
 157
 158     /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
 159     /// non-two-address instruction.
 160     bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
 161                         const ReduceEntry &Entry,
 162                         bool LiveCPSR);
 163
 164     /// ReduceMBB - Reduce width of instructions in the specified basic block.
 165     bool ReduceMBB(MachineBasicBlock &MBB);
 166   };
 167   char Thumb2SizeReduce::ID = 0;
 168 }
 169
 170 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
 171   for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
 172     unsigned FromOpc = ReduceTable[i].WideOpc;
 173     if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
 174       assert(false && "Duplicated entries?");
 175   }
 176 }
 177
 178 static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
 179   for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
 180     if (*Regs == ARM::CPSR)
 181       return true;
 182   return false;
 183 }
 184
 185 bool
 186 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
 187                                   bool is2Addr, ARMCC::CondCodes Pred,
 188                                   bool LiveCPSR, bool &HasCC, bool &CCDead) {
 189   if ((is2Addr  && Entry.PredCC2 == 0) ||
 190       (!is2Addr && Entry.PredCC1 == 0)) {
 191     if (Pred == ARMCC::AL) {
 192       // Not predicated, must set CPSR.
 193       if (!HasCC) {
 194         // Original instruction was not setting CPSR, but CPSR is not
 195         // currently live anyway. It's ok to set it. The CPSR def is
 196         // dead though.
 197         if (!LiveCPSR) {
 198           HasCC = true;
 199           CCDead = true;
 200           return true;
 201         }
 202         return false;
 203       }
 204     } else {
 205       // Predicated, must not set CPSR.
 206       if (HasCC)
 207         return false;
 208     }
 209   } else if ((is2Addr  && Entry.PredCC2 == 2) ||
 210              (!is2Addr && Entry.PredCC1 == 2)) {
 211     /// Old opcode has an optional def of CPSR.
 212     if (HasCC)
 213       return true;
 214     // If both old opcode does not implicit CPSR def, then it's not ok since
 215     // these new opcodes CPSR def is not meant to be thrown away. e.g. CMP.
 216     if (!HasImplicitCPSRDef(MI->getDesc()))
 217       return false;
 218     HasCC = true;
 219   } else {
 220     // 16-bit instruction does not set CPSR.
 221     if (HasCC)
 222       return false;
 223   }
 224
 225   return true;
 226 }
 227
 228 static bool VerifyLowRegs(MachineInstr *MI) {
 229   unsigned Opc = MI->getOpcode();
 230   bool isPCOk = (Opc == ARM::t2LDM_RET) || (Opc == ARM::t2LDM);
 231   bool isLROk = (Opc == ARM::t2STM);
 232   bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
 233   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 234     const MachineOperand &MO = MI->getOperand(i);
 235     if (!MO.isReg() || MO.isImplicit())
 236       continue;
 237     unsigned Reg = MO.getReg();
 238     if (Reg == 0 || Reg == ARM::CPSR)
 239       continue;
 240     if (isPCOk && Reg == ARM::PC)
 241       continue;
 242     if (isLROk && Reg == ARM::LR)
 243       continue;
 244     if (isSPOk && Reg == ARM::SP)
 245       continue;
 246     if (!isARMLowRegister(Reg))
 247       return false;
 248   }
 249   return true;
 250 }
 251
 252 bool
 253 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
 254                                   const ReduceEntry &Entry) {
 255   if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
 256     return false;
 257
 258   unsigned Scale = 1;
 259   bool HasImmOffset = false;
 260   bool HasShift = false;
 261   bool isLdStMul = false;
 262   bool isPopPush = false;
 263   unsigned Opc = Entry.NarrowOpc1;
 264   unsigned OpNum = 3; // First 'rest' of operands.
 265   switch (Entry.WideOpc) {
 266   default:
 267     llvm_unreachable("Unexpected Thumb2 load / store opcode!");
 268   case ARM::t2LDRi12:
 269   case ARM::t2STRi12:
 270     Scale = 4;
 271     HasImmOffset = true;
 272     break;
 273   case ARM::t2LDRBi12:
 274   case ARM::t2STRBi12:
 275     HasImmOffset = true;
 276     break;
 277   case ARM::t2LDRHi12:
 278   case ARM::t2STRHi12:
 279     Scale = 2;
 280     HasImmOffset = true;
 281     break;
 282   case ARM::t2LDRs:
 283   case ARM::t2LDRBs:
 284   case ARM::t2LDRHs:
 285   case ARM::t2LDRSBs:
 286   case ARM::t2LDRSHs:
 287   case ARM::t2STRs:
 288   case ARM::t2STRBs:
 289   case ARM::t2STRHs:
 290     HasShift = true;
 291     OpNum = 4;
 292     break;
 293   case ARM::t2LDM_RET:
 294   case ARM::t2LDM:
 295   case ARM::t2STM: {
 296     OpNum = 0;
 297     unsigned BaseReg = MI->getOperand(0).getReg();
 298     unsigned Mode = MI->getOperand(1).getImm();
 299     if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
 300       Opc = Entry.NarrowOpc2;
 301       isPopPush = true;
 302       OpNum = 2;
 303     } else if (Entry.WideOpc == ARM::t2LDM_RET ||
 304                !isARMLowRegister(BaseReg) ||
 305                !ARM_AM::getAM4WBFlag(Mode) ||
 306                ARM_AM::getAM4SubMode(Mode) != ARM_AM::ia) {
 307       return false;
 308     }
 309     isLdStMul = true;
 310     break;
 311   }
 312   }
 313
 314   unsigned OffsetReg = 0;
 315   bool OffsetKill = false;
 316   if (HasShift) {
 317     OffsetReg  = MI->getOperand(2).getReg();
 318     OffsetKill = MI->getOperand(2).isKill();
 319     if (MI->getOperand(3).getImm())
 320       // Thumb1 addressing mode doesn't support shift.
 321       return false;
 322   }
 323
 324   unsigned OffsetImm = 0;
 325   if (HasImmOffset) {
 326     OffsetImm = MI->getOperand(2).getImm();
 327     unsigned MaxOffset = ((1 << Entry.Imm1Limit) - 1) * Scale;
 328     if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
 329       // Make sure the immediate field fits.
 330       return false;
 331   }
 332
 333   // Add the 16-bit load / store instruction.
 334   // FIXME: Thumb1 addressing mode encode both immediate and register offset.
 335   DebugLoc dl = MI->getDebugLoc();
 336   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
 337   if (!isLdStMul) {
 338     MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
 339     if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) {
 340       // tLDRSB and tLDRSH do not have an immediate offset field. On the other
 341       // hand, it must have an offset register.
 342       // FIXME: Remove this special case.
 343       MIB.addImm(OffsetImm/Scale);
 344     }
 345     assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
 346
 347     MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
 348   }
 349
 350   // Transfer the rest of operands.
 351   for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
 352     MIB.addOperand(MI->getOperand(OpNum));
 353
 354   DOUT << "Converted 32-bit: " << *MI << "       to 16-bit: " << *MIB;
 355
 356   MBB.erase(MI);
 357   ++NumLdSts;
 358   return true;
 359 }
 360
 361 bool
 362 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
 363                                 const ReduceEntry &Entry,
 364                                 bool LiveCPSR) {
 365   if (Entry.LowRegs1 && !VerifyLowRegs(MI))
 366     return false;
 367
 368   const TargetInstrDesc &TID = MI->getDesc();
 369   if (TID.mayLoad() || TID.mayStore())
 370     return ReduceLoadStore(MBB, MI, Entry);
 371
 372   unsigned Opc = MI->getOpcode();
 373   switch (Opc) {
 374   default: break;
 375   case ARM::t2ADDSri:
 376   case ARM::t2ADDSrr: {
 377     unsigned PredReg = 0;
 378     if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
 379       switch (Opc) {
 380       default: break;
 381       case ARM::t2ADDSri: {
 382         if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
 383           return true;
 384         // fallthrough
 385       }
 386       case ARM::t2ADDSrr:
 387         return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
 388       }
 389     }
 390     break;
 391   }
 392   case ARM::t2RSBri:
 393   case ARM::t2RSBSri:
 394     if (MI->getOperand(2).getImm() == 0)
 395       return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
 396     break;
 397   }
 398   return false;
 399 }
 400
 401 bool
 402 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
 403                                 const ReduceEntry &Entry,
 404                                 bool LiveCPSR) {
 405
 406   if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
 407     return false;
 408
 409   const TargetInstrDesc &TID = MI->getDesc();
 410   unsigned Reg0 = MI->getOperand(0).getReg();
 411   unsigned Reg1 = MI->getOperand(1).getReg();
 412   if (Reg0 != Reg1)
 413     return false;
 414   if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
 415     return false;
 416   if (Entry.Imm2Limit) {
 417     unsigned Imm = MI->getOperand(2).getImm();
 418     unsigned Limit = (1 << Entry.Imm2Limit) - 1;
 419     if (Imm > Limit)
 420       return false;
 421   } else {
 422     unsigned Reg2 = MI->getOperand(2).getReg();
 423     if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
 424       return false;
 425   }
 426
 427   // Check if it's possible / necessary to transfer the predicate.
 428   const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
 429   unsigned PredReg = 0;
 430   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
 431   bool SkipPred = false;
 432   if (Pred != ARMCC::AL) {
 433     if (!NewTID.isPredicable())
 434       // Can't transfer predicate, fail.
 435       return false;
 436   } else {
 437     SkipPred = !NewTID.isPredicable();
 438   }
 439
 440   bool HasCC = false;
 441   bool CCDead = false;
 442   if (TID.hasOptionalDef()) {
 443     unsigned NumOps = TID.getNumOperands();
 444     HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
 445     if (HasCC && MI->getOperand(NumOps-1).isDead())
 446       CCDead = true;
 447   }
 448   if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
 449     return false;
 450
 451   // Add the 16-bit instruction.
 452   DebugLoc dl = MI->getDebugLoc();
 453   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
 454   MIB.addOperand(MI->getOperand(0));
 455   if (HasCC && NewTID.hasOptionalDef())
 456     AddDefaultT1CC(MIB, CCDead);
 457
 458   // Transfer the rest of operands.
 459   unsigned NumOps = TID.getNumOperands();
 460   for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
 461     if (i < NumOps && TID.OpInfo[i].isOptionalDef())
 462       continue;
 463     if (SkipPred && TID.OpInfo[i].isPredicate())
 464       continue;
 465     MIB.addOperand(MI->getOperand(i));
 466   }
 467
 468   DOUT << "Converted 32-bit: " << *MI << "       to 16-bit: " << *MIB;
 469
 470   MBB.erase(MI);
 471   ++Num2Addrs;
 472   return true;
 473 }
 474
 475 bool
 476 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
 477                                  const ReduceEntry &Entry,
 478                                  bool LiveCPSR) {
 479   if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
 480     return false;
 481
 482   unsigned Limit = ~0U;
 483   unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
 484   if (Entry.Imm1Limit)
 485     Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
 486
 487   const TargetInstrDesc &TID = MI->getDesc();
 488   for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
 489     if (TID.OpInfo[i].isPredicate())
 490       continue;
 491     const MachineOperand &MO = MI->getOperand(i);
 492     if (MO.isReg()) {
 493       unsigned Reg = MO.getReg();
 494       if (!Reg || Reg == ARM::CPSR)
 495         continue;
 496       if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
 497         continue;
 498       if (Entry.LowRegs1 && !isARMLowRegister(Reg))
 499         return false;
 500     } else if (MO.isImm() &&
 501                !TID.OpInfo[i].isPredicate()) {
 502       if (MO.getImm() > Limit || (MO.getImm() & (Scale-1)) != 0)
 503         return false;
 504     }
 505   }
 506
 507   // Check if it's possible / necessary to transfer the predicate.
 508   const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
 509   unsigned PredReg = 0;
 510   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
 511   bool SkipPred = false;
 512   if (Pred != ARMCC::AL) {
 513     if (!NewTID.isPredicable())
 514       // Can't transfer predicate, fail.
 515       return false;
 516   } else {
 517     SkipPred = !NewTID.isPredicable();
 518   }
 519
 520   bool HasCC = false;
 521   bool CCDead = false;
 522   if (TID.hasOptionalDef()) {
 523     unsigned NumOps = TID.getNumOperands();
 524     HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
 525     if (HasCC && MI->getOperand(NumOps-1).isDead())
 526       CCDead = true;
 527   }
 528   if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
 529     return false;
 530
 531   // Add the 16-bit instruction.
 532   DebugLoc dl = MI->getDebugLoc();
 533   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
 534   MIB.addOperand(MI->getOperand(0));
 535   if (HasCC && NewTID.hasOptionalDef())
 536     AddDefaultT1CC(MIB, CCDead);
 537
 538   // Transfer the rest of operands.
 539   unsigned NumOps = TID.getNumOperands();
 540   for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
 541     if (i < NumOps && TID.OpInfo[i].isOptionalDef())
 542       continue;
 543     if ((TID.getOpcode() == ARM::t2RSBSri ||
 544          TID.getOpcode() == ARM::t2RSBri) && i == 2)
 545       // Skip the zero immediate operand, it's now implicit.
 546       continue;
 547     bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
 548     if (SkipPred && isPred)
 549         continue;
 550     const MachineOperand &MO = MI->getOperand(i);
 551     if (Scale > 1 && !isPred && MO.isImm())
 552       MIB.addImm(MO.getImm() / Scale);
 553     else {
 554       if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
 555         // Skip implicit def of CPSR. Either it's modeled as an optional
 556         // def now or it's already an implicit def on the new instruction.
 557         continue;
 558       MIB.addOperand(MO);
 559     }
 560   }
 561   if (!TID.isPredicable() && NewTID.isPredicable())
 562     AddDefaultPred(MIB);
 563
 564   DOUT << "Converted 32-bit: " << *MI << "       to 16-bit: " << *MIB;
 565
 566   MBB.erase(MI);
 567   ++NumNarrows;
 568   return true;
 569 }
 570
 571 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
 572   bool HasDef = false;
 573   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 574     const MachineOperand &MO = MI.getOperand(i);
 575     if (!MO.isReg() || MO.isUndef() || MO.isUse())
 576       continue;
 577     if (MO.getReg() != ARM::CPSR)
 578       continue;
 579     if (!MO.isDead())
 580       HasDef = true;
 581   }
 582
 583   return HasDef || LiveCPSR;
 584 }
 585
 586 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
 587   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 588     const MachineOperand &MO = MI.getOperand(i);
 589     if (!MO.isReg() || MO.isUndef() || MO.isDef())
 590       continue;
 591     if (MO.getReg() != ARM::CPSR)
 592       continue;
 593     assert(LiveCPSR && "CPSR liveness tracking is wrong!");
 594     if (MO.isKill()) {
 595       LiveCPSR = false;
 596       break;
 597     }
 598   }
 599
 600   return LiveCPSR;
 601 }
 602
 603 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
 604   bool Modified = false;
 605
 606   bool LiveCPSR = false;
 607   // Yes, CPSR could be livein.
 608   for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
 609          E = MBB.livein_end(); I != E; ++I) {
 610     if (*I == ARM::CPSR) {
 611       LiveCPSR = true;
 612       break;
 613     }
 614   }
 615
 616   MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
 617   MachineBasicBlock::iterator NextMII;
 618   for (; MII != E; MII = NextMII) {
 619     NextMII = next(MII);
 620
 621     MachineInstr *MI = &*MII;
 622     LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
 623
 624     unsigned Opcode = MI->getOpcode();
 625     DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
 626     if (OPI != ReduceOpcodeMap.end()) {
 627       const ReduceEntry &Entry = ReduceTable[OPI->second];
 628       // Ignore "special" cases for now.
 629       if (Entry.Special) {
 630         if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
 631           Modified = true;
 632           MachineBasicBlock::iterator I = prior(NextMII);
 633           MI = &*I;
 634         }
 635         goto ProcessNext;
 636       }
 637
 638       // Try to transform to a 16-bit two-address instruction.
 639       if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
 640         Modified = true;
 641         MachineBasicBlock::iterator I = prior(NextMII);
 642         MI = &*I;
 643         goto ProcessNext;
 644       }
 645
 646       // Try to transform ro a 16-bit non-two-address instruction.
 647       if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR))
 648         Modified = true;
 649     }
 650
 651   ProcessNext:
 652     LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
 653   }
 654
 655   return Modified;
 656 }
 657
 658 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
 659   const TargetMachine &TM = MF.getTarget();
 660   TII = TM.getInstrInfo();
 661
 662   bool Modified = false;
 663   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
 664     Modified |= ReduceMBB(*I);
 665   return Modified;
 666 }
 667
 668 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
 669 /// reduction pass.
 670 FunctionPass *llvm::createThumb2SizeReductionPass() {
 671   return new Thumb2SizeReduce();
 672 }