lib/CodeGen/LowerSubregs.cpp

   1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a MachineFunction pass which runs after register
  11 // allocation that turns subreg insert/extract instructions into register
  12 // copies, as needed. This ensures correct codegen even if the coalescer
  13 // isn't able to remove all subreg instructions.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "lowersubregs"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/Compiler.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 using namespace llvm;
  31
  32 namespace {
  33   struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
  34    : public MachineFunctionPass {
  35     static char ID; // Pass identification, replacement for typeid
  36     LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
  37
  38     const char *getPassName() const {
  39       return "Subregister lowering instruction pass";
  40     }
  41
  42     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  43       AU.setPreservesCFG();
  44       AU.addPreservedID(MachineLoopInfoID);
  45       AU.addPreservedID(MachineDominatorsID);
  46       MachineFunctionPass::getAnalysisUsage(AU);
  47     }
  48
  49     /// runOnMachineFunction - pass entry point
  50     bool runOnMachineFunction(MachineFunction&);
  51
  52     bool LowerExtract(MachineInstr *MI);
  53     bool LowerInsert(MachineInstr *MI);
  54     bool LowerSubregToReg(MachineInstr *MI);
  55
  56     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
  57                           const TargetRegisterInfo &TRI);
  58     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
  59                           const TargetRegisterInfo &TRI,
  60                           bool AddIfNotFound = false);
  61   };
  62
  63   char LowerSubregsInstructionPass::ID = 0;
  64 }
  65
  66 FunctionPass *llvm::createLowerSubregsPass() {
  67   return new LowerSubregsInstructionPass();
  68 }
  69
  70 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
  71 /// and the lowered replacement instructions immediately precede it.
  72 /// Mark the replacement instructions with the dead flag.
  73 void
  74 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
  75                                               unsigned DstReg,
  76                                               const TargetRegisterInfo &TRI) {
  77   for (MachineBasicBlock::iterator MII =
  78         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  79     if (MII->addRegisterDead(DstReg, &TRI))
  80       break;
  81     assert(MII != MI->getParent()->begin() &&
  82            "copyRegToReg output doesn't reference destination register!");
  83   }
  84 }
  85
  86 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
  87 /// and the lowered replacement instructions immediately precede it.
  88 /// Mark the replacement instructions with the kill flag.
  89 void
  90 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
  91                                               unsigned SrcReg,
  92                                               const TargetRegisterInfo &TRI,
  93                                               bool AddIfNotFound) {
  94   for (MachineBasicBlock::iterator MII =
  95         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  96     if (MII->addRegisterKilled(SrcReg, &TRI, AddIfNotFound))
  97       break;
  98     assert(MII != MI->getParent()->begin() &&
  99            "copyRegToReg output doesn't reference source register!");
 100   }
 101 }
 102
 103 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
 104   MachineBasicBlock *MBB = MI->getParent();
 105   MachineFunction &MF = *MBB->getParent();
 106   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 107   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 108
 109   assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
 110          MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
 111          MI->getOperand(2).isImm() && "Malformed extract_subreg");
 112
 113   unsigned DstReg   = MI->getOperand(0).getReg();
 114   unsigned SuperReg = MI->getOperand(1).getReg();
 115   unsigned SubIdx   = MI->getOperand(2).getImm();
 116   unsigned SrcReg   = TRI.getSubReg(SuperReg, SubIdx);
 117
 118   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
 119          "Extract supperg source must be a physical register");
 120   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 121          "Extract destination must be in a physical register");
 122   assert(SrcReg && "invalid subregister index for register");
 123
 124   DOUT << "subreg: CONVERTING: " << *MI;
 125
 126   if (SrcReg == DstReg) {
 127     // No need to insert an identity copy instruction.
 128     if (MI->getOperand(1).isKill()) {
 129       // We must make sure the super-register gets killed.Replace the
 130       // instruction with IMPLICIT_DEF.
 131       MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
 132       MI->RemoveOperand(2);     // SubIdx
 133       DOUT << "subreg: replace by: " << *MI;
 134       return true;
 135     }
 136     DOUT << "subreg: eliminated!";
 137   } else {
 138     // Insert copy
 139     const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
 140     const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
 141     bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
 142     (void)Emitted;
 143     assert(Emitted && "Subreg and Dst must be of compatible register class");
 144     // Transfer the kill/dead flags, if needed.
 145     if (MI->getOperand(0).isDead())
 146       TransferDeadFlag(MI, DstReg, TRI);
 147     if (MI->getOperand(1).isKill())
 148       TransferKillFlag(MI, SuperReg, TRI, true);
 149
 150 #ifndef NDEBUG
 151     MachineBasicBlock::iterator dMI = MI;
 152     DOUT << "subreg: " << *(--dMI);
 153 #endif
 154   }
 155
 156   DOUT << "\n";
 157   MBB->erase(MI);
 158   return true;
 159 }
 160
 161 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
 162   MachineBasicBlock *MBB = MI->getParent();
 163   MachineFunction &MF = *MBB->getParent();
 164   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 165   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 166   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 167          MI->getOperand(1).isImm() &&
 168          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 169           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 170
 171   unsigned DstReg  = MI->getOperand(0).getReg();
 172   unsigned InsReg  = MI->getOperand(2).getReg();
 173   unsigned InsSIdx = MI->getOperand(2).getSubReg();
 174   unsigned SubIdx  = MI->getOperand(3).getImm();
 175
 176   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 177   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 178
 179   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 180          "Insert destination must be in a physical register");
 181   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 182          "Inserted value must be in a physical register");
 183
 184   DOUT << "subreg: CONVERTING: " << *MI;
 185
 186   if (DstSubReg == InsReg && InsSIdx == 0) {
 187     // No need to insert an identify copy instruction.
 188     // Watch out for case like this:
 189     // %RAX<def> = ...
 190     // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
 191     // The first def is defining RAX, not EAX so the top bits were not
 192     // zero extended.
 193     DOUT << "subreg: eliminated!";
 194   } else {
 195     // Insert sub-register copy
 196     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 197     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 198     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 199     // Transfer the kill/dead flags, if needed.
 200     if (MI->getOperand(0).isDead())
 201       TransferDeadFlag(MI, DstSubReg, TRI);
 202     if (MI->getOperand(2).isKill())
 203       TransferKillFlag(MI, InsReg, TRI);
 204
 205 #ifndef NDEBUG
 206     MachineBasicBlock::iterator dMI = MI;
 207     DOUT << "subreg: " << *(--dMI);
 208 #endif
 209   }
 210
 211   DOUT << "\n";
 212   MBB->erase(MI);
 213   return true;
 214 }
 215
 216 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
 217   MachineBasicBlock *MBB = MI->getParent();
 218   MachineFunction &MF = *MBB->getParent();
 219   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 220   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 221   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 222          (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
 223          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 224           MI->getOperand(3).isImm() && "Invalid insert_subreg");
 225
 226   unsigned DstReg = MI->getOperand(0).getReg();
 227 #ifndef NDEBUG
 228   unsigned SrcReg = MI->getOperand(1).getReg();
 229 #endif
 230   unsigned InsReg = MI->getOperand(2).getReg();
 231   unsigned SubIdx = MI->getOperand(3).getImm();
 232
 233   assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
 234   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 235   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 236   assert(DstSubReg && "invalid subregister index for register");
 237   assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
 238          "Insert superreg source must be in a physical register");
 239   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 240          "Inserted value must be in a physical register");
 241
 242   DOUT << "subreg: CONVERTING: " << *MI;
 243
 244   if (DstSubReg == InsReg) {
 245     // No need to insert an identity copy instruction. If the SrcReg was
 246     // <undef>, we need to make sure it is alive by inserting an IMPLICIT_DEF
 247     if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
 248       MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
 249                                 TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg);
 250       if (MI->getOperand(2).isUndef())
 251         MIB.addReg(InsReg, RegState::Implicit | RegState::Undef);
 252       else
 253         MIB.addReg(InsReg, RegState::ImplicitKill);
 254     } else {
 255       DOUT << "subreg: eliminated!\n";
 256       MBB->erase(MI);
 257       return true;
 258     }
 259   } else {
 260     // Insert sub-register copy
 261     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 262     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 263     if (MI->getOperand(2).isUndef())
 264       // If the source register being inserted is undef, then this becomes an
 265       // implicit_def.
 266       BuildMI(*MBB, MI, MI->getDebugLoc(),
 267               TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg);
 268     else
 269       TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 270     MachineBasicBlock::iterator CopyMI = MI;
 271     --CopyMI;
 272
 273     // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
 274     if (!MI->getOperand(1).isUndef())
 275       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
 276
 277     // Transfer the kill/dead flags, if needed.
 278     if (MI->getOperand(0).isDead()) {
 279       TransferDeadFlag(MI, DstSubReg, TRI);
 280     } else {
 281       // Make sure the full DstReg is live after this replacement.
 282       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
 283     }
 284
 285     // Make sure the inserted register gets killed
 286     if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
 287       TransferKillFlag(MI, InsReg, TRI);
 288   }
 289
 290 #ifndef NDEBUG
 291   MachineBasicBlock::iterator dMI = MI;
 292   DOUT << "subreg: " << *(--dMI);
 293 #endif
 294
 295   DOUT << "\n";
 296   MBB->erase(MI);
 297   return true;
 298 }
 299
 300 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 301 /// copies.
 302 ///
 303 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 304   DOUT << "Machine Function\n";
 305
 306   bool MadeChange = false;
 307
 308   DOUT << "********** LOWERING SUBREG INSTRS **********\n";
 309   DEBUG(errs() << "********** Function: "
 310         << MF.getFunction()->getName() << '\n');
 311
 312   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
 313        mbbi != mbbe; ++mbbi) {
 314     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
 315          mi != me;) {
 316       MachineInstr *MI = mi++;
 317
 318       if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
 319         MadeChange |= LowerExtract(MI);
 320       } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
 321         MadeChange |= LowerInsert(MI);
 322       } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
 323         MadeChange |= LowerSubregToReg(MI);
 324       }
 325     }
 326   }
 327
 328   return MadeChange;
 329 }