Change allowsUnalignedMemoryAccesses to take type argument since some targets
[llvm/avr.git] / lib / CodeGen / SelectionDAG / SelectionDAGBuild.cpp
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1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/InlineAsm.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/CodeGen/DwarfWriter.h"
42 #include "llvm/Analysis/DebugInfo.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetFrameInfo.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include <algorithm>
57 using namespace llvm;
59 /// LimitFloatPrecision - Generate low-precision inline sequences for
60 /// some float libcalls (6, 8 or 12 bits).
61 static unsigned LimitFloatPrecision;
63 static cl::opt<unsigned, true>
64 LimitFPPrecision("limit-float-precision",
65 cl::desc("Generate low-precision inline sequences "
66 "for some float libcalls"),
67 cl::location(LimitFloatPrecision),
68 cl::init(0));
70 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
71 /// of insertvalue or extractvalue indices that identify a member, return
72 /// the linearized index of the start of the member.
73 ///
74 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
75 const unsigned *Indices,
76 const unsigned *IndicesEnd,
77 unsigned CurIndex = 0) {
78 // Base case: We're done.
79 if (Indices && Indices == IndicesEnd)
80 return CurIndex;
82 // Given a struct type, recursively traverse the elements.
83 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
84 for (StructType::element_iterator EB = STy->element_begin(),
85 EI = EB,
86 EE = STy->element_end();
87 EI != EE; ++EI) {
88 if (Indices && *Indices == unsigned(EI - EB))
89 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
90 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 return CurIndex;
94 // Given an array type, recursively traverse the elements.
95 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
96 const Type *EltTy = ATy->getElementType();
97 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
98 if (Indices && *Indices == i)
99 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
100 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 return CurIndex;
104 // We haven't found the type we're looking for, so keep searching.
105 return CurIndex + 1;
108 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
109 /// EVTs that represent all the individual underlying
110 /// non-aggregate types that comprise it.
112 /// If Offsets is non-null, it points to a vector to be filled in
113 /// with the in-memory offsets of each of the individual values.
115 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
116 SmallVectorImpl<EVT> &ValueVTs,
117 SmallVectorImpl<uint64_t> *Offsets = 0,
118 uint64_t StartingOffset = 0) {
119 // Given a struct type, recursively traverse the elements.
120 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
121 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
122 for (StructType::element_iterator EB = STy->element_begin(),
123 EI = EB,
124 EE = STy->element_end();
125 EI != EE; ++EI)
126 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
127 StartingOffset + SL->getElementOffset(EI - EB));
128 return;
130 // Given an array type, recursively traverse the elements.
131 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
132 const Type *EltTy = ATy->getElementType();
133 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
134 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
135 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
136 StartingOffset + i * EltSize);
137 return;
139 // Interpret void as zero return values.
140 if (Ty == Type::getVoidTy(Ty->getContext()))
141 return;
142 // Base case: we can get an EVT for this LLVM IR type.
143 ValueVTs.push_back(TLI.getValueType(Ty));
144 if (Offsets)
145 Offsets->push_back(StartingOffset);
148 namespace llvm {
149 /// RegsForValue - This struct represents the registers (physical or virtual)
150 /// that a particular set of values is assigned, and the type information about
151 /// the value. The most common situation is to represent one value at a time,
152 /// but struct or array values are handled element-wise as multiple values.
153 /// The splitting of aggregates is performed recursively, so that we never
154 /// have aggregate-typed registers. The values at this point do not necessarily
155 /// have legal types, so each value may require one or more registers of some
156 /// legal type.
158 struct VISIBILITY_HIDDEN RegsForValue {
159 /// TLI - The TargetLowering object.
161 const TargetLowering *TLI;
163 /// ValueVTs - The value types of the values, which may not be legal, and
164 /// may need be promoted or synthesized from one or more registers.
166 SmallVector<EVT, 4> ValueVTs;
168 /// RegVTs - The value types of the registers. This is the same size as
169 /// ValueVTs and it records, for each value, what the type of the assigned
170 /// register or registers are. (Individual values are never synthesized
171 /// from more than one type of register.)
173 /// With virtual registers, the contents of RegVTs is redundant with TLI's
174 /// getRegisterType member function, however when with physical registers
175 /// it is necessary to have a separate record of the types.
177 SmallVector<EVT, 4> RegVTs;
179 /// Regs - This list holds the registers assigned to the values.
180 /// Each legal or promoted value requires one register, and each
181 /// expanded value requires multiple registers.
183 SmallVector<unsigned, 4> Regs;
185 RegsForValue() : TLI(0) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> &regs,
189 EVT regvt, EVT valuevt)
190 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 const SmallVector<unsigned, 4> &regs,
193 const SmallVector<EVT, 4> &regvts,
194 const SmallVector<EVT, 4> &valuevts)
195 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
196 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
197 unsigned Reg, const Type *Ty) : TLI(&tli) {
198 ComputeValueVTs(tli, Ty, ValueVTs);
200 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
201 EVT ValueVT = ValueVTs[Value];
202 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
203 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
204 for (unsigned i = 0; i != NumRegs; ++i)
205 Regs.push_back(Reg + i);
206 RegVTs.push_back(RegisterVT);
207 Reg += NumRegs;
211 /// append - Add the specified values to this one.
212 void append(const RegsForValue &RHS) {
213 TLI = RHS.TLI;
214 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
215 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
216 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
221 /// this value and returns the result as a ValueVTs value. This uses
222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223 /// If the Flag pointer is NULL, no flag is used.
224 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
225 SDValue &Chain, SDValue *Flag) const;
227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
228 /// specified value into the registers specified by this object. This uses
229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
230 /// If the Flag pointer is NULL, no flag is used.
231 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
232 SDValue &Chain, SDValue *Flag) const;
234 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
235 /// operand list. This adds the code marker, matching input operand index
236 /// (if applicable), and includes the number of values added into it.
237 void AddInlineAsmOperands(unsigned Code,
238 bool HasMatching, unsigned MatchingIdx,
239 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
243 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
244 /// PHI nodes or outside of the basic block that defines it, or used by a
245 /// switch or atomic instruction, which may expand to multiple basic blocks.
246 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
247 if (isa<PHINode>(I)) return true;
248 BasicBlock *BB = I->getParent();
249 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
250 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
251 return true;
252 return false;
255 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
256 /// entry block, return true. This includes arguments used by switches, since
257 /// the switch may expand into multiple basic blocks.
258 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
259 // With FastISel active, we may be splitting blocks, so force creation
260 // of virtual registers for all non-dead arguments.
261 // Don't force virtual registers for byval arguments though, because
262 // fast-isel can't handle those in all cases.
263 if (EnableFastISel && !A->hasByValAttr())
264 return A->use_empty();
266 BasicBlock *Entry = A->getParent()->begin();
267 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
268 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
269 return false; // Use not in entry block.
270 return true;
273 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
274 : TLI(tli) {
277 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 SelectionDAG &DAG,
279 bool EnableFastISel) {
280 Fn = &fn;
281 MF = &mf;
282 RegInfo = &MF->getRegInfo();
284 // Create a vreg for each argument register that is not dead and is used
285 // outside of the entry block for the function.
286 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 AI != E; ++AI)
288 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
289 InitializeRegForValue(AI);
291 // Initialize the mapping of values to registers. This is only set up for
292 // instruction values that are used outside of the block that defines
293 // them.
294 Function::iterator BB = Fn->begin(), EB = Fn->end();
295 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
296 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
297 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
298 const Type *Ty = AI->getAllocatedType();
299 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
300 unsigned Align =
301 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
302 AI->getAlignment());
304 TySize *= CUI->getZExtValue(); // Get total allocated size.
305 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
306 StaticAllocaMap[AI] =
307 MF->getFrameInfo()->CreateStackObject(TySize, Align);
310 for (; BB != EB; ++BB)
311 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
312 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
313 if (!isa<AllocaInst>(I) ||
314 !StaticAllocaMap.count(cast<AllocaInst>(I)))
315 InitializeRegForValue(I);
317 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
318 // also creates the initial PHI MachineInstrs, though none of the input
319 // operands are populated.
320 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
321 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
322 MBBMap[BB] = MBB;
323 MF->push_back(MBB);
325 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
326 // appropriate.
327 PHINode *PN;
328 DebugLoc DL;
329 for (BasicBlock::iterator
330 I = BB->begin(), E = BB->end(); I != E; ++I) {
331 if (CallInst *CI = dyn_cast<CallInst>(I)) {
332 if (Function *F = CI->getCalledFunction()) {
333 switch (F->getIntrinsicID()) {
334 default: break;
335 case Intrinsic::dbg_stoppoint: {
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
338 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
339 break;
341 case Intrinsic::dbg_func_start: {
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
344 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
345 break;
351 PN = dyn_cast<PHINode>(I);
352 if (!PN || PN->use_empty()) continue;
354 unsigned PHIReg = ValueMap[PN];
355 assert(PHIReg && "PHI node does not have an assigned virtual register!");
357 SmallVector<EVT, 4> ValueVTs;
358 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
359 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
360 EVT VT = ValueVTs[vti];
361 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
362 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
363 for (unsigned i = 0; i != NumRegisters; ++i)
364 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
365 PHIReg += NumRegisters;
371 unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
372 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 EVT ValueVT = ValueVTs[Value];
389 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
397 return FirstReg;
400 /// getCopyFromParts - Create a value that contains the specified legal parts
401 /// combined into the value they represent. If the parts combine to a type
402 /// larger then ValueVT then AssertOp can be used to specify whether the extra
403 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
404 /// (ISD::AssertSext).
405 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
406 const SDValue *Parts,
407 unsigned NumParts, EVT PartVT, EVT ValueVT,
408 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
409 assert(NumParts > 0 && "No parts to assemble!");
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 SDValue Val = Parts[0];
413 if (NumParts > 1) {
414 // Assemble the value from multiple parts.
415 if (!ValueVT.isVector() && ValueVT.isInteger()) {
416 unsigned PartBits = PartVT.getSizeInBits();
417 unsigned ValueBits = ValueVT.getSizeInBits();
419 // Assemble the power of 2 part.
420 unsigned RoundParts = NumParts & (NumParts - 1) ?
421 1 << Log2_32(NumParts) : NumParts;
422 unsigned RoundBits = PartBits * RoundParts;
423 EVT RoundVT = RoundBits == ValueBits ?
424 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
425 SDValue Lo, Hi;
427 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
429 if (RoundParts > 2) {
430 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
431 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
432 PartVT, HalfVT);
433 } else {
434 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
435 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
437 if (TLI.isBigEndian())
438 std::swap(Lo, Hi);
439 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
441 if (RoundParts < NumParts) {
442 // Assemble the trailing non-power-of-2 part.
443 unsigned OddParts = NumParts - RoundParts;
444 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
445 Hi = getCopyFromParts(DAG, dl,
446 Parts+RoundParts, OddParts, PartVT, OddVT);
448 // Combine the round and odd parts.
449 Lo = Val;
450 if (TLI.isBigEndian())
451 std::swap(Lo, Hi);
452 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
453 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
454 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
455 DAG.getConstant(Lo.getValueType().getSizeInBits(),
456 TLI.getPointerTy()));
457 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
458 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
460 } else if (ValueVT.isVector()) {
461 // Handle a multi-element vector.
462 EVT IntermediateVT, RegisterVT;
463 unsigned NumIntermediates;
464 unsigned NumRegs =
465 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
466 NumIntermediates, RegisterVT);
467 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
468 NumParts = NumRegs; // Silence a compiler warning.
469 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
470 assert(RegisterVT == Parts[0].getValueType() &&
471 "Part type doesn't match part!");
473 // Assemble the parts into intermediate operands.
474 SmallVector<SDValue, 8> Ops(NumIntermediates);
475 if (NumIntermediates == NumParts) {
476 // If the register was not expanded, truncate or copy the value,
477 // as appropriate.
478 for (unsigned i = 0; i != NumParts; ++i)
479 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
480 PartVT, IntermediateVT);
481 } else if (NumParts > 0) {
482 // If the intermediate type was expanded, build the intermediate operands
483 // from the parts.
484 assert(NumParts % NumIntermediates == 0 &&
485 "Must expand into a divisible number of parts!");
486 unsigned Factor = NumParts / NumIntermediates;
487 for (unsigned i = 0; i != NumIntermediates; ++i)
488 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
489 PartVT, IntermediateVT);
492 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
493 // operands.
494 Val = DAG.getNode(IntermediateVT.isVector() ?
495 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
496 ValueVT, &Ops[0], NumIntermediates);
497 } else if (PartVT.isFloatingPoint()) {
498 // FP split into multiple FP parts (for ppcf128)
499 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
500 "Unexpected split");
501 SDValue Lo, Hi;
502 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
503 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
504 if (TLI.isBigEndian())
505 std::swap(Lo, Hi);
506 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
507 } else {
508 // FP split into integer parts (soft fp)
509 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
510 !PartVT.isVector() && "Unexpected split");
511 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
512 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
520 return Val;
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
544 } else {
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 llvm_unreachable("Unknown mismatch!");
561 return SDValue();
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, EVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 EVT PtrVT = TLI.getPointerTy();
572 EVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
577 if (!NumParts)
578 return;
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
583 Parts[0] = Val;
584 return;
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
595 } else {
596 llvm_unreachable("Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
607 } else {
608 llvm_unreachable("Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
617 if (NumParts == 1) {
618 assert(PartVT == ValueVT && "Type conversion failed!");
619 Parts[0] = Val;
620 return;
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
644 // EXTRACT_ELEMENT.
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
647 Val);
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
656 ThisVT, Part0,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
659 ThisVT, Part0,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
664 PartVT, Part0);
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
666 PartVT, Part1);
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
674 return;
677 // Vector ValueVT.
678 if (NumParts == 1) {
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
682 } else {
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
687 PartVT, Val,
688 DAG.getConstant(0, PtrVT));
692 Parts[0] = Val;
693 return;
696 // Handle a multi-element vector.
697 EVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
700 IntermediateVT, NumIntermediates, RegisterVT);
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
712 IntermediateVT, Val,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
714 PtrVT));
715 else
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
717 IntermediateVT, Val,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
723 // as appropriate.
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
728 // legal parts.
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
739 AA = &aa;
740 GFI = gfi;
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
749 /// consumed.
750 void SelectionDAGLowering::clear() {
751 NodeMap.clear();
752 PendingLoads.clear();
753 PendingExports.clear();
754 DAG.clear();
755 CurDebugLoc = DebugLoc::getUnknownLoc();
756 HasTailCall = false;
759 /// getRoot - Return the current virtual root of the Selection DAG,
760 /// flushing any PendingLoad items. This must be done before emitting
761 /// a store or any other node that may need to be ordered after any
762 /// prior load instructions.
764 SDValue SelectionDAGLowering::getRoot() {
765 if (PendingLoads.empty())
766 return DAG.getRoot();
768 if (PendingLoads.size() == 1) {
769 SDValue Root = PendingLoads[0];
770 DAG.setRoot(Root);
771 PendingLoads.clear();
772 return Root;
775 // Otherwise, we have to make a token factor node.
776 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
777 &PendingLoads[0], PendingLoads.size());
778 PendingLoads.clear();
779 DAG.setRoot(Root);
780 return Root;
783 /// getControlRoot - Similar to getRoot, but instead of flushing all the
784 /// PendingLoad items, flush all the PendingExports items. It is necessary
785 /// to do this before emitting a terminator instruction.
787 SDValue SelectionDAGLowering::getControlRoot() {
788 SDValue Root = DAG.getRoot();
790 if (PendingExports.empty())
791 return Root;
793 // Turn all of the CopyToReg chains into one factored node.
794 if (Root.getOpcode() != ISD::EntryToken) {
795 unsigned i = 0, e = PendingExports.size();
796 for (; i != e; ++i) {
797 assert(PendingExports[i].getNode()->getNumOperands() > 1);
798 if (PendingExports[i].getNode()->getOperand(0) == Root)
799 break; // Don't add the root if we already indirectly depend on it.
802 if (i == e)
803 PendingExports.push_back(Root);
806 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
807 &PendingExports[0],
808 PendingExports.size());
809 PendingExports.clear();
810 DAG.setRoot(Root);
811 return Root;
814 void SelectionDAGLowering::visit(Instruction &I) {
815 visit(I.getOpcode(), I);
818 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
819 // Note: this doesn't use InstVisitor, because it has to work with
820 // ConstantExpr's in addition to instructions.
821 switch (Opcode) {
822 default: llvm_unreachable("Unknown instruction type encountered!");
823 // Build the switch statement using the Instruction.def file.
824 #define HANDLE_INST(NUM, OPCODE, CLASS) \
825 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
826 #include "llvm/Instruction.def"
830 SDValue SelectionDAGLowering::getValue(const Value *V) {
831 SDValue &N = NodeMap[V];
832 if (N.getNode()) return N;
834 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
835 EVT VT = TLI.getValueType(V->getType(), true);
837 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
838 return N = DAG.getConstant(*CI, VT);
840 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
841 return N = DAG.getGlobalAddress(GV, VT);
843 if (isa<ConstantPointerNull>(C))
844 return N = DAG.getConstant(0, TLI.getPointerTy());
846 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
847 return N = DAG.getConstantFP(*CFP, VT);
849 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
850 return N = DAG.getUNDEF(VT);
852 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
853 visit(CE->getOpcode(), *CE);
854 SDValue N1 = NodeMap[V];
855 assert(N1.getNode() && "visit didn't populate the ValueMap!");
856 return N1;
859 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
860 SmallVector<SDValue, 4> Constants;
861 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
862 OI != OE; ++OI) {
863 SDNode *Val = getValue(*OI).getNode();
864 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
865 Constants.push_back(SDValue(Val, i));
867 return DAG.getMergeValues(&Constants[0], Constants.size(),
868 getCurDebugLoc());
871 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
872 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
873 "Unknown struct or array constant!");
875 SmallVector<EVT, 4> ValueVTs;
876 ComputeValueVTs(TLI, C->getType(), ValueVTs);
877 unsigned NumElts = ValueVTs.size();
878 if (NumElts == 0)
879 return SDValue(); // empty struct
880 SmallVector<SDValue, 4> Constants(NumElts);
881 for (unsigned i = 0; i != NumElts; ++i) {
882 EVT EltVT = ValueVTs[i];
883 if (isa<UndefValue>(C))
884 Constants[i] = DAG.getUNDEF(EltVT);
885 else if (EltVT.isFloatingPoint())
886 Constants[i] = DAG.getConstantFP(0, EltVT);
887 else
888 Constants[i] = DAG.getConstant(0, EltVT);
890 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
893 const VectorType *VecTy = cast<VectorType>(V->getType());
894 unsigned NumElements = VecTy->getNumElements();
896 // Now that we know the number and type of the elements, get that number of
897 // elements into the Ops array based on what kind of constant it is.
898 SmallVector<SDValue, 16> Ops;
899 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
900 for (unsigned i = 0; i != NumElements; ++i)
901 Ops.push_back(getValue(CP->getOperand(i)));
902 } else {
903 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
904 EVT EltVT = TLI.getValueType(VecTy->getElementType());
906 SDValue Op;
907 if (EltVT.isFloatingPoint())
908 Op = DAG.getConstantFP(0, EltVT);
909 else
910 Op = DAG.getConstant(0, EltVT);
911 Ops.assign(NumElements, Op);
914 // Create a BUILD_VECTOR node.
915 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
916 VT, &Ops[0], Ops.size());
919 // If this is a static alloca, generate it as the frameindex instead of
920 // computation.
921 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
922 DenseMap<const AllocaInst*, int>::iterator SI =
923 FuncInfo.StaticAllocaMap.find(AI);
924 if (SI != FuncInfo.StaticAllocaMap.end())
925 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
928 unsigned InReg = FuncInfo.ValueMap[V];
929 assert(InReg && "Value not in map!");
931 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
932 SDValue Chain = DAG.getEntryNode();
933 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
937 void SelectionDAGLowering::visitRet(ReturnInst &I) {
938 SDValue Chain = getControlRoot();
939 SmallVector<ISD::OutputArg, 8> Outs;
940 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
941 SmallVector<EVT, 4> ValueVTs;
942 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
943 unsigned NumValues = ValueVTs.size();
944 if (NumValues == 0) continue;
946 SDValue RetOp = getValue(I.getOperand(i));
947 for (unsigned j = 0, f = NumValues; j != f; ++j) {
948 EVT VT = ValueVTs[j];
950 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
952 const Function *F = I.getParent()->getParent();
953 if (F->paramHasAttr(0, Attribute::SExt))
954 ExtendKind = ISD::SIGN_EXTEND;
955 else if (F->paramHasAttr(0, Attribute::ZExt))
956 ExtendKind = ISD::ZERO_EXTEND;
958 // FIXME: C calling convention requires the return type to be promoted to
959 // at least 32-bit. But this is not necessary for non-C calling
960 // conventions. The frontend should mark functions whose return values
961 // require promoting with signext or zeroext attributes.
962 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
963 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
964 if (VT.bitsLT(MinVT))
965 VT = MinVT;
968 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
969 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
970 SmallVector<SDValue, 4> Parts(NumParts);
971 getCopyToParts(DAG, getCurDebugLoc(),
972 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
973 &Parts[0], NumParts, PartVT, ExtendKind);
975 // 'inreg' on function refers to return value
976 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
977 if (F->paramHasAttr(0, Attribute::InReg))
978 Flags.setInReg();
980 // Propagate extension type if any
981 if (F->paramHasAttr(0, Attribute::SExt))
982 Flags.setSExt();
983 else if (F->paramHasAttr(0, Attribute::ZExt))
984 Flags.setZExt();
986 for (unsigned i = 0; i < NumParts; ++i)
987 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
991 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
992 unsigned CallConv = DAG.getMachineFunction().getFunction()->getCallingConv();
993 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
994 Outs, getCurDebugLoc(), DAG);
996 // Verify that the target's LowerReturn behaved as expected.
997 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
998 "LowerReturn didn't return a valid chain!");
1000 // Update the DAG with the new chain value resulting from return lowering.
1001 DAG.setRoot(Chain);
1004 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1005 /// created for it, emit nodes to copy the value into the virtual
1006 /// registers.
1007 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1008 if (!V->use_empty()) {
1009 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1010 if (VMI != FuncInfo.ValueMap.end())
1011 CopyValueToVirtualRegister(V, VMI->second);
1015 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1016 /// the current basic block, add it to ValueMap now so that we'll get a
1017 /// CopyTo/FromReg.
1018 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1019 // No need to export constants.
1020 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1022 // Already exported?
1023 if (FuncInfo.isExportedInst(V)) return;
1025 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1026 CopyValueToVirtualRegister(V, Reg);
1029 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1030 const BasicBlock *FromBB) {
1031 // The operands of the setcc have to be in this block. We don't know
1032 // how to export them from some other block.
1033 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1034 // Can export from current BB.
1035 if (VI->getParent() == FromBB)
1036 return true;
1038 // Is already exported, noop.
1039 return FuncInfo.isExportedInst(V);
1042 // If this is an argument, we can export it if the BB is the entry block or
1043 // if it is already exported.
1044 if (isa<Argument>(V)) {
1045 if (FromBB == &FromBB->getParent()->getEntryBlock())
1046 return true;
1048 // Otherwise, can only export this if it is already exported.
1049 return FuncInfo.isExportedInst(V);
1052 // Otherwise, constants can always be exported.
1053 return true;
1056 static bool InBlock(const Value *V, const BasicBlock *BB) {
1057 if (const Instruction *I = dyn_cast<Instruction>(V))
1058 return I->getParent() == BB;
1059 return true;
1062 /// getFCmpCondCode - Return the ISD condition code corresponding to
1063 /// the given LLVM IR floating-point condition code. This includes
1064 /// consideration of global floating-point math flags.
1066 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1067 ISD::CondCode FPC, FOC;
1068 switch (Pred) {
1069 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1070 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1071 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1072 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1073 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1074 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1075 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1076 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1077 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1078 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1079 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1080 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1081 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1082 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1083 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1084 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1085 default:
1086 llvm_unreachable("Invalid FCmp predicate opcode!");
1087 FOC = FPC = ISD::SETFALSE;
1088 break;
1090 if (FiniteOnlyFPMath())
1091 return FOC;
1092 else
1093 return FPC;
1096 /// getICmpCondCode - Return the ISD condition code corresponding to
1097 /// the given LLVM IR integer condition code.
1099 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1100 switch (Pred) {
1101 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1102 case ICmpInst::ICMP_NE: return ISD::SETNE;
1103 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1104 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1105 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1106 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1107 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1108 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1109 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1110 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1111 default:
1112 llvm_unreachable("Invalid ICmp predicate opcode!");
1113 return ISD::SETNE;
1117 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1118 /// This function emits a branch and is used at the leaves of an OR or an
1119 /// AND operator tree.
1121 void
1122 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1123 MachineBasicBlock *TBB,
1124 MachineBasicBlock *FBB,
1125 MachineBasicBlock *CurBB) {
1126 const BasicBlock *BB = CurBB->getBasicBlock();
1128 // If the leaf of the tree is a comparison, merge the condition into
1129 // the caseblock.
1130 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1131 // The operands of the cmp have to be in this block. We don't know
1132 // how to export them from some other block. If this is the first block
1133 // of the sequence, no exporting is needed.
1134 if (CurBB == CurMBB ||
1135 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1136 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1137 ISD::CondCode Condition;
1138 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1139 Condition = getICmpCondCode(IC->getPredicate());
1140 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1141 Condition = getFCmpCondCode(FC->getPredicate());
1142 } else {
1143 Condition = ISD::SETEQ; // silence warning.
1144 llvm_unreachable("Unknown compare instruction");
1147 CaseBlock CB(Condition, BOp->getOperand(0),
1148 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1149 SwitchCases.push_back(CB);
1150 return;
1154 // Create a CaseBlock record representing this branch.
1155 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1156 NULL, TBB, FBB, CurBB);
1157 SwitchCases.push_back(CB);
1160 /// FindMergedConditions - If Cond is an expression like
1161 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1162 MachineBasicBlock *TBB,
1163 MachineBasicBlock *FBB,
1164 MachineBasicBlock *CurBB,
1165 unsigned Opc) {
1166 // If this node is not part of the or/and tree, emit it as a branch.
1167 Instruction *BOp = dyn_cast<Instruction>(Cond);
1168 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1169 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1170 BOp->getParent() != CurBB->getBasicBlock() ||
1171 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1172 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1173 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1174 return;
1177 // Create TmpBB after CurBB.
1178 MachineFunction::iterator BBI = CurBB;
1179 MachineFunction &MF = DAG.getMachineFunction();
1180 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1181 CurBB->getParent()->insert(++BBI, TmpBB);
1183 if (Opc == Instruction::Or) {
1184 // Codegen X | Y as:
1185 // jmp_if_X TBB
1186 // jmp TmpBB
1187 // TmpBB:
1188 // jmp_if_Y TBB
1189 // jmp FBB
1192 // Emit the LHS condition.
1193 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1195 // Emit the RHS condition into TmpBB.
1196 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1197 } else {
1198 assert(Opc == Instruction::And && "Unknown merge op!");
1199 // Codegen X & Y as:
1200 // jmp_if_X TmpBB
1201 // jmp FBB
1202 // TmpBB:
1203 // jmp_if_Y TBB
1204 // jmp FBB
1206 // This requires creation of TmpBB after CurBB.
1208 // Emit the LHS condition.
1209 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1211 // Emit the RHS condition into TmpBB.
1212 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1216 /// If the set of cases should be emitted as a series of branches, return true.
1217 /// If we should emit this as a bunch of and/or'd together conditions, return
1218 /// false.
1219 bool
1220 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1221 if (Cases.size() != 2) return true;
1223 // If this is two comparisons of the same values or'd or and'd together, they
1224 // will get folded into a single comparison, so don't emit two blocks.
1225 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1226 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1227 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1228 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1229 return false;
1232 return true;
1235 void SelectionDAGLowering::visitBr(BranchInst &I) {
1236 // Update machine-CFG edges.
1237 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1239 // Figure out which block is immediately after the current one.
1240 MachineBasicBlock *NextBlock = 0;
1241 MachineFunction::iterator BBI = CurMBB;
1242 if (++BBI != FuncInfo.MF->end())
1243 NextBlock = BBI;
1245 if (I.isUnconditional()) {
1246 // Update machine-CFG edges.
1247 CurMBB->addSuccessor(Succ0MBB);
1249 // If this is not a fall-through branch, emit the branch.
1250 if (Succ0MBB != NextBlock)
1251 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1252 MVT::Other, getControlRoot(),
1253 DAG.getBasicBlock(Succ0MBB)));
1254 return;
1257 // If this condition is one of the special cases we handle, do special stuff
1258 // now.
1259 Value *CondVal = I.getCondition();
1260 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1262 // If this is a series of conditions that are or'd or and'd together, emit
1263 // this as a sequence of branches instead of setcc's with and/or operations.
1264 // For example, instead of something like:
1265 // cmp A, B
1266 // C = seteq
1267 // cmp D, E
1268 // F = setle
1269 // or C, F
1270 // jnz foo
1271 // Emit:
1272 // cmp A, B
1273 // je foo
1274 // cmp D, E
1275 // jle foo
1277 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1278 if (BOp->hasOneUse() &&
1279 (BOp->getOpcode() == Instruction::And ||
1280 BOp->getOpcode() == Instruction::Or)) {
1281 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1282 // If the compares in later blocks need to use values not currently
1283 // exported from this block, export them now. This block should always
1284 // be the first entry.
1285 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1287 // Allow some cases to be rejected.
1288 if (ShouldEmitAsBranches(SwitchCases)) {
1289 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1290 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1291 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1294 // Emit the branch for this block.
1295 visitSwitchCase(SwitchCases[0]);
1296 SwitchCases.erase(SwitchCases.begin());
1297 return;
1300 // Okay, we decided not to do this, remove any inserted MBB's and clear
1301 // SwitchCases.
1302 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1303 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1305 SwitchCases.clear();
1309 // Create a CaseBlock record representing this branch.
1310 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1311 NULL, Succ0MBB, Succ1MBB, CurMBB);
1312 // Use visitSwitchCase to actually insert the fast branch sequence for this
1313 // cond branch.
1314 visitSwitchCase(CB);
1317 /// visitSwitchCase - Emits the necessary code to represent a single node in
1318 /// the binary search tree resulting from lowering a switch instruction.
1319 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1320 SDValue Cond;
1321 SDValue CondLHS = getValue(CB.CmpLHS);
1322 DebugLoc dl = getCurDebugLoc();
1324 // Build the setcc now.
1325 if (CB.CmpMHS == NULL) {
1326 // Fold "(X == true)" to X and "(X == false)" to !X to
1327 // handle common cases produced by branch lowering.
1328 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1329 CB.CC == ISD::SETEQ)
1330 Cond = CondLHS;
1331 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1332 CB.CC == ISD::SETEQ) {
1333 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1334 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1335 } else
1336 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1337 } else {
1338 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1340 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1341 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1343 SDValue CmpOp = getValue(CB.CmpMHS);
1344 EVT VT = CmpOp.getValueType();
1346 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1347 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1348 ISD::SETLE);
1349 } else {
1350 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1351 VT, CmpOp, DAG.getConstant(Low, VT));
1352 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1353 DAG.getConstant(High-Low, VT), ISD::SETULE);
1357 // Update successor info
1358 CurMBB->addSuccessor(CB.TrueBB);
1359 CurMBB->addSuccessor(CB.FalseBB);
1361 // Set NextBlock to be the MBB immediately after the current one, if any.
1362 // This is used to avoid emitting unnecessary branches to the next block.
1363 MachineBasicBlock *NextBlock = 0;
1364 MachineFunction::iterator BBI = CurMBB;
1365 if (++BBI != FuncInfo.MF->end())
1366 NextBlock = BBI;
1368 // If the lhs block is the next block, invert the condition so that we can
1369 // fall through to the lhs instead of the rhs block.
1370 if (CB.TrueBB == NextBlock) {
1371 std::swap(CB.TrueBB, CB.FalseBB);
1372 SDValue True = DAG.getConstant(1, Cond.getValueType());
1373 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1375 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1376 MVT::Other, getControlRoot(), Cond,
1377 DAG.getBasicBlock(CB.TrueBB));
1379 // If the branch was constant folded, fix up the CFG.
1380 if (BrCond.getOpcode() == ISD::BR) {
1381 CurMBB->removeSuccessor(CB.FalseBB);
1382 DAG.setRoot(BrCond);
1383 } else {
1384 // Otherwise, go ahead and insert the false branch.
1385 if (BrCond == getControlRoot())
1386 CurMBB->removeSuccessor(CB.TrueBB);
1388 if (CB.FalseBB == NextBlock)
1389 DAG.setRoot(BrCond);
1390 else
1391 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1392 DAG.getBasicBlock(CB.FalseBB)));
1396 /// visitJumpTable - Emit JumpTable node in the current MBB
1397 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1398 // Emit the code for the jump table
1399 assert(JT.Reg != -1U && "Should lower JT Header first!");
1400 EVT PTy = TLI.getPointerTy();
1401 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1402 JT.Reg, PTy);
1403 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1404 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1405 MVT::Other, Index.getValue(1),
1406 Table, Index));
1409 /// visitJumpTableHeader - This function emits necessary code to produce index
1410 /// in the JumpTable from switch case.
1411 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1412 JumpTableHeader &JTH) {
1413 // Subtract the lowest switch case value from the value being switched on and
1414 // conditional branch to default mbb if the result is greater than the
1415 // difference between smallest and largest cases.
1416 SDValue SwitchOp = getValue(JTH.SValue);
1417 EVT VT = SwitchOp.getValueType();
1418 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1419 DAG.getConstant(JTH.First, VT));
1421 // The SDNode we just created, which holds the value being switched on minus
1422 // the the smallest case value, needs to be copied to a virtual register so it
1423 // can be used as an index into the jump table in a subsequent basic block.
1424 // This value may be smaller or larger than the target's pointer type, and
1425 // therefore require extension or truncating.
1426 if (VT.bitsGT(TLI.getPointerTy()))
1427 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1428 TLI.getPointerTy(), SUB);
1429 else
1430 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1431 TLI.getPointerTy(), SUB);
1433 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1434 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1435 JumpTableReg, SwitchOp);
1436 JT.Reg = JumpTableReg;
1438 // Emit the range check for the jump table, and branch to the default block
1439 // for the switch statement if the value being switched on exceeds the largest
1440 // case in the switch.
1441 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1442 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1443 DAG.getConstant(JTH.Last-JTH.First,VT),
1444 ISD::SETUGT);
1446 // Set NextBlock to be the MBB immediately after the current one, if any.
1447 // This is used to avoid emitting unnecessary branches to the next block.
1448 MachineBasicBlock *NextBlock = 0;
1449 MachineFunction::iterator BBI = CurMBB;
1450 if (++BBI != FuncInfo.MF->end())
1451 NextBlock = BBI;
1453 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1454 MVT::Other, CopyTo, CMP,
1455 DAG.getBasicBlock(JT.Default));
1457 if (JT.MBB == NextBlock)
1458 DAG.setRoot(BrCond);
1459 else
1460 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1461 DAG.getBasicBlock(JT.MBB)));
1464 /// visitBitTestHeader - This function emits necessary code to produce value
1465 /// suitable for "bit tests"
1466 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1467 // Subtract the minimum value
1468 SDValue SwitchOp = getValue(B.SValue);
1469 EVT VT = SwitchOp.getValueType();
1470 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1471 DAG.getConstant(B.First, VT));
1473 // Check range
1474 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1475 TLI.getSetCCResultType(SUB.getValueType()),
1476 SUB, DAG.getConstant(B.Range, VT),
1477 ISD::SETUGT);
1479 SDValue ShiftOp;
1480 if (VT.bitsGT(TLI.getPointerTy()))
1481 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1482 TLI.getPointerTy(), SUB);
1483 else
1484 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1485 TLI.getPointerTy(), SUB);
1487 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1488 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1489 B.Reg, ShiftOp);
1491 // Set NextBlock to be the MBB immediately after the current one, if any.
1492 // This is used to avoid emitting unnecessary branches to the next block.
1493 MachineBasicBlock *NextBlock = 0;
1494 MachineFunction::iterator BBI = CurMBB;
1495 if (++BBI != FuncInfo.MF->end())
1496 NextBlock = BBI;
1498 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1500 CurMBB->addSuccessor(B.Default);
1501 CurMBB->addSuccessor(MBB);
1503 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1504 MVT::Other, CopyTo, RangeCmp,
1505 DAG.getBasicBlock(B.Default));
1507 if (MBB == NextBlock)
1508 DAG.setRoot(BrRange);
1509 else
1510 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1511 DAG.getBasicBlock(MBB)));
1514 /// visitBitTestCase - this function produces one "bit test"
1515 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1516 unsigned Reg,
1517 BitTestCase &B) {
1518 // Make desired shift
1519 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1520 TLI.getPointerTy());
1521 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1522 TLI.getPointerTy(),
1523 DAG.getConstant(1, TLI.getPointerTy()),
1524 ShiftOp);
1526 // Emit bit tests and jumps
1527 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1528 TLI.getPointerTy(), SwitchVal,
1529 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1530 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1531 TLI.getSetCCResultType(AndOp.getValueType()),
1532 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1533 ISD::SETNE);
1535 CurMBB->addSuccessor(B.TargetBB);
1536 CurMBB->addSuccessor(NextMBB);
1538 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1539 MVT::Other, getControlRoot(),
1540 AndCmp, DAG.getBasicBlock(B.TargetBB));
1542 // Set NextBlock to be the MBB immediately after the current one, if any.
1543 // This is used to avoid emitting unnecessary branches to the next block.
1544 MachineBasicBlock *NextBlock = 0;
1545 MachineFunction::iterator BBI = CurMBB;
1546 if (++BBI != FuncInfo.MF->end())
1547 NextBlock = BBI;
1549 if (NextMBB == NextBlock)
1550 DAG.setRoot(BrAnd);
1551 else
1552 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1553 DAG.getBasicBlock(NextMBB)));
1556 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1557 // Retrieve successors.
1558 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1559 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1561 const Value *Callee(I.getCalledValue());
1562 if (isa<InlineAsm>(Callee))
1563 visitInlineAsm(&I);
1564 else
1565 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1567 // If the value of the invoke is used outside of its defining block, make it
1568 // available as a virtual register.
1569 CopyToExportRegsIfNeeded(&I);
1571 // Update successor info
1572 CurMBB->addSuccessor(Return);
1573 CurMBB->addSuccessor(LandingPad);
1575 // Drop into normal successor.
1576 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1577 MVT::Other, getControlRoot(),
1578 DAG.getBasicBlock(Return)));
1581 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1584 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1585 /// small case ranges).
1586 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1587 CaseRecVector& WorkList,
1588 Value* SV,
1589 MachineBasicBlock* Default) {
1590 Case& BackCase = *(CR.Range.second-1);
1592 // Size is the number of Cases represented by this range.
1593 size_t Size = CR.Range.second - CR.Range.first;
1594 if (Size > 3)
1595 return false;
1597 // Get the MachineFunction which holds the current MBB. This is used when
1598 // inserting any additional MBBs necessary to represent the switch.
1599 MachineFunction *CurMF = FuncInfo.MF;
1601 // Figure out which block is immediately after the current one.
1602 MachineBasicBlock *NextBlock = 0;
1603 MachineFunction::iterator BBI = CR.CaseBB;
1605 if (++BBI != FuncInfo.MF->end())
1606 NextBlock = BBI;
1608 // TODO: If any two of the cases has the same destination, and if one value
1609 // is the same as the other, but has one bit unset that the other has set,
1610 // use bit manipulation to do two compares at once. For example:
1611 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1613 // Rearrange the case blocks so that the last one falls through if possible.
1614 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1615 // The last case block won't fall through into 'NextBlock' if we emit the
1616 // branches in this order. See if rearranging a case value would help.
1617 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1618 if (I->BB == NextBlock) {
1619 std::swap(*I, BackCase);
1620 break;
1625 // Create a CaseBlock record representing a conditional branch to
1626 // the Case's target mbb if the value being switched on SV is equal
1627 // to C.
1628 MachineBasicBlock *CurBlock = CR.CaseBB;
1629 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1630 MachineBasicBlock *FallThrough;
1631 if (I != E-1) {
1632 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1633 CurMF->insert(BBI, FallThrough);
1635 // Put SV in a virtual register to make it available from the new blocks.
1636 ExportFromCurrentBlock(SV);
1637 } else {
1638 // If the last case doesn't match, go to the default block.
1639 FallThrough = Default;
1642 Value *RHS, *LHS, *MHS;
1643 ISD::CondCode CC;
1644 if (I->High == I->Low) {
1645 // This is just small small case range :) containing exactly 1 case
1646 CC = ISD::SETEQ;
1647 LHS = SV; RHS = I->High; MHS = NULL;
1648 } else {
1649 CC = ISD::SETLE;
1650 LHS = I->Low; MHS = SV; RHS = I->High;
1652 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1654 // If emitting the first comparison, just call visitSwitchCase to emit the
1655 // code into the current block. Otherwise, push the CaseBlock onto the
1656 // vector to be later processed by SDISel, and insert the node's MBB
1657 // before the next MBB.
1658 if (CurBlock == CurMBB)
1659 visitSwitchCase(CB);
1660 else
1661 SwitchCases.push_back(CB);
1663 CurBlock = FallThrough;
1666 return true;
1669 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1670 return !DisableJumpTables &&
1671 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1672 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1675 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1676 APInt LastExt(Last), FirstExt(First);
1677 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1678 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1679 return (LastExt - FirstExt + 1ULL);
1682 /// handleJTSwitchCase - Emit jumptable for current switch case range
1683 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1684 CaseRecVector& WorkList,
1685 Value* SV,
1686 MachineBasicBlock* Default) {
1687 Case& FrontCase = *CR.Range.first;
1688 Case& BackCase = *(CR.Range.second-1);
1690 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1691 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1693 size_t TSize = 0;
1694 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1695 I!=E; ++I)
1696 TSize += I->size();
1698 if (!areJTsAllowed(TLI) || TSize <= 3)
1699 return false;
1701 APInt Range = ComputeRange(First, Last);
1702 double Density = (double)TSize / Range.roundToDouble();
1703 if (Density < 0.4)
1704 return false;
1706 DEBUG(errs() << "Lowering jump table\n"
1707 << "First entry: " << First << ". Last entry: " << Last << '\n'
1708 << "Range: " << Range
1709 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1711 // Get the MachineFunction which holds the current MBB. This is used when
1712 // inserting any additional MBBs necessary to represent the switch.
1713 MachineFunction *CurMF = FuncInfo.MF;
1715 // Figure out which block is immediately after the current one.
1716 MachineBasicBlock *NextBlock = 0;
1717 MachineFunction::iterator BBI = CR.CaseBB;
1719 if (++BBI != FuncInfo.MF->end())
1720 NextBlock = BBI;
1722 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1724 // Create a new basic block to hold the code for loading the address
1725 // of the jump table, and jumping to it. Update successor information;
1726 // we will either branch to the default case for the switch, or the jump
1727 // table.
1728 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1729 CurMF->insert(BBI, JumpTableBB);
1730 CR.CaseBB->addSuccessor(Default);
1731 CR.CaseBB->addSuccessor(JumpTableBB);
1733 // Build a vector of destination BBs, corresponding to each target
1734 // of the jump table. If the value of the jump table slot corresponds to
1735 // a case statement, push the case's BB onto the vector, otherwise, push
1736 // the default BB.
1737 std::vector<MachineBasicBlock*> DestBBs;
1738 APInt TEI = First;
1739 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1740 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1741 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1743 if (Low.sle(TEI) && TEI.sle(High)) {
1744 DestBBs.push_back(I->BB);
1745 if (TEI==High)
1746 ++I;
1747 } else {
1748 DestBBs.push_back(Default);
1752 // Update successor info. Add one edge to each unique successor.
1753 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1754 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1755 E = DestBBs.end(); I != E; ++I) {
1756 if (!SuccsHandled[(*I)->getNumber()]) {
1757 SuccsHandled[(*I)->getNumber()] = true;
1758 JumpTableBB->addSuccessor(*I);
1762 // Create a jump table index for this jump table, or return an existing
1763 // one.
1764 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1766 // Set the jump table information so that we can codegen it as a second
1767 // MachineBasicBlock
1768 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1769 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1770 if (CR.CaseBB == CurMBB)
1771 visitJumpTableHeader(JT, JTH);
1773 JTCases.push_back(JumpTableBlock(JTH, JT));
1775 return true;
1778 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1779 /// 2 subtrees.
1780 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1781 CaseRecVector& WorkList,
1782 Value* SV,
1783 MachineBasicBlock* Default) {
1784 // Get the MachineFunction which holds the current MBB. This is used when
1785 // inserting any additional MBBs necessary to represent the switch.
1786 MachineFunction *CurMF = FuncInfo.MF;
1788 // Figure out which block is immediately after the current one.
1789 MachineBasicBlock *NextBlock = 0;
1790 MachineFunction::iterator BBI = CR.CaseBB;
1792 if (++BBI != FuncInfo.MF->end())
1793 NextBlock = BBI;
1795 Case& FrontCase = *CR.Range.first;
1796 Case& BackCase = *(CR.Range.second-1);
1797 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1799 // Size is the number of Cases represented by this range.
1800 unsigned Size = CR.Range.second - CR.Range.first;
1802 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1803 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1804 double FMetric = 0;
1805 CaseItr Pivot = CR.Range.first + Size/2;
1807 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1808 // (heuristically) allow us to emit JumpTable's later.
1809 size_t TSize = 0;
1810 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1811 I!=E; ++I)
1812 TSize += I->size();
1814 size_t LSize = FrontCase.size();
1815 size_t RSize = TSize-LSize;
1816 DEBUG(errs() << "Selecting best pivot: \n"
1817 << "First: " << First << ", Last: " << Last <<'\n'
1818 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1819 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1820 J!=E; ++I, ++J) {
1821 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1822 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1823 APInt Range = ComputeRange(LEnd, RBegin);
1824 assert((Range - 2ULL).isNonNegative() &&
1825 "Invalid case distance");
1826 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1827 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1828 double Metric = Range.logBase2()*(LDensity+RDensity);
1829 // Should always split in some non-trivial place
1830 DEBUG(errs() <<"=>Step\n"
1831 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1832 << "LDensity: " << LDensity
1833 << ", RDensity: " << RDensity << '\n'
1834 << "Metric: " << Metric << '\n');
1835 if (FMetric < Metric) {
1836 Pivot = J;
1837 FMetric = Metric;
1838 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1841 LSize += J->size();
1842 RSize -= J->size();
1844 if (areJTsAllowed(TLI)) {
1845 // If our case is dense we *really* should handle it earlier!
1846 assert((FMetric > 0) && "Should handle dense range earlier!");
1847 } else {
1848 Pivot = CR.Range.first + Size/2;
1851 CaseRange LHSR(CR.Range.first, Pivot);
1852 CaseRange RHSR(Pivot, CR.Range.second);
1853 Constant *C = Pivot->Low;
1854 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1856 // We know that we branch to the LHS if the Value being switched on is
1857 // less than the Pivot value, C. We use this to optimize our binary
1858 // tree a bit, by recognizing that if SV is greater than or equal to the
1859 // LHS's Case Value, and that Case Value is exactly one less than the
1860 // Pivot's Value, then we can branch directly to the LHS's Target,
1861 // rather than creating a leaf node for it.
1862 if ((LHSR.second - LHSR.first) == 1 &&
1863 LHSR.first->High == CR.GE &&
1864 cast<ConstantInt>(C)->getValue() ==
1865 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1866 TrueBB = LHSR.first->BB;
1867 } else {
1868 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1869 CurMF->insert(BBI, TrueBB);
1870 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1872 // Put SV in a virtual register to make it available from the new blocks.
1873 ExportFromCurrentBlock(SV);
1876 // Similar to the optimization above, if the Value being switched on is
1877 // known to be less than the Constant CR.LT, and the current Case Value
1878 // is CR.LT - 1, then we can branch directly to the target block for
1879 // the current Case Value, rather than emitting a RHS leaf node for it.
1880 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1881 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1882 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1883 FalseBB = RHSR.first->BB;
1884 } else {
1885 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1886 CurMF->insert(BBI, FalseBB);
1887 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1889 // Put SV in a virtual register to make it available from the new blocks.
1890 ExportFromCurrentBlock(SV);
1893 // Create a CaseBlock record representing a conditional branch to
1894 // the LHS node if the value being switched on SV is less than C.
1895 // Otherwise, branch to LHS.
1896 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1898 if (CR.CaseBB == CurMBB)
1899 visitSwitchCase(CB);
1900 else
1901 SwitchCases.push_back(CB);
1903 return true;
1906 /// handleBitTestsSwitchCase - if current case range has few destination and
1907 /// range span less, than machine word bitwidth, encode case range into series
1908 /// of masks and emit bit tests with these masks.
1909 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1910 CaseRecVector& WorkList,
1911 Value* SV,
1912 MachineBasicBlock* Default){
1913 EVT PTy = TLI.getPointerTy();
1914 unsigned IntPtrBits = PTy.getSizeInBits();
1916 Case& FrontCase = *CR.Range.first;
1917 Case& BackCase = *(CR.Range.second-1);
1919 // Get the MachineFunction which holds the current MBB. This is used when
1920 // inserting any additional MBBs necessary to represent the switch.
1921 MachineFunction *CurMF = FuncInfo.MF;
1923 // If target does not have legal shift left, do not emit bit tests at all.
1924 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1925 return false;
1927 size_t numCmps = 0;
1928 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1929 I!=E; ++I) {
1930 // Single case counts one, case range - two.
1931 numCmps += (I->Low == I->High ? 1 : 2);
1934 // Count unique destinations
1935 SmallSet<MachineBasicBlock*, 4> Dests;
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1937 Dests.insert(I->BB);
1938 if (Dests.size() > 3)
1939 // Don't bother the code below, if there are too much unique destinations
1940 return false;
1942 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1943 << "Total number of comparisons: " << numCmps << '\n');
1945 // Compute span of values.
1946 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1947 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1948 APInt cmpRange = maxValue - minValue;
1950 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1951 << "Low bound: " << minValue << '\n'
1952 << "High bound: " << maxValue << '\n');
1954 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1955 (!(Dests.size() == 1 && numCmps >= 3) &&
1956 !(Dests.size() == 2 && numCmps >= 5) &&
1957 !(Dests.size() >= 3 && numCmps >= 6)))
1958 return false;
1960 DEBUG(errs() << "Emitting bit tests\n");
1961 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1963 // Optimize the case where all the case values fit in a
1964 // word without having to subtract minValue. In this case,
1965 // we can optimize away the subtraction.
1966 if (minValue.isNonNegative() &&
1967 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1968 cmpRange = maxValue;
1969 } else {
1970 lowBound = minValue;
1973 CaseBitsVector CasesBits;
1974 unsigned i, count = 0;
1976 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1977 MachineBasicBlock* Dest = I->BB;
1978 for (i = 0; i < count; ++i)
1979 if (Dest == CasesBits[i].BB)
1980 break;
1982 if (i == count) {
1983 assert((count < 3) && "Too much destinations to test!");
1984 CasesBits.push_back(CaseBits(0, Dest, 0));
1985 count++;
1988 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1989 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1991 uint64_t lo = (lowValue - lowBound).getZExtValue();
1992 uint64_t hi = (highValue - lowBound).getZExtValue();
1994 for (uint64_t j = lo; j <= hi; j++) {
1995 CasesBits[i].Mask |= 1ULL << j;
1996 CasesBits[i].Bits++;
2000 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2002 BitTestInfo BTC;
2004 // Figure out which block is immediately after the current one.
2005 MachineFunction::iterator BBI = CR.CaseBB;
2006 ++BBI;
2008 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2010 DEBUG(errs() << "Cases:\n");
2011 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2012 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2013 << ", Bits: " << CasesBits[i].Bits
2014 << ", BB: " << CasesBits[i].BB << '\n');
2016 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2017 CurMF->insert(BBI, CaseBB);
2018 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2019 CaseBB,
2020 CasesBits[i].BB));
2022 // Put SV in a virtual register to make it available from the new blocks.
2023 ExportFromCurrentBlock(SV);
2026 BitTestBlock BTB(lowBound, cmpRange, SV,
2027 -1U, (CR.CaseBB == CurMBB),
2028 CR.CaseBB, Default, BTC);
2030 if (CR.CaseBB == CurMBB)
2031 visitBitTestHeader(BTB);
2033 BitTestCases.push_back(BTB);
2035 return true;
2039 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2040 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2041 const SwitchInst& SI) {
2042 size_t numCmps = 0;
2044 // Start with "simple" cases
2045 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2046 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2047 Cases.push_back(Case(SI.getSuccessorValue(i),
2048 SI.getSuccessorValue(i),
2049 SMBB));
2051 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2053 // Merge case into clusters
2054 if (Cases.size() >= 2)
2055 // Must recompute end() each iteration because it may be
2056 // invalidated by erase if we hold on to it
2057 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2058 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2059 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2060 MachineBasicBlock* nextBB = J->BB;
2061 MachineBasicBlock* currentBB = I->BB;
2063 // If the two neighboring cases go to the same destination, merge them
2064 // into a single case.
2065 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2066 I->High = J->High;
2067 J = Cases.erase(J);
2068 } else {
2069 I = J++;
2073 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2074 if (I->Low != I->High)
2075 // A range counts double, since it requires two compares.
2076 ++numCmps;
2079 return numCmps;
2082 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2083 // Figure out which block is immediately after the current one.
2084 MachineBasicBlock *NextBlock = 0;
2086 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2088 // If there is only the default destination, branch to it if it is not the
2089 // next basic block. Otherwise, just fall through.
2090 if (SI.getNumOperands() == 2) {
2091 // Update machine-CFG edges.
2093 // If this is not a fall-through branch, emit the branch.
2094 CurMBB->addSuccessor(Default);
2095 if (Default != NextBlock)
2096 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2097 MVT::Other, getControlRoot(),
2098 DAG.getBasicBlock(Default)));
2099 return;
2102 // If there are any non-default case statements, create a vector of Cases
2103 // representing each one, and sort the vector so that we can efficiently
2104 // create a binary search tree from them.
2105 CaseVector Cases;
2106 size_t numCmps = Clusterify(Cases, SI);
2107 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2108 << ". Total compares: " << numCmps << '\n');
2109 numCmps = 0;
2111 // Get the Value to be switched on and default basic blocks, which will be
2112 // inserted into CaseBlock records, representing basic blocks in the binary
2113 // search tree.
2114 Value *SV = SI.getOperand(0);
2116 // Push the initial CaseRec onto the worklist
2117 CaseRecVector WorkList;
2118 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2120 while (!WorkList.empty()) {
2121 // Grab a record representing a case range to process off the worklist
2122 CaseRec CR = WorkList.back();
2123 WorkList.pop_back();
2125 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2126 continue;
2128 // If the range has few cases (two or less) emit a series of specific
2129 // tests.
2130 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2131 continue;
2133 // If the switch has more than 5 blocks, and at least 40% dense, and the
2134 // target supports indirect branches, then emit a jump table rather than
2135 // lowering the switch to a binary tree of conditional branches.
2136 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2137 continue;
2139 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2140 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2141 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2146 void SelectionDAGLowering::visitFSub(User &I) {
2147 // -0.0 - X --> fneg
2148 const Type *Ty = I.getType();
2149 if (isa<VectorType>(Ty)) {
2150 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2151 const VectorType *DestTy = cast<VectorType>(I.getType());
2152 const Type *ElTy = DestTy->getElementType();
2153 unsigned VL = DestTy->getNumElements();
2154 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2155 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2156 if (CV == CNZ) {
2157 SDValue Op2 = getValue(I.getOperand(1));
2158 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2159 Op2.getValueType(), Op2));
2160 return;
2164 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2165 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2166 SDValue Op2 = getValue(I.getOperand(1));
2167 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2168 Op2.getValueType(), Op2));
2169 return;
2172 visitBinary(I, ISD::FSUB);
2175 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2176 SDValue Op1 = getValue(I.getOperand(0));
2177 SDValue Op2 = getValue(I.getOperand(1));
2179 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2180 Op1.getValueType(), Op1, Op2));
2183 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2184 SDValue Op1 = getValue(I.getOperand(0));
2185 SDValue Op2 = getValue(I.getOperand(1));
2186 if (!isa<VectorType>(I.getType()) &&
2187 Op2.getValueType() != TLI.getShiftAmountTy()) {
2188 // If the operand is smaller than the shift count type, promote it.
2189 EVT PTy = TLI.getPointerTy();
2190 EVT STy = TLI.getShiftAmountTy();
2191 if (STy.bitsGT(Op2.getValueType()))
2192 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2193 TLI.getShiftAmountTy(), Op2);
2194 // If the operand is larger than the shift count type but the shift
2195 // count type has enough bits to represent any shift value, truncate
2196 // it now. This is a common case and it exposes the truncate to
2197 // optimization early.
2198 else if (STy.getSizeInBits() >=
2199 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2200 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2201 TLI.getShiftAmountTy(), Op2);
2202 // Otherwise we'll need to temporarily settle for some other
2203 // convenient type; type legalization will make adjustments as
2204 // needed.
2205 else if (PTy.bitsLT(Op2.getValueType()))
2206 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2207 TLI.getPointerTy(), Op2);
2208 else if (PTy.bitsGT(Op2.getValueType()))
2209 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2210 TLI.getPointerTy(), Op2);
2213 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2214 Op1.getValueType(), Op1, Op2));
2217 void SelectionDAGLowering::visitICmp(User &I) {
2218 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2219 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2220 predicate = IC->getPredicate();
2221 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2222 predicate = ICmpInst::Predicate(IC->getPredicate());
2223 SDValue Op1 = getValue(I.getOperand(0));
2224 SDValue Op2 = getValue(I.getOperand(1));
2225 ISD::CondCode Opcode = getICmpCondCode(predicate);
2227 EVT DestVT = TLI.getValueType(I.getType());
2228 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2231 void SelectionDAGLowering::visitFCmp(User &I) {
2232 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2233 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2234 predicate = FC->getPredicate();
2235 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2236 predicate = FCmpInst::Predicate(FC->getPredicate());
2237 SDValue Op1 = getValue(I.getOperand(0));
2238 SDValue Op2 = getValue(I.getOperand(1));
2239 ISD::CondCode Condition = getFCmpCondCode(predicate);
2240 EVT DestVT = TLI.getValueType(I.getType());
2241 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2244 void SelectionDAGLowering::visitSelect(User &I) {
2245 SmallVector<EVT, 4> ValueVTs;
2246 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2247 unsigned NumValues = ValueVTs.size();
2248 if (NumValues != 0) {
2249 SmallVector<SDValue, 4> Values(NumValues);
2250 SDValue Cond = getValue(I.getOperand(0));
2251 SDValue TrueVal = getValue(I.getOperand(1));
2252 SDValue FalseVal = getValue(I.getOperand(2));
2254 for (unsigned i = 0; i != NumValues; ++i)
2255 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2256 TrueVal.getValueType(), Cond,
2257 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2258 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2260 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2261 DAG.getVTList(&ValueVTs[0], NumValues),
2262 &Values[0], NumValues));
2267 void SelectionDAGLowering::visitTrunc(User &I) {
2268 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2269 SDValue N = getValue(I.getOperand(0));
2270 EVT DestVT = TLI.getValueType(I.getType());
2271 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2274 void SelectionDAGLowering::visitZExt(User &I) {
2275 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2276 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2277 SDValue N = getValue(I.getOperand(0));
2278 EVT DestVT = TLI.getValueType(I.getType());
2279 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2282 void SelectionDAGLowering::visitSExt(User &I) {
2283 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2284 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2285 SDValue N = getValue(I.getOperand(0));
2286 EVT DestVT = TLI.getValueType(I.getType());
2287 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2290 void SelectionDAGLowering::visitFPTrunc(User &I) {
2291 // FPTrunc is never a no-op cast, no need to check
2292 SDValue N = getValue(I.getOperand(0));
2293 EVT DestVT = TLI.getValueType(I.getType());
2294 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2295 DestVT, N, DAG.getIntPtrConstant(0)));
2298 void SelectionDAGLowering::visitFPExt(User &I){
2299 // FPTrunc is never a no-op cast, no need to check
2300 SDValue N = getValue(I.getOperand(0));
2301 EVT DestVT = TLI.getValueType(I.getType());
2302 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2305 void SelectionDAGLowering::visitFPToUI(User &I) {
2306 // FPToUI is never a no-op cast, no need to check
2307 SDValue N = getValue(I.getOperand(0));
2308 EVT DestVT = TLI.getValueType(I.getType());
2309 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2312 void SelectionDAGLowering::visitFPToSI(User &I) {
2313 // FPToSI is never a no-op cast, no need to check
2314 SDValue N = getValue(I.getOperand(0));
2315 EVT DestVT = TLI.getValueType(I.getType());
2316 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2319 void SelectionDAGLowering::visitUIToFP(User &I) {
2320 // UIToFP is never a no-op cast, no need to check
2321 SDValue N = getValue(I.getOperand(0));
2322 EVT DestVT = TLI.getValueType(I.getType());
2323 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2326 void SelectionDAGLowering::visitSIToFP(User &I){
2327 // SIToFP is never a no-op cast, no need to check
2328 SDValue N = getValue(I.getOperand(0));
2329 EVT DestVT = TLI.getValueType(I.getType());
2330 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2333 void SelectionDAGLowering::visitPtrToInt(User &I) {
2334 // What to do depends on the size of the integer and the size of the pointer.
2335 // We can either truncate, zero extend, or no-op, accordingly.
2336 SDValue N = getValue(I.getOperand(0));
2337 EVT SrcVT = N.getValueType();
2338 EVT DestVT = TLI.getValueType(I.getType());
2339 SDValue Result;
2340 if (DestVT.bitsLT(SrcVT))
2341 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2342 else
2343 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2344 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2345 setValue(&I, Result);
2348 void SelectionDAGLowering::visitIntToPtr(User &I) {
2349 // What to do depends on the size of the integer and the size of the pointer.
2350 // We can either truncate, zero extend, or no-op, accordingly.
2351 SDValue N = getValue(I.getOperand(0));
2352 EVT SrcVT = N.getValueType();
2353 EVT DestVT = TLI.getValueType(I.getType());
2354 if (DestVT.bitsLT(SrcVT))
2355 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2356 else
2357 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2358 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2359 DestVT, N));
2362 void SelectionDAGLowering::visitBitCast(User &I) {
2363 SDValue N = getValue(I.getOperand(0));
2364 EVT DestVT = TLI.getValueType(I.getType());
2366 // BitCast assures us that source and destination are the same size so this
2367 // is either a BIT_CONVERT or a no-op.
2368 if (DestVT != N.getValueType())
2369 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2370 DestVT, N)); // convert types
2371 else
2372 setValue(&I, N); // noop cast.
2375 void SelectionDAGLowering::visitInsertElement(User &I) {
2376 SDValue InVec = getValue(I.getOperand(0));
2377 SDValue InVal = getValue(I.getOperand(1));
2378 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2379 TLI.getPointerTy(),
2380 getValue(I.getOperand(2)));
2382 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2383 TLI.getValueType(I.getType()),
2384 InVec, InVal, InIdx));
2387 void SelectionDAGLowering::visitExtractElement(User &I) {
2388 SDValue InVec = getValue(I.getOperand(0));
2389 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2390 TLI.getPointerTy(),
2391 getValue(I.getOperand(1)));
2392 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2393 TLI.getValueType(I.getType()), InVec, InIdx));
2397 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2398 // from SIndx and increasing to the element length (undefs are allowed).
2399 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2400 unsigned MaskNumElts = Mask.size();
2401 for (unsigned i = 0; i != MaskNumElts; ++i)
2402 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2403 return false;
2404 return true;
2407 void SelectionDAGLowering::visitShuffleVector(User &I) {
2408 SmallVector<int, 8> Mask;
2409 SDValue Src1 = getValue(I.getOperand(0));
2410 SDValue Src2 = getValue(I.getOperand(1));
2412 // Convert the ConstantVector mask operand into an array of ints, with -1
2413 // representing undef values.
2414 SmallVector<Constant*, 8> MaskElts;
2415 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2416 MaskElts);
2417 unsigned MaskNumElts = MaskElts.size();
2418 for (unsigned i = 0; i != MaskNumElts; ++i) {
2419 if (isa<UndefValue>(MaskElts[i]))
2420 Mask.push_back(-1);
2421 else
2422 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2425 EVT VT = TLI.getValueType(I.getType());
2426 EVT SrcVT = Src1.getValueType();
2427 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2429 if (SrcNumElts == MaskNumElts) {
2430 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2431 &Mask[0]));
2432 return;
2435 // Normalize the shuffle vector since mask and vector length don't match.
2436 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2437 // Mask is longer than the source vectors and is a multiple of the source
2438 // vectors. We can use concatenate vector to make the mask and vectors
2439 // lengths match.
2440 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2441 // The shuffle is concatenating two vectors together.
2442 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2443 VT, Src1, Src2));
2444 return;
2447 // Pad both vectors with undefs to make them the same length as the mask.
2448 unsigned NumConcat = MaskNumElts / SrcNumElts;
2449 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2450 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2451 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2453 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2454 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2455 MOps1[0] = Src1;
2456 MOps2[0] = Src2;
2458 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2459 getCurDebugLoc(), VT,
2460 &MOps1[0], NumConcat);
2461 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2462 getCurDebugLoc(), VT,
2463 &MOps2[0], NumConcat);
2465 // Readjust mask for new input vector length.
2466 SmallVector<int, 8> MappedOps;
2467 for (unsigned i = 0; i != MaskNumElts; ++i) {
2468 int Idx = Mask[i];
2469 if (Idx < (int)SrcNumElts)
2470 MappedOps.push_back(Idx);
2471 else
2472 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2474 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2475 &MappedOps[0]));
2476 return;
2479 if (SrcNumElts > MaskNumElts) {
2480 // Analyze the access pattern of the vector to see if we can extract
2481 // two subvectors and do the shuffle. The analysis is done by calculating
2482 // the range of elements the mask access on both vectors.
2483 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2484 int MaxRange[2] = {-1, -1};
2486 for (unsigned i = 0; i != MaskNumElts; ++i) {
2487 int Idx = Mask[i];
2488 int Input = 0;
2489 if (Idx < 0)
2490 continue;
2492 if (Idx >= (int)SrcNumElts) {
2493 Input = 1;
2494 Idx -= SrcNumElts;
2496 if (Idx > MaxRange[Input])
2497 MaxRange[Input] = Idx;
2498 if (Idx < MinRange[Input])
2499 MinRange[Input] = Idx;
2502 // Check if the access is smaller than the vector size and can we find
2503 // a reasonable extract index.
2504 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2505 int StartIdx[2]; // StartIdx to extract from
2506 for (int Input=0; Input < 2; ++Input) {
2507 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2508 RangeUse[Input] = 0; // Unused
2509 StartIdx[Input] = 0;
2510 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2511 // Fits within range but we should see if we can find a good
2512 // start index that is a multiple of the mask length.
2513 if (MaxRange[Input] < (int)MaskNumElts) {
2514 RangeUse[Input] = 1; // Extract from beginning of the vector
2515 StartIdx[Input] = 0;
2516 } else {
2517 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2518 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2519 StartIdx[Input] + MaskNumElts < SrcNumElts)
2520 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2525 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2526 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2527 return;
2529 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2530 // Extract appropriate subvector and generate a vector shuffle
2531 for (int Input=0; Input < 2; ++Input) {
2532 SDValue& Src = Input == 0 ? Src1 : Src2;
2533 if (RangeUse[Input] == 0) {
2534 Src = DAG.getUNDEF(VT);
2535 } else {
2536 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2537 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2540 // Calculate new mask.
2541 SmallVector<int, 8> MappedOps;
2542 for (unsigned i = 0; i != MaskNumElts; ++i) {
2543 int Idx = Mask[i];
2544 if (Idx < 0)
2545 MappedOps.push_back(Idx);
2546 else if (Idx < (int)SrcNumElts)
2547 MappedOps.push_back(Idx - StartIdx[0]);
2548 else
2549 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2551 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2552 &MappedOps[0]));
2553 return;
2557 // We can't use either concat vectors or extract subvectors so fall back to
2558 // replacing the shuffle with extract and build vector.
2559 // to insert and build vector.
2560 EVT EltVT = VT.getVectorElementType();
2561 EVT PtrVT = TLI.getPointerTy();
2562 SmallVector<SDValue,8> Ops;
2563 for (unsigned i = 0; i != MaskNumElts; ++i) {
2564 if (Mask[i] < 0) {
2565 Ops.push_back(DAG.getUNDEF(EltVT));
2566 } else {
2567 int Idx = Mask[i];
2568 if (Idx < (int)SrcNumElts)
2569 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2570 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2571 else
2572 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2573 EltVT, Src2,
2574 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2577 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2578 VT, &Ops[0], Ops.size()));
2581 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2582 const Value *Op0 = I.getOperand(0);
2583 const Value *Op1 = I.getOperand(1);
2584 const Type *AggTy = I.getType();
2585 const Type *ValTy = Op1->getType();
2586 bool IntoUndef = isa<UndefValue>(Op0);
2587 bool FromUndef = isa<UndefValue>(Op1);
2589 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2590 I.idx_begin(), I.idx_end());
2592 SmallVector<EVT, 4> AggValueVTs;
2593 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2594 SmallVector<EVT, 4> ValValueVTs;
2595 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2597 unsigned NumAggValues = AggValueVTs.size();
2598 unsigned NumValValues = ValValueVTs.size();
2599 SmallVector<SDValue, 4> Values(NumAggValues);
2601 SDValue Agg = getValue(Op0);
2602 SDValue Val = getValue(Op1);
2603 unsigned i = 0;
2604 // Copy the beginning value(s) from the original aggregate.
2605 for (; i != LinearIndex; ++i)
2606 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2607 SDValue(Agg.getNode(), Agg.getResNo() + i);
2608 // Copy values from the inserted value(s).
2609 for (; i != LinearIndex + NumValValues; ++i)
2610 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2611 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2612 // Copy remaining value(s) from the original aggregate.
2613 for (; i != NumAggValues; ++i)
2614 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2615 SDValue(Agg.getNode(), Agg.getResNo() + i);
2617 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2618 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2619 &Values[0], NumAggValues));
2622 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2623 const Value *Op0 = I.getOperand(0);
2624 const Type *AggTy = Op0->getType();
2625 const Type *ValTy = I.getType();
2626 bool OutOfUndef = isa<UndefValue>(Op0);
2628 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2629 I.idx_begin(), I.idx_end());
2631 SmallVector<EVT, 4> ValValueVTs;
2632 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2634 unsigned NumValValues = ValValueVTs.size();
2635 SmallVector<SDValue, 4> Values(NumValValues);
2637 SDValue Agg = getValue(Op0);
2638 // Copy out the selected value(s).
2639 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2640 Values[i - LinearIndex] =
2641 OutOfUndef ?
2642 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2643 SDValue(Agg.getNode(), Agg.getResNo() + i);
2645 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2646 DAG.getVTList(&ValValueVTs[0], NumValValues),
2647 &Values[0], NumValValues));
2651 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2652 SDValue N = getValue(I.getOperand(0));
2653 const Type *Ty = I.getOperand(0)->getType();
2655 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2656 OI != E; ++OI) {
2657 Value *Idx = *OI;
2658 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2659 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2660 if (Field) {
2661 // N = N + Offset
2662 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2663 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2664 DAG.getIntPtrConstant(Offset));
2666 Ty = StTy->getElementType(Field);
2667 } else {
2668 Ty = cast<SequentialType>(Ty)->getElementType();
2670 // If this is a constant subscript, handle it quickly.
2671 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2672 if (CI->getZExtValue() == 0) continue;
2673 uint64_t Offs =
2674 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2675 SDValue OffsVal;
2676 EVT PTy = TLI.getPointerTy();
2677 unsigned PtrBits = PTy.getSizeInBits();
2678 if (PtrBits < 64) {
2679 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2680 TLI.getPointerTy(),
2681 DAG.getConstant(Offs, MVT::i64));
2682 } else
2683 OffsVal = DAG.getIntPtrConstant(Offs);
2684 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2685 OffsVal);
2686 continue;
2689 // N = N + Idx * ElementSize;
2690 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2691 SDValue IdxN = getValue(Idx);
2693 // If the index is smaller or larger than intptr_t, truncate or extend
2694 // it.
2695 if (IdxN.getValueType().bitsLT(N.getValueType()))
2696 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2697 N.getValueType(), IdxN);
2698 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2699 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2700 N.getValueType(), IdxN);
2702 // If this is a multiply by a power of two, turn it into a shl
2703 // immediately. This is a very common case.
2704 if (ElementSize != 1) {
2705 if (isPowerOf2_64(ElementSize)) {
2706 unsigned Amt = Log2_64(ElementSize);
2707 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2708 N.getValueType(), IdxN,
2709 DAG.getConstant(Amt, TLI.getPointerTy()));
2710 } else {
2711 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2712 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2713 N.getValueType(), IdxN, Scale);
2717 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2718 N.getValueType(), N, IdxN);
2721 setValue(&I, N);
2724 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2725 // If this is a fixed sized alloca in the entry block of the function,
2726 // allocate it statically on the stack.
2727 if (FuncInfo.StaticAllocaMap.count(&I))
2728 return; // getValue will auto-populate this.
2730 const Type *Ty = I.getAllocatedType();
2731 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2732 unsigned Align =
2733 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2734 I.getAlignment());
2736 SDValue AllocSize = getValue(I.getArraySize());
2738 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2739 AllocSize,
2740 DAG.getConstant(TySize, AllocSize.getValueType()));
2744 EVT IntPtr = TLI.getPointerTy();
2745 if (IntPtr.bitsLT(AllocSize.getValueType()))
2746 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2747 IntPtr, AllocSize);
2748 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2749 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2750 IntPtr, AllocSize);
2752 // Handle alignment. If the requested alignment is less than or equal to
2753 // the stack alignment, ignore it. If the size is greater than or equal to
2754 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2755 unsigned StackAlign =
2756 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2757 if (Align <= StackAlign)
2758 Align = 0;
2760 // Round the size of the allocation up to the stack alignment size
2761 // by add SA-1 to the size.
2762 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2763 AllocSize.getValueType(), AllocSize,
2764 DAG.getIntPtrConstant(StackAlign-1));
2765 // Mask out the low bits for alignment purposes.
2766 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2767 AllocSize.getValueType(), AllocSize,
2768 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2770 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2771 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2772 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2773 VTs, Ops, 3);
2774 setValue(&I, DSA);
2775 DAG.setRoot(DSA.getValue(1));
2777 // Inform the Frame Information that we have just allocated a variable-sized
2778 // object.
2779 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2782 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2783 const Value *SV = I.getOperand(0);
2784 SDValue Ptr = getValue(SV);
2786 const Type *Ty = I.getType();
2787 bool isVolatile = I.isVolatile();
2788 unsigned Alignment = I.getAlignment();
2790 SmallVector<EVT, 4> ValueVTs;
2791 SmallVector<uint64_t, 4> Offsets;
2792 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2793 unsigned NumValues = ValueVTs.size();
2794 if (NumValues == 0)
2795 return;
2797 SDValue Root;
2798 bool ConstantMemory = false;
2799 if (I.isVolatile())
2800 // Serialize volatile loads with other side effects.
2801 Root = getRoot();
2802 else if (AA->pointsToConstantMemory(SV)) {
2803 // Do not serialize (non-volatile) loads of constant memory with anything.
2804 Root = DAG.getEntryNode();
2805 ConstantMemory = true;
2806 } else {
2807 // Do not serialize non-volatile loads against each other.
2808 Root = DAG.getRoot();
2811 SmallVector<SDValue, 4> Values(NumValues);
2812 SmallVector<SDValue, 4> Chains(NumValues);
2813 EVT PtrVT = Ptr.getValueType();
2814 for (unsigned i = 0; i != NumValues; ++i) {
2815 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2816 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2817 PtrVT, Ptr,
2818 DAG.getConstant(Offsets[i], PtrVT)),
2819 SV, Offsets[i],
2820 isVolatile, Alignment);
2821 Values[i] = L;
2822 Chains[i] = L.getValue(1);
2825 if (!ConstantMemory) {
2826 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2827 MVT::Other,
2828 &Chains[0], NumValues);
2829 if (isVolatile)
2830 DAG.setRoot(Chain);
2831 else
2832 PendingLoads.push_back(Chain);
2835 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2836 DAG.getVTList(&ValueVTs[0], NumValues),
2837 &Values[0], NumValues));
2841 void SelectionDAGLowering::visitStore(StoreInst &I) {
2842 Value *SrcV = I.getOperand(0);
2843 Value *PtrV = I.getOperand(1);
2845 SmallVector<EVT, 4> ValueVTs;
2846 SmallVector<uint64_t, 4> Offsets;
2847 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2848 unsigned NumValues = ValueVTs.size();
2849 if (NumValues == 0)
2850 return;
2852 // Get the lowered operands. Note that we do this after
2853 // checking if NumResults is zero, because with zero results
2854 // the operands won't have values in the map.
2855 SDValue Src = getValue(SrcV);
2856 SDValue Ptr = getValue(PtrV);
2858 SDValue Root = getRoot();
2859 SmallVector<SDValue, 4> Chains(NumValues);
2860 EVT PtrVT = Ptr.getValueType();
2861 bool isVolatile = I.isVolatile();
2862 unsigned Alignment = I.getAlignment();
2863 for (unsigned i = 0; i != NumValues; ++i)
2864 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2865 SDValue(Src.getNode(), Src.getResNo() + i),
2866 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2867 PtrVT, Ptr,
2868 DAG.getConstant(Offsets[i], PtrVT)),
2869 PtrV, Offsets[i],
2870 isVolatile, Alignment);
2872 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2873 MVT::Other, &Chains[0], NumValues));
2876 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2877 /// node.
2878 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2879 unsigned Intrinsic) {
2880 bool HasChain = !I.doesNotAccessMemory();
2881 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2883 // Build the operand list.
2884 SmallVector<SDValue, 8> Ops;
2885 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2886 if (OnlyLoad) {
2887 // We don't need to serialize loads against other loads.
2888 Ops.push_back(DAG.getRoot());
2889 } else {
2890 Ops.push_back(getRoot());
2894 // Info is set by getTgtMemInstrinsic
2895 TargetLowering::IntrinsicInfo Info;
2896 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2898 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2899 if (!IsTgtIntrinsic)
2900 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2902 // Add all operands of the call to the operand list.
2903 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2904 SDValue Op = getValue(I.getOperand(i));
2905 assert(TLI.isTypeLegal(Op.getValueType()) &&
2906 "Intrinsic uses a non-legal type?");
2907 Ops.push_back(Op);
2910 SmallVector<EVT, 4> ValueVTs;
2911 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2912 #ifndef NDEBUG
2913 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2914 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2915 "Intrinsic uses a non-legal type?");
2917 #endif // NDEBUG
2918 if (HasChain)
2919 ValueVTs.push_back(MVT::Other);
2921 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2923 // Create the node.
2924 SDValue Result;
2925 if (IsTgtIntrinsic) {
2926 // This is target intrinsic that touches memory
2927 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2928 VTs, &Ops[0], Ops.size(),
2929 Info.memVT, Info.ptrVal, Info.offset,
2930 Info.align, Info.vol,
2931 Info.readMem, Info.writeMem);
2933 else if (!HasChain)
2934 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2935 VTs, &Ops[0], Ops.size());
2936 else if (I.getType() != Type::getVoidTy(*DAG.getContext()))
2937 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2938 VTs, &Ops[0], Ops.size());
2939 else
2940 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2941 VTs, &Ops[0], Ops.size());
2943 if (HasChain) {
2944 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2945 if (OnlyLoad)
2946 PendingLoads.push_back(Chain);
2947 else
2948 DAG.setRoot(Chain);
2950 if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
2951 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2952 EVT VT = TLI.getValueType(PTy);
2953 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2955 setValue(&I, Result);
2959 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2960 static GlobalVariable *ExtractTypeInfo(Value *V) {
2961 V = V->stripPointerCasts();
2962 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2963 assert ((GV || isa<ConstantPointerNull>(V)) &&
2964 "TypeInfo must be a global variable or NULL");
2965 return GV;
2968 namespace llvm {
2970 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2971 /// call, and add them to the specified machine basic block.
2972 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2973 MachineBasicBlock *MBB) {
2974 // Inform the MachineModuleInfo of the personality for this landing pad.
2975 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2976 assert(CE->getOpcode() == Instruction::BitCast &&
2977 isa<Function>(CE->getOperand(0)) &&
2978 "Personality should be a function");
2979 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2981 // Gather all the type infos for this landing pad and pass them along to
2982 // MachineModuleInfo.
2983 std::vector<GlobalVariable *> TyInfo;
2984 unsigned N = I.getNumOperands();
2986 for (unsigned i = N - 1; i > 2; --i) {
2987 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2988 unsigned FilterLength = CI->getZExtValue();
2989 unsigned FirstCatch = i + FilterLength + !FilterLength;
2990 assert (FirstCatch <= N && "Invalid filter length");
2992 if (FirstCatch < N) {
2993 TyInfo.reserve(N - FirstCatch);
2994 for (unsigned j = FirstCatch; j < N; ++j)
2995 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2996 MMI->addCatchTypeInfo(MBB, TyInfo);
2997 TyInfo.clear();
3000 if (!FilterLength) {
3001 // Cleanup.
3002 MMI->addCleanup(MBB);
3003 } else {
3004 // Filter.
3005 TyInfo.reserve(FilterLength - 1);
3006 for (unsigned j = i + 1; j < FirstCatch; ++j)
3007 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3008 MMI->addFilterTypeInfo(MBB, TyInfo);
3009 TyInfo.clear();
3012 N = i;
3016 if (N > 3) {
3017 TyInfo.reserve(N - 3);
3018 for (unsigned j = 3; j < N; ++j)
3019 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3020 MMI->addCatchTypeInfo(MBB, TyInfo);
3026 /// GetSignificand - Get the significand and build it into a floating-point
3027 /// number with exponent of 1:
3029 /// Op = (Op & 0x007fffff) | 0x3f800000;
3031 /// where Op is the hexidecimal representation of floating point value.
3032 static SDValue
3033 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3034 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3035 DAG.getConstant(0x007fffff, MVT::i32));
3036 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3037 DAG.getConstant(0x3f800000, MVT::i32));
3038 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3041 /// GetExponent - Get the exponent:
3043 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3045 /// where Op is the hexidecimal representation of floating point value.
3046 static SDValue
3047 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3048 DebugLoc dl) {
3049 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3050 DAG.getConstant(0x7f800000, MVT::i32));
3051 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3052 DAG.getConstant(23, TLI.getPointerTy()));
3053 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3054 DAG.getConstant(127, MVT::i32));
3055 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3058 /// getF32Constant - Get 32-bit floating point constant.
3059 static SDValue
3060 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3061 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3064 /// Inlined utility function to implement binary input atomic intrinsics for
3065 /// visitIntrinsicCall: I is a call instruction
3066 /// Op is the associated NodeType for I
3067 const char *
3068 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3069 SDValue Root = getRoot();
3070 SDValue L =
3071 DAG.getAtomic(Op, getCurDebugLoc(),
3072 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3073 Root,
3074 getValue(I.getOperand(1)),
3075 getValue(I.getOperand(2)),
3076 I.getOperand(1));
3077 setValue(&I, L);
3078 DAG.setRoot(L.getValue(1));
3079 return 0;
3082 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3083 const char *
3084 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3085 SDValue Op1 = getValue(I.getOperand(1));
3086 SDValue Op2 = getValue(I.getOperand(2));
3088 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3089 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3091 setValue(&I, Result);
3092 return 0;
3095 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3096 /// limited-precision mode.
3097 void
3098 SelectionDAGLowering::visitExp(CallInst &I) {
3099 SDValue result;
3100 DebugLoc dl = getCurDebugLoc();
3102 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3103 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3104 SDValue Op = getValue(I.getOperand(1));
3106 // Put the exponent in the right bit position for later addition to the
3107 // final result:
3109 // #define LOG2OFe 1.4426950f
3110 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3112 getF32Constant(DAG, 0x3fb8aa3b));
3113 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3115 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3116 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3117 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3119 // IntegerPartOfX <<= 23;
3120 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3121 DAG.getConstant(23, TLI.getPointerTy()));
3123 if (LimitFloatPrecision <= 6) {
3124 // For floating-point precision of 6:
3126 // TwoToFractionalPartOfX =
3127 // 0.997535578f +
3128 // (0.735607626f + 0.252464424f * x) * x;
3130 // error 0.0144103317, which is 6 bits
3131 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3132 getF32Constant(DAG, 0x3e814304));
3133 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3134 getF32Constant(DAG, 0x3f3c50c8));
3135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3137 getF32Constant(DAG, 0x3f7f5e7e));
3138 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3140 // Add the exponent into the result in integer domain.
3141 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3142 TwoToFracPartOfX, IntegerPartOfX);
3144 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3145 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3146 // For floating-point precision of 12:
3148 // TwoToFractionalPartOfX =
3149 // 0.999892986f +
3150 // (0.696457318f +
3151 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3153 // 0.000107046256 error, which is 13 to 14 bits
3154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3155 getF32Constant(DAG, 0x3da235e3));
3156 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3157 getF32Constant(DAG, 0x3e65b8f3));
3158 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3159 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3160 getF32Constant(DAG, 0x3f324b07));
3161 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3162 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3163 getF32Constant(DAG, 0x3f7ff8fd));
3164 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3166 // Add the exponent into the result in integer domain.
3167 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3168 TwoToFracPartOfX, IntegerPartOfX);
3170 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3171 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3172 // For floating-point precision of 18:
3174 // TwoToFractionalPartOfX =
3175 // 0.999999982f +
3176 // (0.693148872f +
3177 // (0.240227044f +
3178 // (0.554906021e-1f +
3179 // (0.961591928e-2f +
3180 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3182 // error 2.47208000*10^(-7), which is better than 18 bits
3183 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3184 getF32Constant(DAG, 0x3924b03e));
3185 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3186 getF32Constant(DAG, 0x3ab24b87));
3187 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3188 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3189 getF32Constant(DAG, 0x3c1d8c17));
3190 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3191 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3192 getF32Constant(DAG, 0x3d634a1d));
3193 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3194 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3195 getF32Constant(DAG, 0x3e75fe14));
3196 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3197 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3198 getF32Constant(DAG, 0x3f317234));
3199 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3200 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3201 getF32Constant(DAG, 0x3f800000));
3202 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3203 MVT::i32, t13);
3205 // Add the exponent into the result in integer domain.
3206 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3207 TwoToFracPartOfX, IntegerPartOfX);
3209 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3211 } else {
3212 // No special expansion.
3213 result = DAG.getNode(ISD::FEXP, dl,
3214 getValue(I.getOperand(1)).getValueType(),
3215 getValue(I.getOperand(1)));
3218 setValue(&I, result);
3221 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3222 /// limited-precision mode.
3223 void
3224 SelectionDAGLowering::visitLog(CallInst &I) {
3225 SDValue result;
3226 DebugLoc dl = getCurDebugLoc();
3228 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3229 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3230 SDValue Op = getValue(I.getOperand(1));
3231 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3233 // Scale the exponent by log(2) [0.69314718f].
3234 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3235 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3236 getF32Constant(DAG, 0x3f317218));
3238 // Get the significand and build it into a floating-point number with
3239 // exponent of 1.
3240 SDValue X = GetSignificand(DAG, Op1, dl);
3242 if (LimitFloatPrecision <= 6) {
3243 // For floating-point precision of 6:
3245 // LogofMantissa =
3246 // -1.1609546f +
3247 // (1.4034025f - 0.23903021f * x) * x;
3249 // error 0.0034276066, which is better than 8 bits
3250 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3251 getF32Constant(DAG, 0xbe74c456));
3252 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3253 getF32Constant(DAG, 0x3fb3a2b1));
3254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3255 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3256 getF32Constant(DAG, 0x3f949a29));
3258 result = DAG.getNode(ISD::FADD, dl,
3259 MVT::f32, LogOfExponent, LogOfMantissa);
3260 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3261 // For floating-point precision of 12:
3263 // LogOfMantissa =
3264 // -1.7417939f +
3265 // (2.8212026f +
3266 // (-1.4699568f +
3267 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3269 // error 0.000061011436, which is 14 bits
3270 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3271 getF32Constant(DAG, 0xbd67b6d6));
3272 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3273 getF32Constant(DAG, 0x3ee4f4b8));
3274 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3275 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3276 getF32Constant(DAG, 0x3fbc278b));
3277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3278 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3279 getF32Constant(DAG, 0x40348e95));
3280 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3281 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3282 getF32Constant(DAG, 0x3fdef31a));
3284 result = DAG.getNode(ISD::FADD, dl,
3285 MVT::f32, LogOfExponent, LogOfMantissa);
3286 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3287 // For floating-point precision of 18:
3289 // LogOfMantissa =
3290 // -2.1072184f +
3291 // (4.2372794f +
3292 // (-3.7029485f +
3293 // (2.2781945f +
3294 // (-0.87823314f +
3295 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3297 // error 0.0000023660568, which is better than 18 bits
3298 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3299 getF32Constant(DAG, 0xbc91e5ac));
3300 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3301 getF32Constant(DAG, 0x3e4350aa));
3302 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3303 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3304 getF32Constant(DAG, 0x3f60d3e3));
3305 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3306 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3307 getF32Constant(DAG, 0x4011cdf0));
3308 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3309 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3310 getF32Constant(DAG, 0x406cfd1c));
3311 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3312 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3313 getF32Constant(DAG, 0x408797cb));
3314 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3315 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3316 getF32Constant(DAG, 0x4006dcab));
3318 result = DAG.getNode(ISD::FADD, dl,
3319 MVT::f32, LogOfExponent, LogOfMantissa);
3321 } else {
3322 // No special expansion.
3323 result = DAG.getNode(ISD::FLOG, dl,
3324 getValue(I.getOperand(1)).getValueType(),
3325 getValue(I.getOperand(1)));
3328 setValue(&I, result);
3331 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3332 /// limited-precision mode.
3333 void
3334 SelectionDAGLowering::visitLog2(CallInst &I) {
3335 SDValue result;
3336 DebugLoc dl = getCurDebugLoc();
3338 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3339 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3340 SDValue Op = getValue(I.getOperand(1));
3341 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3343 // Get the exponent.
3344 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3346 // Get the significand and build it into a floating-point number with
3347 // exponent of 1.
3348 SDValue X = GetSignificand(DAG, Op1, dl);
3350 // Different possible minimax approximations of significand in
3351 // floating-point for various degrees of accuracy over [1,2].
3352 if (LimitFloatPrecision <= 6) {
3353 // For floating-point precision of 6:
3355 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3357 // error 0.0049451742, which is more than 7 bits
3358 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3359 getF32Constant(DAG, 0xbeb08fe0));
3360 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3361 getF32Constant(DAG, 0x40019463));
3362 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3363 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3364 getF32Constant(DAG, 0x3fd6633d));
3366 result = DAG.getNode(ISD::FADD, dl,
3367 MVT::f32, LogOfExponent, Log2ofMantissa);
3368 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3369 // For floating-point precision of 12:
3371 // Log2ofMantissa =
3372 // -2.51285454f +
3373 // (4.07009056f +
3374 // (-2.12067489f +
3375 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3377 // error 0.0000876136000, which is better than 13 bits
3378 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3379 getF32Constant(DAG, 0xbda7262e));
3380 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3381 getF32Constant(DAG, 0x3f25280b));
3382 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3383 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3384 getF32Constant(DAG, 0x4007b923));
3385 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3386 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3387 getF32Constant(DAG, 0x40823e2f));
3388 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3389 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3390 getF32Constant(DAG, 0x4020d29c));
3392 result = DAG.getNode(ISD::FADD, dl,
3393 MVT::f32, LogOfExponent, Log2ofMantissa);
3394 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3395 // For floating-point precision of 18:
3397 // Log2ofMantissa =
3398 // -3.0400495f +
3399 // (6.1129976f +
3400 // (-5.3420409f +
3401 // (3.2865683f +
3402 // (-1.2669343f +
3403 // (0.27515199f -
3404 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3406 // error 0.0000018516, which is better than 18 bits
3407 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3408 getF32Constant(DAG, 0xbcd2769e));
3409 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3410 getF32Constant(DAG, 0x3e8ce0b9));
3411 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3412 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3413 getF32Constant(DAG, 0x3fa22ae7));
3414 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3415 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3416 getF32Constant(DAG, 0x40525723));
3417 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3418 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3419 getF32Constant(DAG, 0x40aaf200));
3420 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3421 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3422 getF32Constant(DAG, 0x40c39dad));
3423 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3424 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3425 getF32Constant(DAG, 0x4042902c));
3427 result = DAG.getNode(ISD::FADD, dl,
3428 MVT::f32, LogOfExponent, Log2ofMantissa);
3430 } else {
3431 // No special expansion.
3432 result = DAG.getNode(ISD::FLOG2, dl,
3433 getValue(I.getOperand(1)).getValueType(),
3434 getValue(I.getOperand(1)));
3437 setValue(&I, result);
3440 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3441 /// limited-precision mode.
3442 void
3443 SelectionDAGLowering::visitLog10(CallInst &I) {
3444 SDValue result;
3445 DebugLoc dl = getCurDebugLoc();
3447 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3448 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3449 SDValue Op = getValue(I.getOperand(1));
3450 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3452 // Scale the exponent by log10(2) [0.30102999f].
3453 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3454 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3455 getF32Constant(DAG, 0x3e9a209a));
3457 // Get the significand and build it into a floating-point number with
3458 // exponent of 1.
3459 SDValue X = GetSignificand(DAG, Op1, dl);
3461 if (LimitFloatPrecision <= 6) {
3462 // For floating-point precision of 6:
3464 // Log10ofMantissa =
3465 // -0.50419619f +
3466 // (0.60948995f - 0.10380950f * x) * x;
3468 // error 0.0014886165, which is 6 bits
3469 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3470 getF32Constant(DAG, 0xbdd49a13));
3471 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3472 getF32Constant(DAG, 0x3f1c0789));
3473 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3474 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3475 getF32Constant(DAG, 0x3f011300));
3477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, Log10ofMantissa);
3479 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3480 // For floating-point precision of 12:
3482 // Log10ofMantissa =
3483 // -0.64831180f +
3484 // (0.91751397f +
3485 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3487 // error 0.00019228036, which is better than 12 bits
3488 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3489 getF32Constant(DAG, 0x3d431f31));
3490 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3491 getF32Constant(DAG, 0x3ea21fb2));
3492 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3493 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3494 getF32Constant(DAG, 0x3f6ae232));
3495 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3496 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3497 getF32Constant(DAG, 0x3f25f7c3));
3499 result = DAG.getNode(ISD::FADD, dl,
3500 MVT::f32, LogOfExponent, Log10ofMantissa);
3501 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3502 // For floating-point precision of 18:
3504 // Log10ofMantissa =
3505 // -0.84299375f +
3506 // (1.5327582f +
3507 // (-1.0688956f +
3508 // (0.49102474f +
3509 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3511 // error 0.0000037995730, which is better than 18 bits
3512 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3513 getF32Constant(DAG, 0x3c5d51ce));
3514 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3515 getF32Constant(DAG, 0x3e00685a));
3516 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3517 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3518 getF32Constant(DAG, 0x3efb6798));
3519 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3520 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3521 getF32Constant(DAG, 0x3f88d192));
3522 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3523 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3524 getF32Constant(DAG, 0x3fc4316c));
3525 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3526 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3527 getF32Constant(DAG, 0x3f57ce70));
3529 result = DAG.getNode(ISD::FADD, dl,
3530 MVT::f32, LogOfExponent, Log10ofMantissa);
3532 } else {
3533 // No special expansion.
3534 result = DAG.getNode(ISD::FLOG10, dl,
3535 getValue(I.getOperand(1)).getValueType(),
3536 getValue(I.getOperand(1)));
3539 setValue(&I, result);
3542 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3543 /// limited-precision mode.
3544 void
3545 SelectionDAGLowering::visitExp2(CallInst &I) {
3546 SDValue result;
3547 DebugLoc dl = getCurDebugLoc();
3549 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3550 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3551 SDValue Op = getValue(I.getOperand(1));
3553 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3555 // FractionalPartOfX = x - (float)IntegerPartOfX;
3556 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3557 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3559 // IntegerPartOfX <<= 23;
3560 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3561 DAG.getConstant(23, TLI.getPointerTy()));
3563 if (LimitFloatPrecision <= 6) {
3564 // For floating-point precision of 6:
3566 // TwoToFractionalPartOfX =
3567 // 0.997535578f +
3568 // (0.735607626f + 0.252464424f * x) * x;
3570 // error 0.0144103317, which is 6 bits
3571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0x3e814304));
3573 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3574 getF32Constant(DAG, 0x3f3c50c8));
3575 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3576 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3577 getF32Constant(DAG, 0x3f7f5e7e));
3578 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3579 SDValue TwoToFractionalPartOfX =
3580 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3582 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3583 MVT::f32, TwoToFractionalPartOfX);
3584 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3585 // For floating-point precision of 12:
3587 // TwoToFractionalPartOfX =
3588 // 0.999892986f +
3589 // (0.696457318f +
3590 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3592 // error 0.000107046256, which is 13 to 14 bits
3593 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3594 getF32Constant(DAG, 0x3da235e3));
3595 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3596 getF32Constant(DAG, 0x3e65b8f3));
3597 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3598 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3599 getF32Constant(DAG, 0x3f324b07));
3600 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3601 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3602 getF32Constant(DAG, 0x3f7ff8fd));
3603 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3604 SDValue TwoToFractionalPartOfX =
3605 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3607 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3608 MVT::f32, TwoToFractionalPartOfX);
3609 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3610 // For floating-point precision of 18:
3612 // TwoToFractionalPartOfX =
3613 // 0.999999982f +
3614 // (0.693148872f +
3615 // (0.240227044f +
3616 // (0.554906021e-1f +
3617 // (0.961591928e-2f +
3618 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3619 // error 2.47208000*10^(-7), which is better than 18 bits
3620 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3621 getF32Constant(DAG, 0x3924b03e));
3622 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3623 getF32Constant(DAG, 0x3ab24b87));
3624 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3625 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3626 getF32Constant(DAG, 0x3c1d8c17));
3627 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3628 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3629 getF32Constant(DAG, 0x3d634a1d));
3630 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3631 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3632 getF32Constant(DAG, 0x3e75fe14));
3633 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3634 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3635 getF32Constant(DAG, 0x3f317234));
3636 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3637 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3638 getF32Constant(DAG, 0x3f800000));
3639 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3640 SDValue TwoToFractionalPartOfX =
3641 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3643 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3644 MVT::f32, TwoToFractionalPartOfX);
3646 } else {
3647 // No special expansion.
3648 result = DAG.getNode(ISD::FEXP2, dl,
3649 getValue(I.getOperand(1)).getValueType(),
3650 getValue(I.getOperand(1)));
3653 setValue(&I, result);
3656 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3657 /// limited-precision mode with x == 10.0f.
3658 void
3659 SelectionDAGLowering::visitPow(CallInst &I) {
3660 SDValue result;
3661 Value *Val = I.getOperand(1);
3662 DebugLoc dl = getCurDebugLoc();
3663 bool IsExp10 = false;
3665 if (getValue(Val).getValueType() == MVT::f32 &&
3666 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3667 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3668 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3669 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3670 APFloat Ten(10.0f);
3671 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3676 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3677 SDValue Op = getValue(I.getOperand(2));
3679 // Put the exponent in the right bit position for later addition to the
3680 // final result:
3682 // #define LOG2OF10 3.3219281f
3683 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3684 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3685 getF32Constant(DAG, 0x40549a78));
3686 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3688 // FractionalPartOfX = x - (float)IntegerPartOfX;
3689 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3690 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3692 // IntegerPartOfX <<= 23;
3693 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3694 DAG.getConstant(23, TLI.getPointerTy()));
3696 if (LimitFloatPrecision <= 6) {
3697 // For floating-point precision of 6:
3699 // twoToFractionalPartOfX =
3700 // 0.997535578f +
3701 // (0.735607626f + 0.252464424f * x) * x;
3703 // error 0.0144103317, which is 6 bits
3704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3705 getF32Constant(DAG, 0x3e814304));
3706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3707 getF32Constant(DAG, 0x3f3c50c8));
3708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3710 getF32Constant(DAG, 0x3f7f5e7e));
3711 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3712 SDValue TwoToFractionalPartOfX =
3713 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3715 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3716 MVT::f32, TwoToFractionalPartOfX);
3717 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3718 // For floating-point precision of 12:
3720 // TwoToFractionalPartOfX =
3721 // 0.999892986f +
3722 // (0.696457318f +
3723 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3725 // error 0.000107046256, which is 13 to 14 bits
3726 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3727 getF32Constant(DAG, 0x3da235e3));
3728 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3729 getF32Constant(DAG, 0x3e65b8f3));
3730 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3731 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3732 getF32Constant(DAG, 0x3f324b07));
3733 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3734 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3735 getF32Constant(DAG, 0x3f7ff8fd));
3736 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3737 SDValue TwoToFractionalPartOfX =
3738 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3740 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3741 MVT::f32, TwoToFractionalPartOfX);
3742 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3743 // For floating-point precision of 18:
3745 // TwoToFractionalPartOfX =
3746 // 0.999999982f +
3747 // (0.693148872f +
3748 // (0.240227044f +
3749 // (0.554906021e-1f +
3750 // (0.961591928e-2f +
3751 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3752 // error 2.47208000*10^(-7), which is better than 18 bits
3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3754 getF32Constant(DAG, 0x3924b03e));
3755 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3756 getF32Constant(DAG, 0x3ab24b87));
3757 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3758 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3759 getF32Constant(DAG, 0x3c1d8c17));
3760 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3761 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3762 getF32Constant(DAG, 0x3d634a1d));
3763 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3764 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3765 getF32Constant(DAG, 0x3e75fe14));
3766 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3767 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3768 getF32Constant(DAG, 0x3f317234));
3769 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3770 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3771 getF32Constant(DAG, 0x3f800000));
3772 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3773 SDValue TwoToFractionalPartOfX =
3774 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3776 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3777 MVT::f32, TwoToFractionalPartOfX);
3779 } else {
3780 // No special expansion.
3781 result = DAG.getNode(ISD::FPOW, dl,
3782 getValue(I.getOperand(1)).getValueType(),
3783 getValue(I.getOperand(1)),
3784 getValue(I.getOperand(2)));
3787 setValue(&I, result);
3790 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3791 /// we want to emit this as a call to a named external function, return the name
3792 /// otherwise lower it and return null.
3793 const char *
3794 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3795 DebugLoc dl = getCurDebugLoc();
3796 switch (Intrinsic) {
3797 default:
3798 // By default, turn this into a target intrinsic node.
3799 visitTargetIntrinsic(I, Intrinsic);
3800 return 0;
3801 case Intrinsic::vastart: visitVAStart(I); return 0;
3802 case Intrinsic::vaend: visitVAEnd(I); return 0;
3803 case Intrinsic::vacopy: visitVACopy(I); return 0;
3804 case Intrinsic::returnaddress:
3805 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3806 getValue(I.getOperand(1))));
3807 return 0;
3808 case Intrinsic::frameaddress:
3809 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3810 getValue(I.getOperand(1))));
3811 return 0;
3812 case Intrinsic::setjmp:
3813 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3814 break;
3815 case Intrinsic::longjmp:
3816 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3817 break;
3818 case Intrinsic::memcpy: {
3819 SDValue Op1 = getValue(I.getOperand(1));
3820 SDValue Op2 = getValue(I.getOperand(2));
3821 SDValue Op3 = getValue(I.getOperand(3));
3822 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3823 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3824 I.getOperand(1), 0, I.getOperand(2), 0));
3825 return 0;
3827 case Intrinsic::memset: {
3828 SDValue Op1 = getValue(I.getOperand(1));
3829 SDValue Op2 = getValue(I.getOperand(2));
3830 SDValue Op3 = getValue(I.getOperand(3));
3831 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3832 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3833 I.getOperand(1), 0));
3834 return 0;
3836 case Intrinsic::memmove: {
3837 SDValue Op1 = getValue(I.getOperand(1));
3838 SDValue Op2 = getValue(I.getOperand(2));
3839 SDValue Op3 = getValue(I.getOperand(3));
3840 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3842 // If the source and destination are known to not be aliases, we can
3843 // lower memmove as memcpy.
3844 uint64_t Size = -1ULL;
3845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3846 Size = C->getZExtValue();
3847 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3848 AliasAnalysis::NoAlias) {
3849 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3850 I.getOperand(1), 0, I.getOperand(2), 0));
3851 return 0;
3854 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3855 I.getOperand(1), 0, I.getOperand(2), 0));
3856 return 0;
3858 case Intrinsic::dbg_stoppoint: {
3859 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3860 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3861 MachineFunction &MF = DAG.getMachineFunction();
3862 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3863 setCurDebugLoc(Loc);
3865 if (OptLevel == CodeGenOpt::None)
3866 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3867 SPI.getLine(),
3868 SPI.getColumn(),
3869 SPI.getContext()));
3871 return 0;
3873 case Intrinsic::dbg_region_start: {
3874 DwarfWriter *DW = DAG.getDwarfWriter();
3875 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3876 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3877 && DW->ShouldEmitDwarfDebug()) {
3878 unsigned LabelID =
3879 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3880 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3881 getRoot(), LabelID));
3883 return 0;
3885 case Intrinsic::dbg_region_end: {
3886 DwarfWriter *DW = DAG.getDwarfWriter();
3887 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3889 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3890 || !DW->ShouldEmitDwarfDebug())
3891 return 0;
3893 MachineFunction &MF = DAG.getMachineFunction();
3894 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3896 if (isInlinedFnEnd(REI, MF.getFunction())) {
3897 // This is end of inlined function. Debugging information for inlined
3898 // function is not handled yet (only supported by FastISel).
3899 if (OptLevel == CodeGenOpt::None) {
3900 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3901 if (ID != 0)
3902 // Returned ID is 0 if this is unbalanced "end of inlined
3903 // scope". This could happen if optimizer eats dbg intrinsics or
3904 // "beginning of inlined scope" is not recoginized due to missing
3905 // location info. In such cases, do ignore this region.end.
3906 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3907 getRoot(), ID));
3909 return 0;
3912 unsigned LabelID =
3913 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3914 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3915 getRoot(), LabelID));
3916 return 0;
3918 case Intrinsic::dbg_func_start: {
3919 DwarfWriter *DW = DAG.getDwarfWriter();
3920 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3921 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3922 return 0;
3924 MachineFunction &MF = DAG.getMachineFunction();
3925 // This is a beginning of an inlined function.
3926 if (isInlinedFnStart(FSI, MF.getFunction())) {
3927 if (OptLevel != CodeGenOpt::None)
3928 // FIXME: Debugging informaation for inlined function is only
3929 // supported at CodeGenOpt::Node.
3930 return 0;
3932 DebugLoc PrevLoc = CurDebugLoc;
3933 // If llvm.dbg.func.start is seen in a new block before any
3934 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3935 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3936 if (PrevLoc.isUnknown())
3937 return 0;
3939 // Record the source line.
3940 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3942 if (!DW || !DW->ShouldEmitDwarfDebug())
3943 return 0;
3944 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3945 DISubprogram SP(cast<GlobalVariable>(FSI.getSubprogram()));
3946 DICompileUnit CU(PrevLocTpl.CompileUnit);
3947 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3948 PrevLocTpl.Line,
3949 PrevLocTpl.Col);
3950 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3951 getRoot(), LabelID));
3952 return 0;
3955 // This is a beginning of a new function.
3956 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3958 if (!DW || !DW->ShouldEmitDwarfDebug())
3959 return 0;
3960 // llvm.dbg.func_start also defines beginning of function scope.
3961 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
3962 return 0;
3964 case Intrinsic::dbg_declare: {
3965 if (OptLevel != CodeGenOpt::None)
3966 // FIXME: Variable debug info is not supported here.
3967 return 0;
3969 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3970 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3971 return 0;
3973 Value *Variable = DI.getVariable();
3974 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3975 getValue(DI.getAddress()), getValue(Variable)));
3976 return 0;
3978 case Intrinsic::eh_exception: {
3979 // Insert the EXCEPTIONADDR instruction.
3980 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3981 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3982 SDValue Ops[1];
3983 Ops[0] = DAG.getRoot();
3984 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3985 setValue(&I, Op);
3986 DAG.setRoot(Op.getValue(1));
3987 return 0;
3990 case Intrinsic::eh_selector_i32:
3991 case Intrinsic::eh_selector_i64: {
3992 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3993 EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
3995 if (MMI) {
3996 if (CurMBB->isLandingPad())
3997 AddCatchInfo(I, MMI, CurMBB);
3998 else {
3999 #ifndef NDEBUG
4000 FuncInfo.CatchInfoLost.insert(&I);
4001 #endif
4002 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4003 unsigned Reg = TLI.getExceptionSelectorRegister();
4004 if (Reg) CurMBB->addLiveIn(Reg);
4007 // Insert the EHSELECTION instruction.
4008 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4009 SDValue Ops[2];
4010 Ops[0] = getValue(I.getOperand(1));
4011 Ops[1] = getRoot();
4012 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4013 setValue(&I, Op);
4014 DAG.setRoot(Op.getValue(1));
4015 } else {
4016 setValue(&I, DAG.getConstant(0, VT));
4019 return 0;
4022 case Intrinsic::eh_typeid_for_i32:
4023 case Intrinsic::eh_typeid_for_i64: {
4024 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4025 EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4026 MVT::i32 : MVT::i64);
4028 if (MMI) {
4029 // Find the type id for the given typeinfo.
4030 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4032 unsigned TypeID = MMI->getTypeIDFor(GV);
4033 setValue(&I, DAG.getConstant(TypeID, VT));
4034 } else {
4035 // Return something different to eh_selector.
4036 setValue(&I, DAG.getConstant(1, VT));
4039 return 0;
4042 case Intrinsic::eh_return_i32:
4043 case Intrinsic::eh_return_i64:
4044 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4045 MMI->setCallsEHReturn(true);
4046 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4047 MVT::Other,
4048 getControlRoot(),
4049 getValue(I.getOperand(1)),
4050 getValue(I.getOperand(2))));
4051 } else {
4052 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4055 return 0;
4056 case Intrinsic::eh_unwind_init:
4057 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4058 MMI->setCallsUnwindInit(true);
4061 return 0;
4063 case Intrinsic::eh_dwarf_cfa: {
4064 EVT VT = getValue(I.getOperand(1)).getValueType();
4065 SDValue CfaArg;
4066 if (VT.bitsGT(TLI.getPointerTy()))
4067 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4068 TLI.getPointerTy(), getValue(I.getOperand(1)));
4069 else
4070 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4071 TLI.getPointerTy(), getValue(I.getOperand(1)));
4073 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4074 TLI.getPointerTy(),
4075 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4076 TLI.getPointerTy()),
4077 CfaArg);
4078 setValue(&I, DAG.getNode(ISD::ADD, dl,
4079 TLI.getPointerTy(),
4080 DAG.getNode(ISD::FRAMEADDR, dl,
4081 TLI.getPointerTy(),
4082 DAG.getConstant(0,
4083 TLI.getPointerTy())),
4084 Offset));
4085 return 0;
4087 case Intrinsic::eh_sjlj_callsite: {
4088 MachineFunction &MF = DAG.getMachineFunction();
4089 MF.setCallSiteIndex(cast<ConstantSDNode>(getValue(I.getOperand(1)))->getZExtValue());
4090 return 0;
4092 case Intrinsic::convertff:
4093 case Intrinsic::convertfsi:
4094 case Intrinsic::convertfui:
4095 case Intrinsic::convertsif:
4096 case Intrinsic::convertuif:
4097 case Intrinsic::convertss:
4098 case Intrinsic::convertsu:
4099 case Intrinsic::convertus:
4100 case Intrinsic::convertuu: {
4101 ISD::CvtCode Code = ISD::CVT_INVALID;
4102 switch (Intrinsic) {
4103 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4104 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4105 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4106 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4107 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4108 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4109 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4110 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4111 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4113 EVT DestVT = TLI.getValueType(I.getType());
4114 Value* Op1 = I.getOperand(1);
4115 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4116 DAG.getValueType(DestVT),
4117 DAG.getValueType(getValue(Op1).getValueType()),
4118 getValue(I.getOperand(2)),
4119 getValue(I.getOperand(3)),
4120 Code));
4121 return 0;
4124 case Intrinsic::sqrt:
4125 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4126 getValue(I.getOperand(1)).getValueType(),
4127 getValue(I.getOperand(1))));
4128 return 0;
4129 case Intrinsic::powi:
4130 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4131 getValue(I.getOperand(1)).getValueType(),
4132 getValue(I.getOperand(1)),
4133 getValue(I.getOperand(2))));
4134 return 0;
4135 case Intrinsic::sin:
4136 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4137 getValue(I.getOperand(1)).getValueType(),
4138 getValue(I.getOperand(1))));
4139 return 0;
4140 case Intrinsic::cos:
4141 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4142 getValue(I.getOperand(1)).getValueType(),
4143 getValue(I.getOperand(1))));
4144 return 0;
4145 case Intrinsic::log:
4146 visitLog(I);
4147 return 0;
4148 case Intrinsic::log2:
4149 visitLog2(I);
4150 return 0;
4151 case Intrinsic::log10:
4152 visitLog10(I);
4153 return 0;
4154 case Intrinsic::exp:
4155 visitExp(I);
4156 return 0;
4157 case Intrinsic::exp2:
4158 visitExp2(I);
4159 return 0;
4160 case Intrinsic::pow:
4161 visitPow(I);
4162 return 0;
4163 case Intrinsic::pcmarker: {
4164 SDValue Tmp = getValue(I.getOperand(1));
4165 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4166 return 0;
4168 case Intrinsic::readcyclecounter: {
4169 SDValue Op = getRoot();
4170 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4171 DAG.getVTList(MVT::i64, MVT::Other),
4172 &Op, 1);
4173 setValue(&I, Tmp);
4174 DAG.setRoot(Tmp.getValue(1));
4175 return 0;
4177 case Intrinsic::bswap:
4178 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4179 getValue(I.getOperand(1)).getValueType(),
4180 getValue(I.getOperand(1))));
4181 return 0;
4182 case Intrinsic::cttz: {
4183 SDValue Arg = getValue(I.getOperand(1));
4184 EVT Ty = Arg.getValueType();
4185 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4186 setValue(&I, result);
4187 return 0;
4189 case Intrinsic::ctlz: {
4190 SDValue Arg = getValue(I.getOperand(1));
4191 EVT Ty = Arg.getValueType();
4192 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4193 setValue(&I, result);
4194 return 0;
4196 case Intrinsic::ctpop: {
4197 SDValue Arg = getValue(I.getOperand(1));
4198 EVT Ty = Arg.getValueType();
4199 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4200 setValue(&I, result);
4201 return 0;
4203 case Intrinsic::stacksave: {
4204 SDValue Op = getRoot();
4205 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4206 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4207 setValue(&I, Tmp);
4208 DAG.setRoot(Tmp.getValue(1));
4209 return 0;
4211 case Intrinsic::stackrestore: {
4212 SDValue Tmp = getValue(I.getOperand(1));
4213 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4214 return 0;
4216 case Intrinsic::stackprotector: {
4217 // Emit code into the DAG to store the stack guard onto the stack.
4218 MachineFunction &MF = DAG.getMachineFunction();
4219 MachineFrameInfo *MFI = MF.getFrameInfo();
4220 EVT PtrTy = TLI.getPointerTy();
4222 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4223 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4225 int FI = FuncInfo.StaticAllocaMap[Slot];
4226 MFI->setStackProtectorIndex(FI);
4228 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4230 // Store the stack protector onto the stack.
4231 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4232 PseudoSourceValue::getFixedStack(FI),
4233 0, true);
4234 setValue(&I, Result);
4235 DAG.setRoot(Result);
4236 return 0;
4238 case Intrinsic::var_annotation:
4239 // Discard annotate attributes
4240 return 0;
4242 case Intrinsic::init_trampoline: {
4243 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4245 SDValue Ops[6];
4246 Ops[0] = getRoot();
4247 Ops[1] = getValue(I.getOperand(1));
4248 Ops[2] = getValue(I.getOperand(2));
4249 Ops[3] = getValue(I.getOperand(3));
4250 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4251 Ops[5] = DAG.getSrcValue(F);
4253 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4254 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4255 Ops, 6);
4257 setValue(&I, Tmp);
4258 DAG.setRoot(Tmp.getValue(1));
4259 return 0;
4262 case Intrinsic::gcroot:
4263 if (GFI) {
4264 Value *Alloca = I.getOperand(1);
4265 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4267 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4268 GFI->addStackRoot(FI->getIndex(), TypeMap);
4270 return 0;
4272 case Intrinsic::gcread:
4273 case Intrinsic::gcwrite:
4274 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4275 return 0;
4277 case Intrinsic::flt_rounds: {
4278 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4279 return 0;
4282 case Intrinsic::trap: {
4283 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4284 return 0;
4287 case Intrinsic::uadd_with_overflow:
4288 return implVisitAluOverflow(I, ISD::UADDO);
4289 case Intrinsic::sadd_with_overflow:
4290 return implVisitAluOverflow(I, ISD::SADDO);
4291 case Intrinsic::usub_with_overflow:
4292 return implVisitAluOverflow(I, ISD::USUBO);
4293 case Intrinsic::ssub_with_overflow:
4294 return implVisitAluOverflow(I, ISD::SSUBO);
4295 case Intrinsic::umul_with_overflow:
4296 return implVisitAluOverflow(I, ISD::UMULO);
4297 case Intrinsic::smul_with_overflow:
4298 return implVisitAluOverflow(I, ISD::SMULO);
4300 case Intrinsic::prefetch: {
4301 SDValue Ops[4];
4302 Ops[0] = getRoot();
4303 Ops[1] = getValue(I.getOperand(1));
4304 Ops[2] = getValue(I.getOperand(2));
4305 Ops[3] = getValue(I.getOperand(3));
4306 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4307 return 0;
4310 case Intrinsic::memory_barrier: {
4311 SDValue Ops[6];
4312 Ops[0] = getRoot();
4313 for (int x = 1; x < 6; ++x)
4314 Ops[x] = getValue(I.getOperand(x));
4316 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4317 return 0;
4319 case Intrinsic::atomic_cmp_swap: {
4320 SDValue Root = getRoot();
4321 SDValue L =
4322 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4323 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4324 Root,
4325 getValue(I.getOperand(1)),
4326 getValue(I.getOperand(2)),
4327 getValue(I.getOperand(3)),
4328 I.getOperand(1));
4329 setValue(&I, L);
4330 DAG.setRoot(L.getValue(1));
4331 return 0;
4333 case Intrinsic::atomic_load_add:
4334 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4335 case Intrinsic::atomic_load_sub:
4336 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4337 case Intrinsic::atomic_load_or:
4338 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4339 case Intrinsic::atomic_load_xor:
4340 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4341 case Intrinsic::atomic_load_and:
4342 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4343 case Intrinsic::atomic_load_nand:
4344 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4345 case Intrinsic::atomic_load_max:
4346 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4347 case Intrinsic::atomic_load_min:
4348 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4349 case Intrinsic::atomic_load_umin:
4350 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4351 case Intrinsic::atomic_load_umax:
4352 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4353 case Intrinsic::atomic_swap:
4354 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4358 /// Test if the given instruction is in a position to be optimized
4359 /// with a tail-call. This roughly means that it's in a block with
4360 /// a return and there's nothing that needs to be scheduled
4361 /// between it and the return.
4363 /// This function only tests target-independent requirements.
4364 /// For target-dependent requirements, a target should override
4365 /// TargetLowering::IsEligibleForTailCallOptimization.
4367 static bool
4368 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4369 const TargetLowering &TLI) {
4370 const BasicBlock *ExitBB = I->getParent();
4371 const TerminatorInst *Term = ExitBB->getTerminator();
4372 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4373 const Function *F = ExitBB->getParent();
4375 // The block must end in a return statement or an unreachable.
4376 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4378 // If I will have a chain, make sure no other instruction that will have a
4379 // chain interposes between I and the return.
4380 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4381 !I->isSafeToSpeculativelyExecute())
4382 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4383 --BBI) {
4384 if (&*BBI == I)
4385 break;
4386 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4387 !BBI->isSafeToSpeculativelyExecute())
4388 return false;
4391 // If the block ends with a void return or unreachable, it doesn't matter
4392 // what the call's return type is.
4393 if (!Ret || Ret->getNumOperands() == 0) return true;
4395 // Conservatively require the attributes of the call to match those of
4396 // the return.
4397 if (F->getAttributes().getRetAttributes() != RetAttr)
4398 return false;
4400 // Otherwise, make sure the unmodified return value of I is the return value.
4401 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4402 U = dyn_cast<Instruction>(U->getOperand(0))) {
4403 if (!U)
4404 return false;
4405 if (!U->hasOneUse())
4406 return false;
4407 if (U == I)
4408 break;
4409 // Check for a truly no-op truncate.
4410 if (isa<TruncInst>(U) &&
4411 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4412 continue;
4413 // Check for a truly no-op bitcast.
4414 if (isa<BitCastInst>(U) &&
4415 (U->getOperand(0)->getType() == U->getType() ||
4416 (isa<PointerType>(U->getOperand(0)->getType()) &&
4417 isa<PointerType>(U->getType()))))
4418 continue;
4419 // Otherwise it's not a true no-op.
4420 return false;
4423 return true;
4426 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4427 bool isTailCall,
4428 MachineBasicBlock *LandingPad) {
4429 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4430 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4431 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4432 unsigned BeginLabel = 0, EndLabel = 0;
4434 TargetLowering::ArgListTy Args;
4435 TargetLowering::ArgListEntry Entry;
4436 Args.reserve(CS.arg_size());
4437 unsigned j = 1;
4438 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4439 i != e; ++i, ++j) {
4440 SDValue ArgNode = getValue(*i);
4441 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4443 unsigned attrInd = i - CS.arg_begin() + 1;
4444 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4445 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4446 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4447 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4448 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4449 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4450 Entry.Alignment = CS.getParamAlignment(attrInd);
4451 Args.push_back(Entry);
4454 if (LandingPad && MMI) {
4455 MachineFunction &MF = DAG.getMachineFunction();
4456 // Insert a label before the invoke call to mark the try range. This can be
4457 // used to detect deletion of the invoke via the MachineModuleInfo.
4458 BeginLabel = MMI->NextLabelID();
4460 // Map this landing pad to the current call site entry
4461 MF.setLandingPadCallSiteIndex(LandingPad, MF.getCallSiteIndex());
4463 // Both PendingLoads and PendingExports must be flushed here;
4464 // this call might not return.
4465 (void)getRoot();
4466 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4467 getControlRoot(), BeginLabel));
4470 // Check if target-independent constraints permit a tail call here.
4471 // Target-dependent constraints are checked within TLI.LowerCallTo.
4472 if (isTailCall &&
4473 !isInTailCallPosition(CS.getInstruction(),
4474 CS.getAttributes().getRetAttributes(),
4475 TLI))
4476 isTailCall = false;
4478 std::pair<SDValue,SDValue> Result =
4479 TLI.LowerCallTo(getRoot(), CS.getType(),
4480 CS.paramHasAttr(0, Attribute::SExt),
4481 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4482 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4483 CS.getCallingConv(),
4484 isTailCall,
4485 !CS.getInstruction()->use_empty(),
4486 Callee, Args, DAG, getCurDebugLoc());
4487 assert((isTailCall || Result.second.getNode()) &&
4488 "Non-null chain expected with non-tail call!");
4489 assert((Result.second.getNode() || !Result.first.getNode()) &&
4490 "Null value expected with tail call!");
4491 if (Result.first.getNode())
4492 setValue(CS.getInstruction(), Result.first);
4493 // As a special case, a null chain means that a tail call has
4494 // been emitted and the DAG root is already updated.
4495 if (Result.second.getNode())
4496 DAG.setRoot(Result.second);
4497 else
4498 HasTailCall = true;
4500 if (LandingPad && MMI) {
4501 // Insert a label at the end of the invoke call to mark the try range. This
4502 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4503 EndLabel = MMI->NextLabelID();
4504 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4505 getRoot(), EndLabel));
4507 // Inform MachineModuleInfo of range.
4508 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4513 void SelectionDAGLowering::visitCall(CallInst &I) {
4514 const char *RenameFn = 0;
4515 if (Function *F = I.getCalledFunction()) {
4516 if (F->isDeclaration()) {
4517 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4518 if (II) {
4519 if (unsigned IID = II->getIntrinsicID(F)) {
4520 RenameFn = visitIntrinsicCall(I, IID);
4521 if (!RenameFn)
4522 return;
4525 if (unsigned IID = F->getIntrinsicID()) {
4526 RenameFn = visitIntrinsicCall(I, IID);
4527 if (!RenameFn)
4528 return;
4532 // Check for well-known libc/libm calls. If the function is internal, it
4533 // can't be a library call.
4534 if (!F->hasLocalLinkage() && F->hasName()) {
4535 StringRef Name = F->getName();
4536 if (Name == "copysign" || Name == "copysignf") {
4537 if (I.getNumOperands() == 3 && // Basic sanity checks.
4538 I.getOperand(1)->getType()->isFloatingPoint() &&
4539 I.getType() == I.getOperand(1)->getType() &&
4540 I.getType() == I.getOperand(2)->getType()) {
4541 SDValue LHS = getValue(I.getOperand(1));
4542 SDValue RHS = getValue(I.getOperand(2));
4543 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4544 LHS.getValueType(), LHS, RHS));
4545 return;
4547 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4548 if (I.getNumOperands() == 2 && // Basic sanity checks.
4549 I.getOperand(1)->getType()->isFloatingPoint() &&
4550 I.getType() == I.getOperand(1)->getType()) {
4551 SDValue Tmp = getValue(I.getOperand(1));
4552 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4553 Tmp.getValueType(), Tmp));
4554 return;
4556 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4557 if (I.getNumOperands() == 2 && // Basic sanity checks.
4558 I.getOperand(1)->getType()->isFloatingPoint() &&
4559 I.getType() == I.getOperand(1)->getType()) {
4560 SDValue Tmp = getValue(I.getOperand(1));
4561 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4562 Tmp.getValueType(), Tmp));
4563 return;
4565 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4566 if (I.getNumOperands() == 2 && // Basic sanity checks.
4567 I.getOperand(1)->getType()->isFloatingPoint() &&
4568 I.getType() == I.getOperand(1)->getType()) {
4569 SDValue Tmp = getValue(I.getOperand(1));
4570 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4571 Tmp.getValueType(), Tmp));
4572 return;
4576 } else if (isa<InlineAsm>(I.getOperand(0))) {
4577 visitInlineAsm(&I);
4578 return;
4581 SDValue Callee;
4582 if (!RenameFn)
4583 Callee = getValue(I.getOperand(0));
4584 else
4585 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4587 // Check if we can potentially perform a tail call. More detailed
4588 // checking is be done within LowerCallTo, after more information
4589 // about the call is known.
4590 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4592 LowerCallTo(&I, Callee, isTailCall);
4596 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4597 /// this value and returns the result as a ValueVT value. This uses
4598 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4599 /// If the Flag pointer is NULL, no flag is used.
4600 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4601 SDValue &Chain,
4602 SDValue *Flag) const {
4603 // Assemble the legal parts into the final values.
4604 SmallVector<SDValue, 4> Values(ValueVTs.size());
4605 SmallVector<SDValue, 8> Parts;
4606 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4607 // Copy the legal parts from the registers.
4608 EVT ValueVT = ValueVTs[Value];
4609 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4610 EVT RegisterVT = RegVTs[Value];
4612 Parts.resize(NumRegs);
4613 for (unsigned i = 0; i != NumRegs; ++i) {
4614 SDValue P;
4615 if (Flag == 0)
4616 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4617 else {
4618 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4619 *Flag = P.getValue(2);
4621 Chain = P.getValue(1);
4623 // If the source register was virtual and if we know something about it,
4624 // add an assert node.
4625 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4626 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4627 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4628 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4629 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4630 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4632 unsigned RegSize = RegisterVT.getSizeInBits();
4633 unsigned NumSignBits = LOI.NumSignBits;
4634 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4636 // FIXME: We capture more information than the dag can represent. For
4637 // now, just use the tightest assertzext/assertsext possible.
4638 bool isSExt = true;
4639 EVT FromVT(MVT::Other);
4640 if (NumSignBits == RegSize)
4641 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4642 else if (NumZeroBits >= RegSize-1)
4643 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4644 else if (NumSignBits > RegSize-8)
4645 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4646 else if (NumZeroBits >= RegSize-8)
4647 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4648 else if (NumSignBits > RegSize-16)
4649 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4650 else if (NumZeroBits >= RegSize-16)
4651 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4652 else if (NumSignBits > RegSize-32)
4653 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4654 else if (NumZeroBits >= RegSize-32)
4655 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4657 if (FromVT != MVT::Other) {
4658 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4659 RegisterVT, P, DAG.getValueType(FromVT));
4665 Parts[i] = P;
4668 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4669 NumRegs, RegisterVT, ValueVT);
4670 Part += NumRegs;
4671 Parts.clear();
4674 return DAG.getNode(ISD::MERGE_VALUES, dl,
4675 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4676 &Values[0], ValueVTs.size());
4679 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4680 /// specified value into the registers specified by this object. This uses
4681 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4682 /// If the Flag pointer is NULL, no flag is used.
4683 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4684 SDValue &Chain, SDValue *Flag) const {
4685 // Get the list of the values's legal parts.
4686 unsigned NumRegs = Regs.size();
4687 SmallVector<SDValue, 8> Parts(NumRegs);
4688 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4689 EVT ValueVT = ValueVTs[Value];
4690 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4691 EVT RegisterVT = RegVTs[Value];
4693 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4694 &Parts[Part], NumParts, RegisterVT);
4695 Part += NumParts;
4698 // Copy the parts into the registers.
4699 SmallVector<SDValue, 8> Chains(NumRegs);
4700 for (unsigned i = 0; i != NumRegs; ++i) {
4701 SDValue Part;
4702 if (Flag == 0)
4703 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4704 else {
4705 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4706 *Flag = Part.getValue(1);
4708 Chains[i] = Part.getValue(0);
4711 if (NumRegs == 1 || Flag)
4712 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4713 // flagged to it. That is the CopyToReg nodes and the user are considered
4714 // a single scheduling unit. If we create a TokenFactor and return it as
4715 // chain, then the TokenFactor is both a predecessor (operand) of the
4716 // user as well as a successor (the TF operands are flagged to the user).
4717 // c1, f1 = CopyToReg
4718 // c2, f2 = CopyToReg
4719 // c3 = TokenFactor c1, c2
4720 // ...
4721 // = op c3, ..., f2
4722 Chain = Chains[NumRegs-1];
4723 else
4724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4727 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4728 /// operand list. This adds the code marker and includes the number of
4729 /// values added into it.
4730 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4731 bool HasMatching,unsigned MatchingIdx,
4732 SelectionDAG &DAG,
4733 std::vector<SDValue> &Ops) const {
4734 EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4735 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4736 unsigned Flag = Code | (Regs.size() << 3);
4737 if (HasMatching)
4738 Flag |= 0x80000000 | (MatchingIdx << 16);
4739 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4740 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4741 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4742 EVT RegisterVT = RegVTs[Value];
4743 for (unsigned i = 0; i != NumRegs; ++i) {
4744 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4745 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4750 /// isAllocatableRegister - If the specified register is safe to allocate,
4751 /// i.e. it isn't a stack pointer or some other special register, return the
4752 /// register class for the register. Otherwise, return null.
4753 static const TargetRegisterClass *
4754 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4755 const TargetLowering &TLI,
4756 const TargetRegisterInfo *TRI) {
4757 EVT FoundVT = MVT::Other;
4758 const TargetRegisterClass *FoundRC = 0;
4759 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4760 E = TRI->regclass_end(); RCI != E; ++RCI) {
4761 EVT ThisVT = MVT::Other;
4763 const TargetRegisterClass *RC = *RCI;
4764 // If none of the the value types for this register class are valid, we
4765 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4766 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4767 I != E; ++I) {
4768 if (TLI.isTypeLegal(*I)) {
4769 // If we have already found this register in a different register class,
4770 // choose the one with the largest VT specified. For example, on
4771 // PowerPC, we favor f64 register classes over f32.
4772 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4773 ThisVT = *I;
4774 break;
4779 if (ThisVT == MVT::Other) continue;
4781 // NOTE: This isn't ideal. In particular, this might allocate the
4782 // frame pointer in functions that need it (due to them not being taken
4783 // out of allocation, because a variable sized allocation hasn't been seen
4784 // yet). This is a slight code pessimization, but should still work.
4785 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4786 E = RC->allocation_order_end(MF); I != E; ++I)
4787 if (*I == Reg) {
4788 // We found a matching register class. Keep looking at others in case
4789 // we find one with larger registers that this physreg is also in.
4790 FoundRC = RC;
4791 FoundVT = ThisVT;
4792 break;
4795 return FoundRC;
4799 namespace llvm {
4800 /// AsmOperandInfo - This contains information for each constraint that we are
4801 /// lowering.
4802 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4803 public TargetLowering::AsmOperandInfo {
4804 public:
4805 /// CallOperand - If this is the result output operand or a clobber
4806 /// this is null, otherwise it is the incoming operand to the CallInst.
4807 /// This gets modified as the asm is processed.
4808 SDValue CallOperand;
4810 /// AssignedRegs - If this is a register or register class operand, this
4811 /// contains the set of register corresponding to the operand.
4812 RegsForValue AssignedRegs;
4814 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4815 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4818 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4819 /// busy in OutputRegs/InputRegs.
4820 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4821 std::set<unsigned> &OutputRegs,
4822 std::set<unsigned> &InputRegs,
4823 const TargetRegisterInfo &TRI) const {
4824 if (isOutReg) {
4825 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4826 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4828 if (isInReg) {
4829 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4830 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4834 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4835 /// corresponds to. If there is no Value* for this operand, it returns
4836 /// MVT::Other.
4837 EVT getCallOperandValEVT(LLVMContext &Context,
4838 const TargetLowering &TLI,
4839 const TargetData *TD) const {
4840 if (CallOperandVal == 0) return MVT::Other;
4842 if (isa<BasicBlock>(CallOperandVal))
4843 return TLI.getPointerTy();
4845 const llvm::Type *OpTy = CallOperandVal->getType();
4847 // If this is an indirect operand, the operand is a pointer to the
4848 // accessed type.
4849 if (isIndirect)
4850 OpTy = cast<PointerType>(OpTy)->getElementType();
4852 // If OpTy is not a single value, it may be a struct/union that we
4853 // can tile with integers.
4854 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4855 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4856 switch (BitSize) {
4857 default: break;
4858 case 1:
4859 case 8:
4860 case 16:
4861 case 32:
4862 case 64:
4863 case 128:
4864 OpTy = IntegerType::get(Context, BitSize);
4865 break;
4869 return TLI.getValueType(OpTy, true);
4872 private:
4873 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4874 /// specified set.
4875 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4876 const TargetRegisterInfo &TRI) {
4877 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4878 Regs.insert(Reg);
4879 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4880 for (; *Aliases; ++Aliases)
4881 Regs.insert(*Aliases);
4884 } // end llvm namespace.
4887 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4888 /// specified operand. We prefer to assign virtual registers, to allow the
4889 /// register allocator handle the assignment process. However, if the asm uses
4890 /// features that we can't model on machineinstrs, we have SDISel do the
4891 /// allocation. This produces generally horrible, but correct, code.
4893 /// OpInfo describes the operand.
4894 /// Input and OutputRegs are the set of already allocated physical registers.
4896 void SelectionDAGLowering::
4897 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4898 std::set<unsigned> &OutputRegs,
4899 std::set<unsigned> &InputRegs) {
4900 LLVMContext &Context = FuncInfo.Fn->getContext();
4902 // Compute whether this value requires an input register, an output register,
4903 // or both.
4904 bool isOutReg = false;
4905 bool isInReg = false;
4906 switch (OpInfo.Type) {
4907 case InlineAsm::isOutput:
4908 isOutReg = true;
4910 // If there is an input constraint that matches this, we need to reserve
4911 // the input register so no other inputs allocate to it.
4912 isInReg = OpInfo.hasMatchingInput();
4913 break;
4914 case InlineAsm::isInput:
4915 isInReg = true;
4916 isOutReg = false;
4917 break;
4918 case InlineAsm::isClobber:
4919 isOutReg = true;
4920 isInReg = true;
4921 break;
4925 MachineFunction &MF = DAG.getMachineFunction();
4926 SmallVector<unsigned, 4> Regs;
4928 // If this is a constraint for a single physreg, or a constraint for a
4929 // register class, find it.
4930 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4931 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4932 OpInfo.ConstraintVT);
4934 unsigned NumRegs = 1;
4935 if (OpInfo.ConstraintVT != MVT::Other) {
4936 // If this is a FP input in an integer register (or visa versa) insert a bit
4937 // cast of the input value. More generally, handle any case where the input
4938 // value disagrees with the register class we plan to stick this in.
4939 if (OpInfo.Type == InlineAsm::isInput &&
4940 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4941 // Try to convert to the first EVT that the reg class contains. If the
4942 // types are identical size, use a bitcast to convert (e.g. two differing
4943 // vector types).
4944 EVT RegVT = *PhysReg.second->vt_begin();
4945 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4946 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4947 RegVT, OpInfo.CallOperand);
4948 OpInfo.ConstraintVT = RegVT;
4949 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4950 // If the input is a FP value and we want it in FP registers, do a
4951 // bitcast to the corresponding integer type. This turns an f64 value
4952 // into i64, which can be passed with two i32 values on a 32-bit
4953 // machine.
4954 RegVT = EVT::getIntegerVT(Context,
4955 OpInfo.ConstraintVT.getSizeInBits());
4956 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4957 RegVT, OpInfo.CallOperand);
4958 OpInfo.ConstraintVT = RegVT;
4962 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
4965 EVT RegVT;
4966 EVT ValueVT = OpInfo.ConstraintVT;
4968 // If this is a constraint for a specific physical register, like {r17},
4969 // assign it now.
4970 if (unsigned AssignedReg = PhysReg.first) {
4971 const TargetRegisterClass *RC = PhysReg.second;
4972 if (OpInfo.ConstraintVT == MVT::Other)
4973 ValueVT = *RC->vt_begin();
4975 // Get the actual register value type. This is important, because the user
4976 // may have asked for (e.g.) the AX register in i32 type. We need to
4977 // remember that AX is actually i16 to get the right extension.
4978 RegVT = *RC->vt_begin();
4980 // This is a explicit reference to a physical register.
4981 Regs.push_back(AssignedReg);
4983 // If this is an expanded reference, add the rest of the regs to Regs.
4984 if (NumRegs != 1) {
4985 TargetRegisterClass::iterator I = RC->begin();
4986 for (; *I != AssignedReg; ++I)
4987 assert(I != RC->end() && "Didn't find reg!");
4989 // Already added the first reg.
4990 --NumRegs; ++I;
4991 for (; NumRegs; --NumRegs, ++I) {
4992 assert(I != RC->end() && "Ran out of registers to allocate!");
4993 Regs.push_back(*I);
4996 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4997 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4998 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4999 return;
5002 // Otherwise, if this was a reference to an LLVM register class, create vregs
5003 // for this reference.
5004 if (const TargetRegisterClass *RC = PhysReg.second) {
5005 RegVT = *RC->vt_begin();
5006 if (OpInfo.ConstraintVT == MVT::Other)
5007 ValueVT = RegVT;
5009 // Create the appropriate number of virtual registers.
5010 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5011 for (; NumRegs; --NumRegs)
5012 Regs.push_back(RegInfo.createVirtualRegister(RC));
5014 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5015 return;
5018 // This is a reference to a register class that doesn't directly correspond
5019 // to an LLVM register class. Allocate NumRegs consecutive, available,
5020 // registers from the class.
5021 std::vector<unsigned> RegClassRegs
5022 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5023 OpInfo.ConstraintVT);
5025 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5026 unsigned NumAllocated = 0;
5027 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5028 unsigned Reg = RegClassRegs[i];
5029 // See if this register is available.
5030 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5031 (isInReg && InputRegs.count(Reg))) { // Already used.
5032 // Make sure we find consecutive registers.
5033 NumAllocated = 0;
5034 continue;
5037 // Check to see if this register is allocatable (i.e. don't give out the
5038 // stack pointer).
5039 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5040 if (!RC) { // Couldn't allocate this register.
5041 // Reset NumAllocated to make sure we return consecutive registers.
5042 NumAllocated = 0;
5043 continue;
5046 // Okay, this register is good, we can use it.
5047 ++NumAllocated;
5049 // If we allocated enough consecutive registers, succeed.
5050 if (NumAllocated == NumRegs) {
5051 unsigned RegStart = (i-NumAllocated)+1;
5052 unsigned RegEnd = i+1;
5053 // Mark all of the allocated registers used.
5054 for (unsigned i = RegStart; i != RegEnd; ++i)
5055 Regs.push_back(RegClassRegs[i]);
5057 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5058 OpInfo.ConstraintVT);
5059 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5060 return;
5064 // Otherwise, we couldn't allocate enough registers for this.
5067 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5068 /// processed uses a memory 'm' constraint.
5069 static bool
5070 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5071 const TargetLowering &TLI) {
5072 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5073 InlineAsm::ConstraintInfo &CI = CInfos[i];
5074 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5075 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5076 if (CType == TargetLowering::C_Memory)
5077 return true;
5080 // Indirect operand accesses access memory.
5081 if (CI.isIndirect)
5082 return true;
5085 return false;
5088 /// visitInlineAsm - Handle a call to an InlineAsm object.
5090 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5091 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5093 /// ConstraintOperands - Information about all of the constraints.
5094 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5096 std::set<unsigned> OutputRegs, InputRegs;
5098 // Do a prepass over the constraints, canonicalizing them, and building up the
5099 // ConstraintOperands list.
5100 std::vector<InlineAsm::ConstraintInfo>
5101 ConstraintInfos = IA->ParseConstraints();
5103 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5105 SDValue Chain, Flag;
5107 // We won't need to flush pending loads if this asm doesn't touch
5108 // memory and is nonvolatile.
5109 if (hasMemory || IA->hasSideEffects())
5110 Chain = getRoot();
5111 else
5112 Chain = DAG.getRoot();
5114 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5115 unsigned ResNo = 0; // ResNo - The result number of the next output.
5116 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5117 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5118 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5120 EVT OpVT = MVT::Other;
5122 // Compute the value type for each operand.
5123 switch (OpInfo.Type) {
5124 case InlineAsm::isOutput:
5125 // Indirect outputs just consume an argument.
5126 if (OpInfo.isIndirect) {
5127 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5128 break;
5131 // The return value of the call is this value. As such, there is no
5132 // corresponding argument.
5133 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5134 "Bad inline asm!");
5135 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5136 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5137 } else {
5138 assert(ResNo == 0 && "Asm only has one result!");
5139 OpVT = TLI.getValueType(CS.getType());
5141 ++ResNo;
5142 break;
5143 case InlineAsm::isInput:
5144 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5145 break;
5146 case InlineAsm::isClobber:
5147 // Nothing to do.
5148 break;
5151 // If this is an input or an indirect output, process the call argument.
5152 // BasicBlocks are labels, currently appearing only in asm's.
5153 if (OpInfo.CallOperandVal) {
5154 // Strip bitcasts, if any. This mostly comes up for functions.
5155 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5157 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5158 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5159 } else {
5160 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5163 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5166 OpInfo.ConstraintVT = OpVT;
5169 // Second pass over the constraints: compute which constraint option to use
5170 // and assign registers to constraints that want a specific physreg.
5171 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5172 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5174 // If this is an output operand with a matching input operand, look up the
5175 // matching input. If their types mismatch, e.g. one is an integer, the
5176 // other is floating point, or their sizes are different, flag it as an
5177 // error.
5178 if (OpInfo.hasMatchingInput()) {
5179 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5180 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5181 if ((OpInfo.ConstraintVT.isInteger() !=
5182 Input.ConstraintVT.isInteger()) ||
5183 (OpInfo.ConstraintVT.getSizeInBits() !=
5184 Input.ConstraintVT.getSizeInBits())) {
5185 llvm_report_error("Unsupported asm: input constraint"
5186 " with a matching output constraint of incompatible"
5187 " type!");
5189 Input.ConstraintVT = OpInfo.ConstraintVT;
5193 // Compute the constraint code and ConstraintType to use.
5194 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5196 // If this is a memory input, and if the operand is not indirect, do what we
5197 // need to to provide an address for the memory input.
5198 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5199 !OpInfo.isIndirect) {
5200 assert(OpInfo.Type == InlineAsm::isInput &&
5201 "Can only indirectify direct input operands!");
5203 // Memory operands really want the address of the value. If we don't have
5204 // an indirect input, put it in the constpool if we can, otherwise spill
5205 // it to a stack slot.
5207 // If the operand is a float, integer, or vector constant, spill to a
5208 // constant pool entry to get its address.
5209 Value *OpVal = OpInfo.CallOperandVal;
5210 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5211 isa<ConstantVector>(OpVal)) {
5212 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5213 TLI.getPointerTy());
5214 } else {
5215 // Otherwise, create a stack slot and emit a store to it before the
5216 // asm.
5217 const Type *Ty = OpVal->getType();
5218 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5219 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5220 MachineFunction &MF = DAG.getMachineFunction();
5221 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5222 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5223 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5224 OpInfo.CallOperand, StackSlot, NULL, 0);
5225 OpInfo.CallOperand = StackSlot;
5228 // There is no longer a Value* corresponding to this operand.
5229 OpInfo.CallOperandVal = 0;
5230 // It is now an indirect operand.
5231 OpInfo.isIndirect = true;
5234 // If this constraint is for a specific register, allocate it before
5235 // anything else.
5236 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5237 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5239 ConstraintInfos.clear();
5242 // Second pass - Loop over all of the operands, assigning virtual or physregs
5243 // to register class operands.
5244 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5245 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5247 // C_Register operands have already been allocated, Other/Memory don't need
5248 // to be.
5249 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5250 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5253 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5254 std::vector<SDValue> AsmNodeOperands;
5255 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5256 AsmNodeOperands.push_back(
5257 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5260 // Loop over all of the inputs, copying the operand values into the
5261 // appropriate registers and processing the output regs.
5262 RegsForValue RetValRegs;
5264 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5265 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5267 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5268 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5270 switch (OpInfo.Type) {
5271 case InlineAsm::isOutput: {
5272 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5273 OpInfo.ConstraintType != TargetLowering::C_Register) {
5274 // Memory output, or 'other' output (e.g. 'X' constraint).
5275 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5277 // Add information to the INLINEASM node to know about this output.
5278 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5279 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5280 TLI.getPointerTy()));
5281 AsmNodeOperands.push_back(OpInfo.CallOperand);
5282 break;
5285 // Otherwise, this is a register or register class output.
5287 // Copy the output from the appropriate register. Find a register that
5288 // we can use.
5289 if (OpInfo.AssignedRegs.Regs.empty()) {
5290 llvm_report_error("Couldn't allocate output reg for"
5291 " constraint '" + OpInfo.ConstraintCode + "'!");
5294 // If this is an indirect operand, store through the pointer after the
5295 // asm.
5296 if (OpInfo.isIndirect) {
5297 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5298 OpInfo.CallOperandVal));
5299 } else {
5300 // This is the result value of the call.
5301 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5302 "Bad inline asm!");
5303 // Concatenate this output onto the outputs list.
5304 RetValRegs.append(OpInfo.AssignedRegs);
5307 // Add information to the INLINEASM node to know that this register is
5308 // set.
5309 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5310 6 /* EARLYCLOBBER REGDEF */ :
5311 2 /* REGDEF */ ,
5312 false,
5314 DAG, AsmNodeOperands);
5315 break;
5317 case InlineAsm::isInput: {
5318 SDValue InOperandVal = OpInfo.CallOperand;
5320 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5321 // If this is required to match an output register we have already set,
5322 // just use its register.
5323 unsigned OperandNo = OpInfo.getMatchedOperand();
5325 // Scan until we find the definition we already emitted of this operand.
5326 // When we find it, create a RegsForValue operand.
5327 unsigned CurOp = 2; // The first operand.
5328 for (; OperandNo; --OperandNo) {
5329 // Advance to the next operand.
5330 unsigned OpFlag =
5331 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5332 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5333 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5334 (OpFlag & 7) == 4 /*MEM*/) &&
5335 "Skipped past definitions?");
5336 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5339 unsigned OpFlag =
5340 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5341 if ((OpFlag & 7) == 2 /*REGDEF*/
5342 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5343 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5344 if (OpInfo.isIndirect) {
5345 llvm_report_error("Don't know how to handle tied indirect "
5346 "register inputs yet!");
5348 RegsForValue MatchedRegs;
5349 MatchedRegs.TLI = &TLI;
5350 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5351 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5352 MatchedRegs.RegVTs.push_back(RegVT);
5353 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5354 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5355 i != e; ++i)
5356 MatchedRegs.Regs.
5357 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5359 // Use the produced MatchedRegs object to
5360 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5361 Chain, &Flag);
5362 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5363 true, OpInfo.getMatchedOperand(),
5364 DAG, AsmNodeOperands);
5365 break;
5366 } else {
5367 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5368 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5369 "Unexpected number of operands");
5370 // Add information to the INLINEASM node to know about this input.
5371 // See InlineAsm.h isUseOperandTiedToDef.
5372 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5373 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5374 TLI.getPointerTy()));
5375 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5376 break;
5380 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5381 assert(!OpInfo.isIndirect &&
5382 "Don't know how to handle indirect other inputs yet!");
5384 std::vector<SDValue> Ops;
5385 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5386 hasMemory, Ops, DAG);
5387 if (Ops.empty()) {
5388 llvm_report_error("Invalid operand for inline asm"
5389 " constraint '" + OpInfo.ConstraintCode + "'!");
5392 // Add information to the INLINEASM node to know about this input.
5393 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5394 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5395 TLI.getPointerTy()));
5396 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5397 break;
5398 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5399 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5400 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5401 "Memory operands expect pointer values");
5403 // Add information to the INLINEASM node to know about this input.
5404 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5405 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5406 TLI.getPointerTy()));
5407 AsmNodeOperands.push_back(InOperandVal);
5408 break;
5411 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5412 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5413 "Unknown constraint type!");
5414 assert(!OpInfo.isIndirect &&
5415 "Don't know how to handle indirect register inputs yet!");
5417 // Copy the input into the appropriate registers.
5418 if (OpInfo.AssignedRegs.Regs.empty()) {
5419 llvm_report_error("Couldn't allocate input reg for"
5420 " constraint '"+ OpInfo.ConstraintCode +"'!");
5423 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5424 Chain, &Flag);
5426 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5427 DAG, AsmNodeOperands);
5428 break;
5430 case InlineAsm::isClobber: {
5431 // Add the clobbered value to the operand list, so that the register
5432 // allocator is aware that the physreg got clobbered.
5433 if (!OpInfo.AssignedRegs.Regs.empty())
5434 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5435 false, 0, DAG,AsmNodeOperands);
5436 break;
5441 // Finish up input operands.
5442 AsmNodeOperands[0] = Chain;
5443 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5445 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5446 DAG.getVTList(MVT::Other, MVT::Flag),
5447 &AsmNodeOperands[0], AsmNodeOperands.size());
5448 Flag = Chain.getValue(1);
5450 // If this asm returns a register value, copy the result from that register
5451 // and set it as the value of the call.
5452 if (!RetValRegs.Regs.empty()) {
5453 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5454 Chain, &Flag);
5456 // FIXME: Why don't we do this for inline asms with MRVs?
5457 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5458 EVT ResultType = TLI.getValueType(CS.getType());
5460 // If any of the results of the inline asm is a vector, it may have the
5461 // wrong width/num elts. This can happen for register classes that can
5462 // contain multiple different value types. The preg or vreg allocated may
5463 // not have the same VT as was expected. Convert it to the right type
5464 // with bit_convert.
5465 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5466 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5467 ResultType, Val);
5469 } else if (ResultType != Val.getValueType() &&
5470 ResultType.isInteger() && Val.getValueType().isInteger()) {
5471 // If a result value was tied to an input value, the computed result may
5472 // have a wider width than the expected result. Extract the relevant
5473 // portion.
5474 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5477 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5480 setValue(CS.getInstruction(), Val);
5481 // Don't need to use this as a chain in this case.
5482 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5483 return;
5486 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5488 // Process indirect outputs, first output all of the flagged copies out of
5489 // physregs.
5490 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5491 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5492 Value *Ptr = IndirectStoresToEmit[i].second;
5493 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5494 Chain, &Flag);
5495 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5499 // Emit the non-flagged stores from the physregs.
5500 SmallVector<SDValue, 8> OutChains;
5501 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5502 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5503 StoresToEmit[i].first,
5504 getValue(StoresToEmit[i].second),
5505 StoresToEmit[i].second, 0));
5506 if (!OutChains.empty())
5507 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5508 &OutChains[0], OutChains.size());
5509 DAG.setRoot(Chain);
5513 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5514 SDValue Src = getValue(I.getOperand(0));
5516 // Scale up by the type size in the original i32 type width. Various
5517 // mid-level optimizers may make assumptions about demanded bits etc from the
5518 // i32-ness of the optimizer: we do not want to promote to i64 and then
5519 // multiply on 64-bit targets.
5520 // FIXME: Malloc inst should go away: PR715.
5521 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5522 if (ElementSize != 1) {
5523 // Src is always 32-bits, make sure the constant fits.
5524 assert(Src.getValueType() == MVT::i32);
5525 ElementSize = (uint32_t)ElementSize;
5526 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5527 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5530 EVT IntPtr = TLI.getPointerTy();
5532 if (IntPtr.bitsLT(Src.getValueType()))
5533 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5534 else if (IntPtr.bitsGT(Src.getValueType()))
5535 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5537 TargetLowering::ArgListTy Args;
5538 TargetLowering::ArgListEntry Entry;
5539 Entry.Node = Src;
5540 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5541 Args.push_back(Entry);
5543 bool isTailCall = PerformTailCallOpt &&
5544 isInTailCallPosition(&I, Attribute::None, TLI);
5545 std::pair<SDValue,SDValue> Result =
5546 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5547 0, CallingConv::C, isTailCall,
5548 /*isReturnValueUsed=*/true,
5549 DAG.getExternalSymbol("malloc", IntPtr),
5550 Args, DAG, getCurDebugLoc());
5551 if (Result.first.getNode())
5552 setValue(&I, Result.first); // Pointers always fit in registers
5553 if (Result.second.getNode())
5554 DAG.setRoot(Result.second);
5557 void SelectionDAGLowering::visitFree(FreeInst &I) {
5558 TargetLowering::ArgListTy Args;
5559 TargetLowering::ArgListEntry Entry;
5560 Entry.Node = getValue(I.getOperand(0));
5561 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5562 Args.push_back(Entry);
5563 EVT IntPtr = TLI.getPointerTy();
5564 bool isTailCall = PerformTailCallOpt &&
5565 isInTailCallPosition(&I, Attribute::None, TLI);
5566 std::pair<SDValue,SDValue> Result =
5567 TLI.LowerCallTo(getRoot(), Type::getVoidTy(*DAG.getContext()),
5568 false, false, false, false,
5569 0, CallingConv::C, isTailCall,
5570 /*isReturnValueUsed=*/true,
5571 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5572 getCurDebugLoc());
5573 if (Result.second.getNode())
5574 DAG.setRoot(Result.second);
5577 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5578 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5579 MVT::Other, getRoot(),
5580 getValue(I.getOperand(1)),
5581 DAG.getSrcValue(I.getOperand(1))));
5584 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5585 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5586 getRoot(), getValue(I.getOperand(0)),
5587 DAG.getSrcValue(I.getOperand(0)));
5588 setValue(&I, V);
5589 DAG.setRoot(V.getValue(1));
5592 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5593 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5594 MVT::Other, getRoot(),
5595 getValue(I.getOperand(1)),
5596 DAG.getSrcValue(I.getOperand(1))));
5599 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5600 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5601 MVT::Other, getRoot(),
5602 getValue(I.getOperand(1)),
5603 getValue(I.getOperand(2)),
5604 DAG.getSrcValue(I.getOperand(1)),
5605 DAG.getSrcValue(I.getOperand(2))));
5608 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5609 /// implementation, which just calls LowerCall.
5610 /// FIXME: When all targets are
5611 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5612 std::pair<SDValue, SDValue>
5613 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5614 bool RetSExt, bool RetZExt, bool isVarArg,
5615 bool isInreg, unsigned NumFixedArgs,
5616 unsigned CallConv, bool isTailCall,
5617 bool isReturnValueUsed,
5618 SDValue Callee,
5619 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5621 assert((!isTailCall || PerformTailCallOpt) &&
5622 "isTailCall set when tail-call optimizations are disabled!");
5624 // Handle all of the outgoing arguments.
5625 SmallVector<ISD::OutputArg, 32> Outs;
5626 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5627 SmallVector<EVT, 4> ValueVTs;
5628 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5629 for (unsigned Value = 0, NumValues = ValueVTs.size();
5630 Value != NumValues; ++Value) {
5631 EVT VT = ValueVTs[Value];
5632 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5633 SDValue Op = SDValue(Args[i].Node.getNode(),
5634 Args[i].Node.getResNo() + Value);
5635 ISD::ArgFlagsTy Flags;
5636 unsigned OriginalAlignment =
5637 getTargetData()->getABITypeAlignment(ArgTy);
5639 if (Args[i].isZExt)
5640 Flags.setZExt();
5641 if (Args[i].isSExt)
5642 Flags.setSExt();
5643 if (Args[i].isInReg)
5644 Flags.setInReg();
5645 if (Args[i].isSRet)
5646 Flags.setSRet();
5647 if (Args[i].isByVal) {
5648 Flags.setByVal();
5649 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5650 const Type *ElementTy = Ty->getElementType();
5651 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5652 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5653 // For ByVal, alignment should come from FE. BE will guess if this
5654 // info is not there but there are cases it cannot get right.
5655 if (Args[i].Alignment)
5656 FrameAlign = Args[i].Alignment;
5657 Flags.setByValAlign(FrameAlign);
5658 Flags.setByValSize(FrameSize);
5660 if (Args[i].isNest)
5661 Flags.setNest();
5662 Flags.setOrigAlign(OriginalAlignment);
5664 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5665 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5666 SmallVector<SDValue, 4> Parts(NumParts);
5667 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5669 if (Args[i].isSExt)
5670 ExtendKind = ISD::SIGN_EXTEND;
5671 else if (Args[i].isZExt)
5672 ExtendKind = ISD::ZERO_EXTEND;
5674 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5676 for (unsigned j = 0; j != NumParts; ++j) {
5677 // if it isn't first piece, alignment must be 1
5678 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5679 if (NumParts > 1 && j == 0)
5680 MyFlags.Flags.setSplit();
5681 else if (j != 0)
5682 MyFlags.Flags.setOrigAlign(1);
5684 Outs.push_back(MyFlags);
5689 // Handle the incoming return values from the call.
5690 SmallVector<ISD::InputArg, 32> Ins;
5691 SmallVector<EVT, 4> RetTys;
5692 ComputeValueVTs(*this, RetTy, RetTys);
5693 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5694 EVT VT = RetTys[I];
5695 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5696 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5697 for (unsigned i = 0; i != NumRegs; ++i) {
5698 ISD::InputArg MyFlags;
5699 MyFlags.VT = RegisterVT;
5700 MyFlags.Used = isReturnValueUsed;
5701 if (RetSExt)
5702 MyFlags.Flags.setSExt();
5703 if (RetZExt)
5704 MyFlags.Flags.setZExt();
5705 if (isInreg)
5706 MyFlags.Flags.setInReg();
5707 Ins.push_back(MyFlags);
5711 // Check if target-dependent constraints permit a tail call here.
5712 // Target-independent constraints should be checked by the caller.
5713 if (isTailCall &&
5714 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5715 isTailCall = false;
5717 SmallVector<SDValue, 4> InVals;
5718 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5719 Outs, Ins, dl, DAG, InVals);
5721 // Verify that the target's LowerCall behaved as expected.
5722 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5723 "LowerCall didn't return a valid chain!");
5724 assert((!isTailCall || InVals.empty()) &&
5725 "LowerCall emitted a return value for a tail call!");
5726 assert((isTailCall || InVals.size() == Ins.size()) &&
5727 "LowerCall didn't emit the correct number of values!");
5728 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5729 assert(InVals[i].getNode() &&
5730 "LowerCall emitted a null value!");
5731 assert(Ins[i].VT == InVals[i].getValueType() &&
5732 "LowerCall emitted a value with the wrong type!");
5735 // For a tail call, the return value is merely live-out and there aren't
5736 // any nodes in the DAG representing it. Return a special value to
5737 // indicate that a tail call has been emitted and no more Instructions
5738 // should be processed in the current block.
5739 if (isTailCall) {
5740 DAG.setRoot(Chain);
5741 return std::make_pair(SDValue(), SDValue());
5744 // Collect the legal value parts into potentially illegal values
5745 // that correspond to the original function's return values.
5746 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5747 if (RetSExt)
5748 AssertOp = ISD::AssertSext;
5749 else if (RetZExt)
5750 AssertOp = ISD::AssertZext;
5751 SmallVector<SDValue, 4> ReturnValues;
5752 unsigned CurReg = 0;
5753 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5754 EVT VT = RetTys[I];
5755 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5756 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5758 SDValue ReturnValue =
5759 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5760 AssertOp);
5761 ReturnValues.push_back(ReturnValue);
5762 CurReg += NumRegs;
5765 // For a function returning void, there is no return value. We can't create
5766 // such a node, so we just return a null return value in that case. In
5767 // that case, nothing will actualy look at the value.
5768 if (ReturnValues.empty())
5769 return std::make_pair(SDValue(), Chain);
5771 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5772 DAG.getVTList(&RetTys[0], RetTys.size()),
5773 &ReturnValues[0], ReturnValues.size());
5775 return std::make_pair(Res, Chain);
5778 void TargetLowering::LowerOperationWrapper(SDNode *N,
5779 SmallVectorImpl<SDValue> &Results,
5780 SelectionDAG &DAG) {
5781 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5782 if (Res.getNode())
5783 Results.push_back(Res);
5786 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5787 llvm_unreachable("LowerOperation not implemented for this target!");
5788 return SDValue();
5792 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5793 SDValue Op = getValue(V);
5794 assert((Op.getOpcode() != ISD::CopyFromReg ||
5795 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5796 "Copy from a reg to the same reg!");
5797 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5799 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5800 SDValue Chain = DAG.getEntryNode();
5801 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5802 PendingExports.push_back(Chain);
5805 #include "llvm/CodeGen/SelectionDAGISel.h"
5807 void SelectionDAGISel::
5808 LowerArguments(BasicBlock *LLVMBB) {
5809 // If this is the entry block, emit arguments.
5810 Function &F = *LLVMBB->getParent();
5811 SelectionDAG &DAG = SDL->DAG;
5812 SDValue OldRoot = DAG.getRoot();
5813 DebugLoc dl = SDL->getCurDebugLoc();
5814 const TargetData *TD = TLI.getTargetData();
5816 // Set up the incoming argument description vector.
5817 SmallVector<ISD::InputArg, 16> Ins;
5818 unsigned Idx = 1;
5819 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5820 I != E; ++I, ++Idx) {
5821 SmallVector<EVT, 4> ValueVTs;
5822 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5823 bool isArgValueUsed = !I->use_empty();
5824 for (unsigned Value = 0, NumValues = ValueVTs.size();
5825 Value != NumValues; ++Value) {
5826 EVT VT = ValueVTs[Value];
5827 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5828 ISD::ArgFlagsTy Flags;
5829 unsigned OriginalAlignment =
5830 TD->getABITypeAlignment(ArgTy);
5832 if (F.paramHasAttr(Idx, Attribute::ZExt))
5833 Flags.setZExt();
5834 if (F.paramHasAttr(Idx, Attribute::SExt))
5835 Flags.setSExt();
5836 if (F.paramHasAttr(Idx, Attribute::InReg))
5837 Flags.setInReg();
5838 if (F.paramHasAttr(Idx, Attribute::StructRet))
5839 Flags.setSRet();
5840 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5841 Flags.setByVal();
5842 const PointerType *Ty = cast<PointerType>(I->getType());
5843 const Type *ElementTy = Ty->getElementType();
5844 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5845 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5846 // For ByVal, alignment should be passed from FE. BE will guess if
5847 // this info is not there but there are cases it cannot get right.
5848 if (F.getParamAlignment(Idx))
5849 FrameAlign = F.getParamAlignment(Idx);
5850 Flags.setByValAlign(FrameAlign);
5851 Flags.setByValSize(FrameSize);
5853 if (F.paramHasAttr(Idx, Attribute::Nest))
5854 Flags.setNest();
5855 Flags.setOrigAlign(OriginalAlignment);
5857 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5858 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5859 for (unsigned i = 0; i != NumRegs; ++i) {
5860 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5861 if (NumRegs > 1 && i == 0)
5862 MyFlags.Flags.setSplit();
5863 // if it isn't first piece, alignment must be 1
5864 else if (i > 0)
5865 MyFlags.Flags.setOrigAlign(1);
5866 Ins.push_back(MyFlags);
5871 // Call the target to set up the argument values.
5872 SmallVector<SDValue, 8> InVals;
5873 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5874 F.isVarArg(), Ins,
5875 dl, DAG, InVals);
5877 // Verify that the target's LowerFormalArguments behaved as expected.
5878 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5879 "LowerFormalArguments didn't return a valid chain!");
5880 assert(InVals.size() == Ins.size() &&
5881 "LowerFormalArguments didn't emit the correct number of values!");
5882 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5883 assert(InVals[i].getNode() &&
5884 "LowerFormalArguments emitted a null value!");
5885 assert(Ins[i].VT == InVals[i].getValueType() &&
5886 "LowerFormalArguments emitted a value with the wrong type!");
5889 // Update the DAG with the new chain value resulting from argument lowering.
5890 DAG.setRoot(NewRoot);
5892 // Set up the argument values.
5893 unsigned i = 0;
5894 Idx = 1;
5895 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5896 ++I, ++Idx) {
5897 SmallVector<SDValue, 4> ArgValues;
5898 SmallVector<EVT, 4> ValueVTs;
5899 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5900 unsigned NumValues = ValueVTs.size();
5901 for (unsigned Value = 0; Value != NumValues; ++Value) {
5902 EVT VT = ValueVTs[Value];
5903 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5904 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5906 if (!I->use_empty()) {
5907 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5908 if (F.paramHasAttr(Idx, Attribute::SExt))
5909 AssertOp = ISD::AssertSext;
5910 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5911 AssertOp = ISD::AssertZext;
5913 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5914 PartVT, VT, AssertOp));
5916 i += NumParts;
5918 if (!I->use_empty()) {
5919 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5920 SDL->getCurDebugLoc()));
5921 // If this argument is live outside of the entry block, insert a copy from
5922 // whereever we got it to the vreg that other BB's will reference it as.
5923 SDL->CopyToExportRegsIfNeeded(I);
5926 assert(i == InVals.size() && "Argument register count mismatch!");
5928 // Finally, if the target has anything special to do, allow it to do so.
5929 // FIXME: this should insert code into the DAG!
5930 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5933 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5934 /// ensure constants are generated when needed. Remember the virtual registers
5935 /// that need to be added to the Machine PHI nodes as input. We cannot just
5936 /// directly add them, because expansion might result in multiple MBB's for one
5937 /// BB. As such, the start of the BB might correspond to a different MBB than
5938 /// the end.
5940 void
5941 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5942 TerminatorInst *TI = LLVMBB->getTerminator();
5944 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5946 // Check successor nodes' PHI nodes that expect a constant to be available
5947 // from this block.
5948 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5949 BasicBlock *SuccBB = TI->getSuccessor(succ);
5950 if (!isa<PHINode>(SuccBB->begin())) continue;
5951 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5953 // If this terminator has multiple identical successors (common for
5954 // switches), only handle each succ once.
5955 if (!SuccsHandled.insert(SuccMBB)) continue;
5957 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5958 PHINode *PN;
5960 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5961 // nodes and Machine PHI nodes, but the incoming operands have not been
5962 // emitted yet.
5963 for (BasicBlock::iterator I = SuccBB->begin();
5964 (PN = dyn_cast<PHINode>(I)); ++I) {
5965 // Ignore dead phi's.
5966 if (PN->use_empty()) continue;
5968 unsigned Reg;
5969 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5971 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5972 unsigned &RegOut = SDL->ConstantsOut[C];
5973 if (RegOut == 0) {
5974 RegOut = FuncInfo->CreateRegForValue(C);
5975 SDL->CopyValueToVirtualRegister(C, RegOut);
5977 Reg = RegOut;
5978 } else {
5979 Reg = FuncInfo->ValueMap[PHIOp];
5980 if (Reg == 0) {
5981 assert(isa<AllocaInst>(PHIOp) &&
5982 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5983 "Didn't codegen value into a register!??");
5984 Reg = FuncInfo->CreateRegForValue(PHIOp);
5985 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5989 // Remember that this register needs to added to the machine PHI node as
5990 // the input for this MBB.
5991 SmallVector<EVT, 4> ValueVTs;
5992 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5993 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5994 EVT VT = ValueVTs[vti];
5995 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5996 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5997 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5998 Reg += NumRegisters;
6002 SDL->ConstantsOut.clear();
6005 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6006 /// supports legal types, and it emits MachineInstrs directly instead of
6007 /// creating SelectionDAG nodes.
6009 bool
6010 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6011 FastISel *F) {
6012 TerminatorInst *TI = LLVMBB->getTerminator();
6014 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6015 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6017 // Check successor nodes' PHI nodes that expect a constant to be available
6018 // from this block.
6019 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6020 BasicBlock *SuccBB = TI->getSuccessor(succ);
6021 if (!isa<PHINode>(SuccBB->begin())) continue;
6022 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6024 // If this terminator has multiple identical successors (common for
6025 // switches), only handle each succ once.
6026 if (!SuccsHandled.insert(SuccMBB)) continue;
6028 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6029 PHINode *PN;
6031 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6032 // nodes and Machine PHI nodes, but the incoming operands have not been
6033 // emitted yet.
6034 for (BasicBlock::iterator I = SuccBB->begin();
6035 (PN = dyn_cast<PHINode>(I)); ++I) {
6036 // Ignore dead phi's.
6037 if (PN->use_empty()) continue;
6039 // Only handle legal types. Two interesting things to note here. First,
6040 // by bailing out early, we may leave behind some dead instructions,
6041 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6042 // own moves. Second, this check is necessary becuase FastISel doesn't
6043 // use CreateRegForValue to create registers, so it always creates
6044 // exactly one register for each non-void instruction.
6045 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6046 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6047 // Promote MVT::i1.
6048 if (VT == MVT::i1)
6049 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6050 else {
6051 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6052 return false;
6056 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6058 unsigned Reg = F->getRegForValue(PHIOp);
6059 if (Reg == 0) {
6060 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6061 return false;
6063 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
6067 return true;