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Change allowsUnalignedMemoryAccesses to take type argument since some targets
[llvm/avr.git] / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob3414fee7d4dadc13fe643954d31472035130b2c5
1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetAsmInfo.h"
16 #include "llvm/Target/TargetData.h"
17 #include "llvm/Target/TargetLoweringObjectFile.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/Target/TargetSubtarget.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/MathExtras.h"
29 using namespace llvm;
30
31 namespace llvm {
32 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
33 bool isLocal = GV->hasLocalLinkage();
34 bool isDeclaration = GV->isDeclaration();
35 // FIXME: what should we do for protected and internal visibility?
36 // For variables, is internal different from hidden?
37 bool isHidden = GV->hasHiddenVisibility();
38
39 if (reloc == Reloc::PIC_) {
40 if (isLocal || isHidden)
41 return TLSModel::LocalDynamic;
42 else
43 return TLSModel::GeneralDynamic;
44 } else {
45 if (!isDeclaration || isHidden)
46 return TLSModel::LocalExec;
47 else
48 return TLSModel::InitialExec;
49 }
50 }
51 }
52
53 /// InitLibcallNames - Set default libcall names.
54 ///
55 static void InitLibcallNames(const char **Names) {
56 Names[RTLIB::SHL_I16] = "__ashlhi3";
57 Names[RTLIB::SHL_I32] = "__ashlsi3";
58 Names[RTLIB::SHL_I64] = "__ashldi3";
59 Names[RTLIB::SHL_I128] = "__ashlti3";
60 Names[RTLIB::SRL_I16] = "__lshrhi3";
61 Names[RTLIB::SRL_I32] = "__lshrsi3";
62 Names[RTLIB::SRL_I64] = "__lshrdi3";
63 Names[RTLIB::SRL_I128] = "__lshrti3";
64 Names[RTLIB::SRA_I16] = "__ashrhi3";
65 Names[RTLIB::SRA_I32] = "__ashrsi3";
66 Names[RTLIB::SRA_I64] = "__ashrdi3";
67 Names[RTLIB::SRA_I128] = "__ashrti3";
68 Names[RTLIB::MUL_I16] = "__mulhi3";
69 Names[RTLIB::MUL_I32] = "__mulsi3";
70 Names[RTLIB::MUL_I64] = "__muldi3";
71 Names[RTLIB::MUL_I128] = "__multi3";
72 Names[RTLIB::SDIV_I16] = "__divhi3";
73 Names[RTLIB::SDIV_I32] = "__divsi3";
74 Names[RTLIB::SDIV_I64] = "__divdi3";
75 Names[RTLIB::SDIV_I128] = "__divti3";
76 Names[RTLIB::UDIV_I16] = "__udivhi3";
77 Names[RTLIB::UDIV_I32] = "__udivsi3";
78 Names[RTLIB::UDIV_I64] = "__udivdi3";
79 Names[RTLIB::UDIV_I128] = "__udivti3";
80 Names[RTLIB::SREM_I16] = "__modhi3";
81 Names[RTLIB::SREM_I32] = "__modsi3";
82 Names[RTLIB::SREM_I64] = "__moddi3";
83 Names[RTLIB::SREM_I128] = "__modti3";
84 Names[RTLIB::UREM_I16] = "__umodhi3";
85 Names[RTLIB::UREM_I32] = "__umodsi3";
86 Names[RTLIB::UREM_I64] = "__umoddi3";
87 Names[RTLIB::UREM_I128] = "__umodti3";
88 Names[RTLIB::NEG_I32] = "__negsi2";
89 Names[RTLIB::NEG_I64] = "__negdi2";
90 Names[RTLIB::ADD_F32] = "__addsf3";
91 Names[RTLIB::ADD_F64] = "__adddf3";
92 Names[RTLIB::ADD_F80] = "__addxf3";
93 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
94 Names[RTLIB::SUB_F32] = "__subsf3";
95 Names[RTLIB::SUB_F64] = "__subdf3";
96 Names[RTLIB::SUB_F80] = "__subxf3";
97 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
98 Names[RTLIB::MUL_F32] = "__mulsf3";
99 Names[RTLIB::MUL_F64] = "__muldf3";
100 Names[RTLIB::MUL_F80] = "__mulxf3";
101 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
102 Names[RTLIB::DIV_F32] = "__divsf3";
103 Names[RTLIB::DIV_F64] = "__divdf3";
104 Names[RTLIB::DIV_F80] = "__divxf3";
105 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
106 Names[RTLIB::REM_F32] = "fmodf";
107 Names[RTLIB::REM_F64] = "fmod";
108 Names[RTLIB::REM_F80] = "fmodl";
109 Names[RTLIB::REM_PPCF128] = "fmodl";
110 Names[RTLIB::POWI_F32] = "__powisf2";
111 Names[RTLIB::POWI_F64] = "__powidf2";
112 Names[RTLIB::POWI_F80] = "__powixf2";
113 Names[RTLIB::POWI_PPCF128] = "__powitf2";
114 Names[RTLIB::SQRT_F32] = "sqrtf";
115 Names[RTLIB::SQRT_F64] = "sqrt";
116 Names[RTLIB::SQRT_F80] = "sqrtl";
117 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
118 Names[RTLIB::LOG_F32] = "logf";
119 Names[RTLIB::LOG_F64] = "log";
120 Names[RTLIB::LOG_F80] = "logl";
121 Names[RTLIB::LOG_PPCF128] = "logl";
122 Names[RTLIB::LOG2_F32] = "log2f";
123 Names[RTLIB::LOG2_F64] = "log2";
124 Names[RTLIB::LOG2_F80] = "log2l";
125 Names[RTLIB::LOG2_PPCF128] = "log2l";
126 Names[RTLIB::LOG10_F32] = "log10f";
127 Names[RTLIB::LOG10_F64] = "log10";
128 Names[RTLIB::LOG10_F80] = "log10l";
129 Names[RTLIB::LOG10_PPCF128] = "log10l";
130 Names[RTLIB::EXP_F32] = "expf";
131 Names[RTLIB::EXP_F64] = "exp";
132 Names[RTLIB::EXP_F80] = "expl";
133 Names[RTLIB::EXP_PPCF128] = "expl";
134 Names[RTLIB::EXP2_F32] = "exp2f";
135 Names[RTLIB::EXP2_F64] = "exp2";
136 Names[RTLIB::EXP2_F80] = "exp2l";
137 Names[RTLIB::EXP2_PPCF128] = "exp2l";
138 Names[RTLIB::SIN_F32] = "sinf";
139 Names[RTLIB::SIN_F64] = "sin";
140 Names[RTLIB::SIN_F80] = "sinl";
141 Names[RTLIB::SIN_PPCF128] = "sinl";
142 Names[RTLIB::COS_F32] = "cosf";
143 Names[RTLIB::COS_F64] = "cos";
144 Names[RTLIB::COS_F80] = "cosl";
145 Names[RTLIB::COS_PPCF128] = "cosl";
146 Names[RTLIB::POW_F32] = "powf";
147 Names[RTLIB::POW_F64] = "pow";
148 Names[RTLIB::POW_F80] = "powl";
149 Names[RTLIB::POW_PPCF128] = "powl";
150 Names[RTLIB::CEIL_F32] = "ceilf";
151 Names[RTLIB::CEIL_F64] = "ceil";
152 Names[RTLIB::CEIL_F80] = "ceill";
153 Names[RTLIB::CEIL_PPCF128] = "ceill";
154 Names[RTLIB::TRUNC_F32] = "truncf";
155 Names[RTLIB::TRUNC_F64] = "trunc";
156 Names[RTLIB::TRUNC_F80] = "truncl";
157 Names[RTLIB::TRUNC_PPCF128] = "truncl";
158 Names[RTLIB::RINT_F32] = "rintf";
159 Names[RTLIB::RINT_F64] = "rint";
160 Names[RTLIB::RINT_F80] = "rintl";
161 Names[RTLIB::RINT_PPCF128] = "rintl";
162 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
163 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
164 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
165 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
166 Names[RTLIB::FLOOR_F32] = "floorf";
167 Names[RTLIB::FLOOR_F64] = "floor";
168 Names[RTLIB::FLOOR_F80] = "floorl";
169 Names[RTLIB::FLOOR_PPCF128] = "floorl";
170 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
171 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
172 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
173 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
174 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
175 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
176 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
177 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
178 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
179 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
180 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
181 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
182 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
183 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
184 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
185 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
186 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
187 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
188 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
189 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
190 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
191 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
192 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
193 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
194 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
195 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
196 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
197 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
198 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
199 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
200 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
201 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
202 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
203 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
204 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
205 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
206 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
207 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
208 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
209 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
210 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
211 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
212 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
213 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
214 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
215 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
216 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
217 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
218 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
219 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
220 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
221 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
222 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
223 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
224 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
225 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
226 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
227 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
228 Names[RTLIB::OEQ_F32] = "__eqsf2";
229 Names[RTLIB::OEQ_F64] = "__eqdf2";
230 Names[RTLIB::UNE_F32] = "__nesf2";
231 Names[RTLIB::UNE_F64] = "__nedf2";
232 Names[RTLIB::OGE_F32] = "__gesf2";
233 Names[RTLIB::OGE_F64] = "__gedf2";
234 Names[RTLIB::OLT_F32] = "__ltsf2";
235 Names[RTLIB::OLT_F64] = "__ltdf2";
236 Names[RTLIB::OLE_F32] = "__lesf2";
237 Names[RTLIB::OLE_F64] = "__ledf2";
238 Names[RTLIB::OGT_F32] = "__gtsf2";
239 Names[RTLIB::OGT_F64] = "__gtdf2";
240 Names[RTLIB::UO_F32] = "__unordsf2";
241 Names[RTLIB::UO_F64] = "__unorddf2";
242 Names[RTLIB::O_F32] = "__unordsf2";
243 Names[RTLIB::O_F64] = "__unorddf2";
244 Names[RTLIB::MEMCPY] = "memcpy";
245 Names[RTLIB::MEMMOVE] = "memmove";
246 Names[RTLIB::MEMSET] = "memset";
247 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
248 }
249
250 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
251 ///
252 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
253 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
254 CCs[i] = CallingConv::C;
255 }
256 }
257
258 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
259 /// UNKNOWN_LIBCALL if there is none.
260 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
261 if (OpVT == MVT::f32) {
262 if (RetVT == MVT::f64)
263 return FPEXT_F32_F64;
264 }
265 return UNKNOWN_LIBCALL;
266 }
267
268 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
269 /// UNKNOWN_LIBCALL if there is none.
270 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
271 if (RetVT == MVT::f32) {
272 if (OpVT == MVT::f64)
273 return FPROUND_F64_F32;
274 if (OpVT == MVT::f80)
275 return FPROUND_F80_F32;
276 if (OpVT == MVT::ppcf128)
277 return FPROUND_PPCF128_F32;
278 } else if (RetVT == MVT::f64) {
279 if (OpVT == MVT::f80)
280 return FPROUND_F80_F64;
281 if (OpVT == MVT::ppcf128)
282 return FPROUND_PPCF128_F64;
283 }
284 return UNKNOWN_LIBCALL;
285 }
286
287 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
288 /// UNKNOWN_LIBCALL if there is none.
289 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
290 if (OpVT == MVT::f32) {
291 if (RetVT == MVT::i8)
292 return FPTOSINT_F32_I8;
293 if (RetVT == MVT::i16)
294 return FPTOSINT_F32_I16;
295 if (RetVT == MVT::i32)
296 return FPTOSINT_F32_I32;
297 if (RetVT == MVT::i64)
298 return FPTOSINT_F32_I64;
299 if (RetVT == MVT::i128)
300 return FPTOSINT_F32_I128;
301 } else if (OpVT == MVT::f64) {
302 if (RetVT == MVT::i32)
303 return FPTOSINT_F64_I32;
304 if (RetVT == MVT::i64)
305 return FPTOSINT_F64_I64;
306 if (RetVT == MVT::i128)
307 return FPTOSINT_F64_I128;
308 } else if (OpVT == MVT::f80) {
309 if (RetVT == MVT::i32)
310 return FPTOSINT_F80_I32;
311 if (RetVT == MVT::i64)
312 return FPTOSINT_F80_I64;
313 if (RetVT == MVT::i128)
314 return FPTOSINT_F80_I128;
315 } else if (OpVT == MVT::ppcf128) {
316 if (RetVT == MVT::i32)
317 return FPTOSINT_PPCF128_I32;
318 if (RetVT == MVT::i64)
319 return FPTOSINT_PPCF128_I64;
320 if (RetVT == MVT::i128)
321 return FPTOSINT_PPCF128_I128;
322 }
323 return UNKNOWN_LIBCALL;
324 }
325
326 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
327 /// UNKNOWN_LIBCALL if there is none.
328 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
329 if (OpVT == MVT::f32) {
330 if (RetVT == MVT::i8)
331 return FPTOUINT_F32_I8;
332 if (RetVT == MVT::i16)
333 return FPTOUINT_F32_I16;
334 if (RetVT == MVT::i32)
335 return FPTOUINT_F32_I32;
336 if (RetVT == MVT::i64)
337 return FPTOUINT_F32_I64;
338 if (RetVT == MVT::i128)
339 return FPTOUINT_F32_I128;
340 } else if (OpVT == MVT::f64) {
341 if (RetVT == MVT::i32)
342 return FPTOUINT_F64_I32;
343 if (RetVT == MVT::i64)
344 return FPTOUINT_F64_I64;
345 if (RetVT == MVT::i128)
346 return FPTOUINT_F64_I128;
347 } else if (OpVT == MVT::f80) {
348 if (RetVT == MVT::i32)
349 return FPTOUINT_F80_I32;
350 if (RetVT == MVT::i64)
351 return FPTOUINT_F80_I64;
352 if (RetVT == MVT::i128)
353 return FPTOUINT_F80_I128;
354 } else if (OpVT == MVT::ppcf128) {
355 if (RetVT == MVT::i32)
356 return FPTOUINT_PPCF128_I32;
357 if (RetVT == MVT::i64)
358 return FPTOUINT_PPCF128_I64;
359 if (RetVT == MVT::i128)
360 return FPTOUINT_PPCF128_I128;
361 }
362 return UNKNOWN_LIBCALL;
363 }
364
365 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
366 /// UNKNOWN_LIBCALL if there is none.
367 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
368 if (OpVT == MVT::i32) {
369 if (RetVT == MVT::f32)
370 return SINTTOFP_I32_F32;
371 else if (RetVT == MVT::f64)
372 return SINTTOFP_I32_F64;
373 else if (RetVT == MVT::f80)
374 return SINTTOFP_I32_F80;
375 else if (RetVT == MVT::ppcf128)
376 return SINTTOFP_I32_PPCF128;
377 } else if (OpVT == MVT::i64) {
378 if (RetVT == MVT::f32)
379 return SINTTOFP_I64_F32;
380 else if (RetVT == MVT::f64)
381 return SINTTOFP_I64_F64;
382 else if (RetVT == MVT::f80)
383 return SINTTOFP_I64_F80;
384 else if (RetVT == MVT::ppcf128)
385 return SINTTOFP_I64_PPCF128;
386 } else if (OpVT == MVT::i128) {
387 if (RetVT == MVT::f32)
388 return SINTTOFP_I128_F32;
389 else if (RetVT == MVT::f64)
390 return SINTTOFP_I128_F64;
391 else if (RetVT == MVT::f80)
392 return SINTTOFP_I128_F80;
393 else if (RetVT == MVT::ppcf128)
394 return SINTTOFP_I128_PPCF128;
395 }
396 return UNKNOWN_LIBCALL;
397 }
398
399 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
400 /// UNKNOWN_LIBCALL if there is none.
401 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
402 if (OpVT == MVT::i32) {
403 if (RetVT == MVT::f32)
404 return UINTTOFP_I32_F32;
405 else if (RetVT == MVT::f64)
406 return UINTTOFP_I32_F64;
407 else if (RetVT == MVT::f80)
408 return UINTTOFP_I32_F80;
409 else if (RetVT == MVT::ppcf128)
410 return UINTTOFP_I32_PPCF128;
411 } else if (OpVT == MVT::i64) {
412 if (RetVT == MVT::f32)
413 return UINTTOFP_I64_F32;
414 else if (RetVT == MVT::f64)
415 return UINTTOFP_I64_F64;
416 else if (RetVT == MVT::f80)
417 return UINTTOFP_I64_F80;
418 else if (RetVT == MVT::ppcf128)
419 return UINTTOFP_I64_PPCF128;
420 } else if (OpVT == MVT::i128) {
421 if (RetVT == MVT::f32)
422 return UINTTOFP_I128_F32;
423 else if (RetVT == MVT::f64)
424 return UINTTOFP_I128_F64;
425 else if (RetVT == MVT::f80)
426 return UINTTOFP_I128_F80;
427 else if (RetVT == MVT::ppcf128)
428 return UINTTOFP_I128_PPCF128;
429 }
430 return UNKNOWN_LIBCALL;
431 }
432
433 /// InitCmpLibcallCCs - Set default comparison libcall CC.
434 ///
435 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
436 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
437 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
438 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
439 CCs[RTLIB::UNE_F32] = ISD::SETNE;
440 CCs[RTLIB::UNE_F64] = ISD::SETNE;
441 CCs[RTLIB::OGE_F32] = ISD::SETGE;
442 CCs[RTLIB::OGE_F64] = ISD::SETGE;
443 CCs[RTLIB::OLT_F32] = ISD::SETLT;
444 CCs[RTLIB::OLT_F64] = ISD::SETLT;
445 CCs[RTLIB::OLE_F32] = ISD::SETLE;
446 CCs[RTLIB::OLE_F64] = ISD::SETLE;
447 CCs[RTLIB::OGT_F32] = ISD::SETGT;
448 CCs[RTLIB::OGT_F64] = ISD::SETGT;
449 CCs[RTLIB::UO_F32] = ISD::SETNE;
450 CCs[RTLIB::UO_F64] = ISD::SETNE;
451 CCs[RTLIB::O_F32] = ISD::SETEQ;
452 CCs[RTLIB::O_F64] = ISD::SETEQ;
453 }
454
455 /// NOTE: The constructor takes ownership of TLOF.
456 TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
457 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
458 // All operations default to being supported.
459 memset(OpActions, 0, sizeof(OpActions));
460 memset(LoadExtActions, 0, sizeof(LoadExtActions));
461 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
462 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
463 memset(ConvertActions, 0, sizeof(ConvertActions));
464 memset(CondCodeActions, 0, sizeof(CondCodeActions));
465
466 // Set default actions for various operations.
467 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
468 // Default all indexed load / store to expand.
469 for (unsigned IM = (unsigned)ISD::PRE_INC;
470 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
471 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
472 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
473 }
474
475 // These operations default to expand.
476 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
477 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
478 }
479
480 // Most targets ignore the @llvm.prefetch intrinsic.
481 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
482
483 // ConstantFP nodes default to expand. Targets can either change this to
484 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
485 // to optimize expansions for certain constants.
486 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
487 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
488 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
489
490 // These library functions default to expand.
491 setOperationAction(ISD::FLOG , MVT::f64, Expand);
492 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
493 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
494 setOperationAction(ISD::FEXP , MVT::f64, Expand);
495 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
496 setOperationAction(ISD::FLOG , MVT::f32, Expand);
497 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
498 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
499 setOperationAction(ISD::FEXP , MVT::f32, Expand);
500 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
501
502 // Default ISD::TRAP to expand (which turns it into abort).
503 setOperationAction(ISD::TRAP, MVT::Other, Expand);
504
505 IsLittleEndian = TD->isLittleEndian();
506 UsesGlobalOffsetTable = false;
507 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
508 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
509 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
510 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
511 allowUnalignedMemoryAccesses = false;
512 benefitFromCodePlacementOpt = false;
513 UseUnderscoreSetJmp = false;
514 UseUnderscoreLongJmp = false;
515 SelectIsExpensive = false;
516 IntDivIsCheap = false;
517 Pow2DivIsCheap = false;
518 StackPointerRegisterToSaveRestore = 0;
519 ExceptionPointerRegister = 0;
520 ExceptionSelectorRegister = 0;
521 BooleanContents = UndefinedBooleanContent;
522 SchedPreferenceInfo = SchedulingForLatency;
523 JumpBufSize = 0;
524 JumpBufAlignment = 0;
525 IfCvtBlockSizeLimit = 2;
526 IfCvtDupBlockSizeLimit = 0;
527 PrefLoopAlignment = 0;
528
529 InitLibcallNames(LibcallRoutineNames);
530 InitCmpLibcallCCs(CmpLibcallCCs);
531 InitLibcallCallingConvs(LibcallCallingConvs);
532
533 // Tell Legalize whether the assembler supports DEBUG_LOC.
534 const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
535 if (!TASM || !TASM->hasDotLocAndDotFile())
536 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
537 }
538
539 TargetLowering::~TargetLowering() {
540 delete &TLOF;
541 }
542
543 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
544 unsigned &NumIntermediates,
545 EVT &RegisterVT,
546 TargetLowering* TLI) {
547 // Figure out the right, legal destination reg to copy into.
548 unsigned NumElts = VT.getVectorNumElements();
549 MVT EltTy = VT.getVectorElementType();
550
551 unsigned NumVectorRegs = 1;
552
553 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
554 // could break down into LHS/RHS like LegalizeDAG does.
555 if (!isPowerOf2_32(NumElts)) {
556 NumVectorRegs = NumElts;
557 NumElts = 1;
558 }
559
560 // Divide the input until we get to a supported size. This will always
561 // end with a scalar if the target doesn't support vectors.
562 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
563 NumElts >>= 1;
564 NumVectorRegs <<= 1;
565 }
566
567 NumIntermediates = NumVectorRegs;
568
569 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
570 if (!TLI->isTypeLegal(NewVT))
571 NewVT = EltTy;
572 IntermediateVT = NewVT;
573
574 EVT DestVT = TLI->getRegisterType(NewVT);
575 RegisterVT = DestVT;
576 if (EVT(DestVT).bitsLT(NewVT)) {
577 // Value is expanded, e.g. i64 -> i16.
578 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
579 } else {
580 // Otherwise, promotion or legal types use the same number of registers as
581 // the vector decimated to the appropriate level.
582 return NumVectorRegs;
583 }
584
585 return 1;
586 }
587
588 /// computeRegisterProperties - Once all of the register classes are added,
589 /// this allows us to compute derived properties we expose.
590 void TargetLowering::computeRegisterProperties() {
591 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
592 "Too many value types for ValueTypeActions to hold!");
593
594 // Everything defaults to needing one register.
595 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
596 NumRegistersForVT[i] = 1;
597 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
598 }
599 // ...except isVoid, which doesn't need any registers.
600 NumRegistersForVT[MVT::isVoid] = 0;
601
602 // Find the largest integer register class.
603 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
604 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
605 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
606
607 // Every integer value type larger than this largest register takes twice as
608 // many registers to represent as the previous ValueType.
609 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
610 EVT EVT = (MVT::SimpleValueType)ExpandedReg;
611 if (!EVT.isInteger())
612 break;
613 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
614 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
615 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
616 ValueTypeActions.setTypeAction(EVT, Expand);
617 }
618
619 // Inspect all of the ValueType's smaller than the largest integer
620 // register to see which ones need promotion.
621 unsigned LegalIntReg = LargestIntReg;
622 for (unsigned IntReg = LargestIntReg - 1;
623 IntReg >= (unsigned)MVT::i1; --IntReg) {
624 EVT IVT = (MVT::SimpleValueType)IntReg;
625 if (isTypeLegal(IVT)) {
626 LegalIntReg = IntReg;
627 } else {
628 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
629 (MVT::SimpleValueType)LegalIntReg;
630 ValueTypeActions.setTypeAction(IVT, Promote);
631 }
632 }
633
634 // ppcf128 type is really two f64's.
635 if (!isTypeLegal(MVT::ppcf128)) {
636 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
637 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
638 TransformToType[MVT::ppcf128] = MVT::f64;
639 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
640 }
641
642 // Decide how to handle f64. If the target does not have native f64 support,
643 // expand it to i64 and we will be generating soft float library calls.
644 if (!isTypeLegal(MVT::f64)) {
645 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
646 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
647 TransformToType[MVT::f64] = MVT::i64;
648 ValueTypeActions.setTypeAction(MVT::f64, Expand);
649 }
650
651 // Decide how to handle f32. If the target does not have native support for
652 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
653 if (!isTypeLegal(MVT::f32)) {
654 if (isTypeLegal(MVT::f64)) {
655 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
656 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
657 TransformToType[MVT::f32] = MVT::f64;
658 ValueTypeActions.setTypeAction(MVT::f32, Promote);
659 } else {
660 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
661 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
662 TransformToType[MVT::f32] = MVT::i32;
663 ValueTypeActions.setTypeAction(MVT::f32, Expand);
664 }
665 }
666
667 // Loop over all of the vector value types to see which need transformations.
668 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
669 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
670 MVT VT = (MVT::SimpleValueType)i;
671 if (!isTypeLegal(VT)) {
672 MVT IntermediateVT;
673 EVT RegisterVT;
674 unsigned NumIntermediates;
675 NumRegistersForVT[i] =
676 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
677 RegisterVT, this);
678 RegisterTypeForVT[i] = RegisterVT;
679
680 // Determine if there is a legal wider type.
681 bool IsLegalWiderType = false;
682 EVT EltVT = VT.getVectorElementType();
683 unsigned NElts = VT.getVectorNumElements();
684 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
685 EVT SVT = (MVT::SimpleValueType)nVT;
686 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
687 SVT.getVectorNumElements() > NElts) {
688 TransformToType[i] = SVT;
689 ValueTypeActions.setTypeAction(VT, Promote);
690 IsLegalWiderType = true;
691 break;
692 }
693 }
694 if (!IsLegalWiderType) {
695 EVT NVT = VT.getPow2VectorType();
696 if (NVT == VT) {
697 // Type is already a power of 2. The default action is to split.
698 TransformToType[i] = MVT::Other;
699 ValueTypeActions.setTypeAction(VT, Expand);
700 } else {
701 TransformToType[i] = NVT;
702 ValueTypeActions.setTypeAction(VT, Promote);
703 }
704 }
705 }
706 }
707 }
708
709 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
710 return NULL;
711 }
712
713
714 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
715 return PointerTy.SimpleTy;
716 }
717
718 /// getVectorTypeBreakdown - Vector types are broken down into some number of
719 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
720 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
721 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
722 ///
723 /// This method returns the number of registers needed, and the VT for each
724 /// register. It also returns the VT and quantity of the intermediate values
725 /// before they are promoted/expanded.
726 ///
727 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
728 EVT &IntermediateVT,
729 unsigned &NumIntermediates,
730 EVT &RegisterVT) const {
731 // Figure out the right, legal destination reg to copy into.
732 unsigned NumElts = VT.getVectorNumElements();
733 EVT EltTy = VT.getVectorElementType();
734
735 unsigned NumVectorRegs = 1;
736
737 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
738 // could break down into LHS/RHS like LegalizeDAG does.
739 if (!isPowerOf2_32(NumElts)) {
740 NumVectorRegs = NumElts;
741 NumElts = 1;
742 }
743
744 // Divide the input until we get to a supported size. This will always
745 // end with a scalar if the target doesn't support vectors.
746 while (NumElts > 1 && !isTypeLegal(
747 EVT::getVectorVT(Context, EltTy, NumElts))) {
748 NumElts >>= 1;
749 NumVectorRegs <<= 1;
750 }
751
752 NumIntermediates = NumVectorRegs;
753
754 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
755 if (!isTypeLegal(NewVT))
756 NewVT = EltTy;
757 IntermediateVT = NewVT;
758
759 EVT DestVT = getRegisterType(Context, NewVT);
760 RegisterVT = DestVT;
761 if (DestVT.bitsLT(NewVT)) {
762 // Value is expanded, e.g. i64 -> i16.
763 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
764 } else {
765 // Otherwise, promotion or legal types use the same number of registers as
766 // the vector decimated to the appropriate level.
767 return NumVectorRegs;
768 }
769
770 return 1;
771 }
772
773 /// getWidenVectorType: given a vector type, returns the type to widen to
774 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
775 /// If there is no vector type that we want to widen to, returns MVT::Other
776 /// When and where to widen is target dependent based on the cost of
777 /// scalarizing vs using the wider vector type.
778 EVT TargetLowering::getWidenVectorType(EVT VT) const {
779 assert(VT.isVector());
780 if (isTypeLegal(VT))
781 return VT;
782
783 // Default is not to widen until moved to LegalizeTypes
784 return MVT::Other;
785 }
786
787 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
788 /// function arguments in the caller parameter area. This is the actual
789 /// alignment, not its logarithm.
790 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
791 return TD->getCallFrameTypeAlignment(Ty);
792 }
793
794 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
795 SelectionDAG &DAG) const {
796 if (usesGlobalOffsetTable())
797 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
798 return Table;
799 }
800
801 bool
802 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
803 // Assume that everything is safe in static mode.
804 if (getTargetMachine().getRelocationModel() == Reloc::Static)
805 return true;
806
807 // In dynamic-no-pic mode, assume that known defined values are safe.
808 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
809 GA &&
810 !GA->getGlobal()->isDeclaration() &&
811 !GA->getGlobal()->isWeakForLinker())
812 return true;
813
814 // Otherwise assume nothing is safe.
815 return false;
816 }
817
818 //===----------------------------------------------------------------------===//
819 // Optimization Methods
820 //===----------------------------------------------------------------------===//
821
822 /// ShrinkDemandedConstant - Check to see if the specified operand of the
823 /// specified instruction is a constant integer. If so, check to see if there
824 /// are any bits set in the constant that are not demanded. If so, shrink the
825 /// constant and return true.
826 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
827 const APInt &Demanded) {
828 DebugLoc dl = Op.getDebugLoc();
829
830 // FIXME: ISD::SELECT, ISD::SELECT_CC
831 switch (Op.getOpcode()) {
832 default: break;
833 case ISD::XOR:
834 case ISD::AND:
835 case ISD::OR: {
836 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
837 if (!C) return false;
838
839 if (Op.getOpcode() == ISD::XOR &&
840 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
841 return false;
842
843 // if we can expand it to have all bits set, do it
844 if (C->getAPIntValue().intersects(~Demanded)) {
845 EVT VT = Op.getValueType();
846 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
847 DAG.getConstant(Demanded &
848 C->getAPIntValue(),
849 VT));
850 return CombineTo(Op, New);
851 }
852
853 break;
854 }
855 }
856
857 return false;
858 }
859
860 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
861 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
862 /// cast, but it could be generalized for targets with other types of
863 /// implicit widening casts.
864 bool
865 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
866 unsigned BitWidth,
867 const APInt &Demanded,
868 DebugLoc dl) {
869 assert(Op.getNumOperands() == 2 &&
870 "ShrinkDemandedOp only supports binary operators!");
871 assert(Op.getNode()->getNumValues() == 1 &&
872 "ShrinkDemandedOp only supports nodes with one result!");
873
874 // Don't do this if the node has another user, which may require the
875 // full value.
876 if (!Op.getNode()->hasOneUse())
877 return false;
878
879 // Search for the smallest integer type with free casts to and from
880 // Op's type. For expedience, just check power-of-2 integer types.
881 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
882 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
883 if (!isPowerOf2_32(SmallVTBits))
884 SmallVTBits = NextPowerOf2(SmallVTBits);
885 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
886 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
887 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
888 TLI.isZExtFree(SmallVT, Op.getValueType())) {
889 // We found a type with free casts.
890 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
891 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
892 Op.getNode()->getOperand(0)),
893 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
894 Op.getNode()->getOperand(1)));
895 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
896 return CombineTo(Op, Z);
897 }
898 }
899 return false;
900 }
901
902 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
903 /// DemandedMask bits of the result of Op are ever used downstream. If we can
904 /// use this information to simplify Op, create a new simplified DAG node and
905 /// return true, returning the original and new nodes in Old and New. Otherwise,
906 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
907 /// the expression (used to simplify the caller). The KnownZero/One bits may
908 /// only be accurate for those bits in the DemandedMask.
909 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
910 const APInt &DemandedMask,
911 APInt &KnownZero,
912 APInt &KnownOne,
913 TargetLoweringOpt &TLO,
914 unsigned Depth) const {
915 unsigned BitWidth = DemandedMask.getBitWidth();
916 assert(Op.getValueSizeInBits() == BitWidth &&
917 "Mask size mismatches value type size!");
918 APInt NewMask = DemandedMask;
919 DebugLoc dl = Op.getDebugLoc();
920
921 // Don't know anything.
922 KnownZero = KnownOne = APInt(BitWidth, 0);
923
924 // Other users may use these bits.
925 if (!Op.getNode()->hasOneUse()) {
926 if (Depth != 0) {
927 // If not at the root, Just compute the KnownZero/KnownOne bits to
928 // simplify things downstream.
929 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
930 return false;
931 }
932 // If this is the root being simplified, allow it to have multiple uses,
933 // just set the NewMask to all bits.
934 NewMask = APInt::getAllOnesValue(BitWidth);
935 } else if (DemandedMask == 0) {
936 // Not demanding any bits from Op.
937 if (Op.getOpcode() != ISD::UNDEF)
938 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
939 return false;
940 } else if (Depth == 6) { // Limit search depth.
941 return false;
942 }
943
944 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
945 switch (Op.getOpcode()) {
946 case ISD::Constant:
947 // We know all of the bits for a constant!
948 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
949 KnownZero = ~KnownOne & NewMask;
950 return false; // Don't fall through, will infinitely loop.
951 case ISD::AND:
952 // If the RHS is a constant, check to see if the LHS would be zero without
953 // using the bits from the RHS. Below, we use knowledge about the RHS to
954 // simplify the LHS, here we're using information from the LHS to simplify
955 // the RHS.
956 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
957 APInt LHSZero, LHSOne;
958 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
959 LHSZero, LHSOne, Depth+1);
960 // If the LHS already has zeros where RHSC does, this and is dead.
961 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
962 return TLO.CombineTo(Op, Op.getOperand(0));
963 // If any of the set bits in the RHS are known zero on the LHS, shrink
964 // the constant.
965 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
966 return true;
967 }
968
969 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
970 KnownOne, TLO, Depth+1))
971 return true;
972 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
973 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
974 KnownZero2, KnownOne2, TLO, Depth+1))
975 return true;
976 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
977
978 // If all of the demanded bits are known one on one side, return the other.
979 // These bits cannot contribute to the result of the 'and'.
980 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
981 return TLO.CombineTo(Op, Op.getOperand(0));
982 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
983 return TLO.CombineTo(Op, Op.getOperand(1));
984 // If all of the demanded bits in the inputs are known zeros, return zero.
985 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
986 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
987 // If the RHS is a constant, see if we can simplify it.
988 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
989 return true;
990 // If the operation can be done in a smaller type, do so.
991 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
992 return true;
993
994 // Output known-1 bits are only known if set in both the LHS & RHS.
995 KnownOne &= KnownOne2;
996 // Output known-0 are known to be clear if zero in either the LHS | RHS.
997 KnownZero |= KnownZero2;
998 break;
999 case ISD::OR:
1000 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1001 KnownOne, TLO, Depth+1))
1002 return true;
1003 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1004 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1005 KnownZero2, KnownOne2, TLO, Depth+1))
1006 return true;
1007 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1008
1009 // If all of the demanded bits are known zero on one side, return the other.
1010 // These bits cannot contribute to the result of the 'or'.
1011 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1012 return TLO.CombineTo(Op, Op.getOperand(0));
1013 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1014 return TLO.CombineTo(Op, Op.getOperand(1));
1015 // If all of the potentially set bits on one side are known to be set on
1016 // the other side, just use the 'other' side.
1017 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1018 return TLO.CombineTo(Op, Op.getOperand(0));
1019 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1020 return TLO.CombineTo(Op, Op.getOperand(1));
1021 // If the RHS is a constant, see if we can simplify it.
1022 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1023 return true;
1024 // If the operation can be done in a smaller type, do so.
1025 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1026 return true;
1027
1028 // Output known-0 bits are only known if clear in both the LHS & RHS.
1029 KnownZero &= KnownZero2;
1030 // Output known-1 are known to be set if set in either the LHS | RHS.
1031 KnownOne |= KnownOne2;
1032 break;
1033 case ISD::XOR:
1034 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1035 KnownOne, TLO, Depth+1))
1036 return true;
1037 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1038 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1039 KnownOne2, TLO, Depth+1))
1040 return true;
1041 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1042
1043 // If all of the demanded bits are known zero on one side, return the other.
1044 // These bits cannot contribute to the result of the 'xor'.
1045 if ((KnownZero & NewMask) == NewMask)
1046 return TLO.CombineTo(Op, Op.getOperand(0));
1047 if ((KnownZero2 & NewMask) == NewMask)
1048 return TLO.CombineTo(Op, Op.getOperand(1));
1049 // If the operation can be done in a smaller type, do so.
1050 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1051 return true;
1052
1053 // If all of the unknown bits are known to be zero on one side or the other
1054 // (but not both) turn this into an *inclusive* or.
1055 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1056 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1057 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1058 Op.getOperand(0),
1059 Op.getOperand(1)));
1060
1061 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1062 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1063 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1064 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1065
1066 // If all of the demanded bits on one side are known, and all of the set
1067 // bits on that side are also known to be set on the other side, turn this
1068 // into an AND, as we know the bits will be cleared.
1069 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1070 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1071 if ((KnownOne & KnownOne2) == KnownOne) {
1072 EVT VT = Op.getValueType();
1073 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1074 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1075 Op.getOperand(0), ANDC));
1076 }
1077 }
1078
1079 // If the RHS is a constant, see if we can simplify it.
1080 // for XOR, we prefer to force bits to 1 if they will make a -1.
1081 // if we can't force bits, try to shrink constant
1082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1083 APInt Expanded = C->getAPIntValue() | (~NewMask);
1084 // if we can expand it to have all bits set, do it
1085 if (Expanded.isAllOnesValue()) {
1086 if (Expanded != C->getAPIntValue()) {
1087 EVT VT = Op.getValueType();
1088 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1089 TLO.DAG.getConstant(Expanded, VT));
1090 return TLO.CombineTo(Op, New);
1091 }
1092 // if it already has all the bits set, nothing to change
1093 // but don't shrink either!
1094 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1095 return true;
1096 }
1097 }
1098
1099 KnownZero = KnownZeroOut;
1100 KnownOne = KnownOneOut;
1101 break;
1102 case ISD::SELECT:
1103 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1104 KnownOne, TLO, Depth+1))
1105 return true;
1106 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1107 KnownOne2, TLO, Depth+1))
1108 return true;
1109 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1110 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1111
1112 // If the operands are constants, see if we can simplify them.
1113 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1114 return true;
1115
1116 // Only known if known in both the LHS and RHS.
1117 KnownOne &= KnownOne2;
1118 KnownZero &= KnownZero2;
1119 break;
1120 case ISD::SELECT_CC:
1121 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1122 KnownOne, TLO, Depth+1))
1123 return true;
1124 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1125 KnownOne2, TLO, Depth+1))
1126 return true;
1127 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1128 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1129
1130 // If the operands are constants, see if we can simplify them.
1131 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1132 return true;
1133
1134 // Only known if known in both the LHS and RHS.
1135 KnownOne &= KnownOne2;
1136 KnownZero &= KnownZero2;
1137 break;
1138 case ISD::SHL:
1139 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1140 unsigned ShAmt = SA->getZExtValue();
1141 SDValue InOp = Op.getOperand(0);
1142
1143 // If the shift count is an invalid immediate, don't do anything.
1144 if (ShAmt >= BitWidth)
1145 break;
1146
1147 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1148 // single shift. We can do this if the bottom bits (which are shifted
1149 // out) are never demanded.
1150 if (InOp.getOpcode() == ISD::SRL &&
1151 isa<ConstantSDNode>(InOp.getOperand(1))) {
1152 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1153 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1154 unsigned Opc = ISD::SHL;
1155 int Diff = ShAmt-C1;
1156 if (Diff < 0) {
1157 Diff = -Diff;
1158 Opc = ISD::SRL;
1159 }
1160
1161 SDValue NewSA =
1162 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1163 EVT VT = Op.getValueType();
1164 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1165 InOp.getOperand(0), NewSA));
1166 }
1167 }
1168
1169 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1170 KnownZero, KnownOne, TLO, Depth+1))
1171 return true;
1172 KnownZero <<= SA->getZExtValue();
1173 KnownOne <<= SA->getZExtValue();
1174 // low bits known zero.
1175 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1176 }
1177 break;
1178 case ISD::SRL:
1179 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1180 EVT VT = Op.getValueType();
1181 unsigned ShAmt = SA->getZExtValue();
1182 unsigned VTSize = VT.getSizeInBits();
1183 SDValue InOp = Op.getOperand(0);
1184
1185 // If the shift count is an invalid immediate, don't do anything.
1186 if (ShAmt >= BitWidth)
1187 break;
1188
1189 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1190 // single shift. We can do this if the top bits (which are shifted out)
1191 // are never demanded.
1192 if (InOp.getOpcode() == ISD::SHL &&
1193 isa<ConstantSDNode>(InOp.getOperand(1))) {
1194 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1195 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1196 unsigned Opc = ISD::SRL;
1197 int Diff = ShAmt-C1;
1198 if (Diff < 0) {
1199 Diff = -Diff;
1200 Opc = ISD::SHL;
1201 }
1202
1203 SDValue NewSA =
1204 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1205 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1206 InOp.getOperand(0), NewSA));
1207 }
1208 }
1209
1210 // Compute the new bits that are at the top now.
1211 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1212 KnownZero, KnownOne, TLO, Depth+1))
1213 return true;
1214 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1215 KnownZero = KnownZero.lshr(ShAmt);
1216 KnownOne = KnownOne.lshr(ShAmt);
1217
1218 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1219 KnownZero |= HighBits; // High bits known zero.
1220 }
1221 break;
1222 case ISD::SRA:
1223 // If this is an arithmetic shift right and only the low-bit is set, we can
1224 // always convert this into a logical shr, even if the shift amount is
1225 // variable. The low bit of the shift cannot be an input sign bit unless
1226 // the shift amount is >= the size of the datatype, which is undefined.
1227 if (DemandedMask == 1)
1228 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1229 Op.getOperand(0), Op.getOperand(1)));
1230
1231 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1232 EVT VT = Op.getValueType();
1233 unsigned ShAmt = SA->getZExtValue();
1234
1235 // If the shift count is an invalid immediate, don't do anything.
1236 if (ShAmt >= BitWidth)
1237 break;
1238
1239 APInt InDemandedMask = (NewMask << ShAmt);
1240
1241 // If any of the demanded bits are produced by the sign extension, we also
1242 // demand the input sign bit.
1243 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1244 if (HighBits.intersects(NewMask))
1245 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1246
1247 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1248 KnownZero, KnownOne, TLO, Depth+1))
1249 return true;
1250 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1251 KnownZero = KnownZero.lshr(ShAmt);
1252 KnownOne = KnownOne.lshr(ShAmt);
1253
1254 // Handle the sign bit, adjusted to where it is now in the mask.
1255 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1256
1257 // If the input sign bit is known to be zero, or if none of the top bits
1258 // are demanded, turn this into an unsigned shift right.
1259 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1260 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1261 Op.getOperand(0),
1262 Op.getOperand(1)));
1263 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1264 KnownOne |= HighBits;
1265 }
1266 }
1267 break;
1268 case ISD::SIGN_EXTEND_INREG: {
1269 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1270
1271 // Sign extension. Compute the demanded bits in the result that are not
1272 // present in the input.
1273 APInt NewBits = APInt::getHighBitsSet(BitWidth,
1274 BitWidth - EVT.getSizeInBits()) &
1275 NewMask;
1276
1277 // If none of the extended bits are demanded, eliminate the sextinreg.
1278 if (NewBits == 0)
1279 return TLO.CombineTo(Op, Op.getOperand(0));
1280
1281 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1282 InSignBit.zext(BitWidth);
1283 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1284 EVT.getSizeInBits()) &
1285 NewMask;
1286
1287 // Since the sign extended bits are demanded, we know that the sign
1288 // bit is demanded.
1289 InputDemandedBits |= InSignBit;
1290
1291 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1292 KnownZero, KnownOne, TLO, Depth+1))
1293 return true;
1294 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1295
1296 // If the sign bit of the input is known set or clear, then we know the
1297 // top bits of the result.
1298
1299 // If the input sign bit is known zero, convert this into a zero extension.
1300 if (KnownZero.intersects(InSignBit))
1301 return TLO.CombineTo(Op,
1302 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1303
1304 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1305 KnownOne |= NewBits;
1306 KnownZero &= ~NewBits;
1307 } else { // Input sign bit unknown
1308 KnownZero &= ~NewBits;
1309 KnownOne &= ~NewBits;
1310 }
1311 break;
1312 }
1313 case ISD::ZERO_EXTEND: {
1314 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1315 APInt InMask = NewMask;
1316 InMask.trunc(OperandBitWidth);
1317
1318 // If none of the top bits are demanded, convert this into an any_extend.
1319 APInt NewBits =
1320 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1321 if (!NewBits.intersects(NewMask))
1322 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1323 Op.getValueType(),
1324 Op.getOperand(0)));
1325
1326 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1327 KnownZero, KnownOne, TLO, Depth+1))
1328 return true;
1329 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1330 KnownZero.zext(BitWidth);
1331 KnownOne.zext(BitWidth);
1332 KnownZero |= NewBits;
1333 break;
1334 }
1335 case ISD::SIGN_EXTEND: {
1336 EVT InVT = Op.getOperand(0).getValueType();
1337 unsigned InBits = InVT.getSizeInBits();
1338 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1339 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1340 APInt NewBits = ~InMask & NewMask;
1341
1342 // If none of the top bits are demanded, convert this into an any_extend.
1343 if (NewBits == 0)
1344 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1345 Op.getValueType(),
1346 Op.getOperand(0)));
1347
1348 // Since some of the sign extended bits are demanded, we know that the sign
1349 // bit is demanded.
1350 APInt InDemandedBits = InMask & NewMask;
1351 InDemandedBits |= InSignBit;
1352 InDemandedBits.trunc(InBits);
1353
1354 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1355 KnownOne, TLO, Depth+1))
1356 return true;
1357 KnownZero.zext(BitWidth);
1358 KnownOne.zext(BitWidth);
1359
1360 // If the sign bit is known zero, convert this to a zero extend.
1361 if (KnownZero.intersects(InSignBit))
1362 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1363 Op.getValueType(),
1364 Op.getOperand(0)));
1365
1366 // If the sign bit is known one, the top bits match.
1367 if (KnownOne.intersects(InSignBit)) {
1368 KnownOne |= NewBits;
1369 KnownZero &= ~NewBits;
1370 } else { // Otherwise, top bits aren't known.
1371 KnownOne &= ~NewBits;
1372 KnownZero &= ~NewBits;
1373 }
1374 break;
1375 }
1376 case ISD::ANY_EXTEND: {
1377 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1378 APInt InMask = NewMask;
1379 InMask.trunc(OperandBitWidth);
1380 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1381 KnownZero, KnownOne, TLO, Depth+1))
1382 return true;
1383 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1384 KnownZero.zext(BitWidth);
1385 KnownOne.zext(BitWidth);
1386 break;
1387 }
1388 case ISD::TRUNCATE: {
1389 // Simplify the input, using demanded bit information, and compute the known
1390 // zero/one bits live out.
1391 APInt TruncMask = NewMask;
1392 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1393 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1394 KnownZero, KnownOne, TLO, Depth+1))
1395 return true;
1396 KnownZero.trunc(BitWidth);
1397 KnownOne.trunc(BitWidth);
1398
1399 // If the input is only used by this truncate, see if we can shrink it based
1400 // on the known demanded bits.
1401 if (Op.getOperand(0).getNode()->hasOneUse()) {
1402 SDValue In = Op.getOperand(0);
1403 unsigned InBitWidth = In.getValueSizeInBits();
1404 switch (In.getOpcode()) {
1405 default: break;
1406 case ISD::SRL:
1407 // Shrink SRL by a constant if none of the high bits shifted in are
1408 // demanded.
1409 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1410 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1411 InBitWidth - BitWidth);
1412 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1413 HighBits.trunc(BitWidth);
1414
1415 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1416 // None of the shifted in bits are needed. Add a truncate of the
1417 // shift input, then shift it.
1418 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1419 Op.getValueType(),
1420 In.getOperand(0));
1421 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1422 Op.getValueType(),
1423 NewTrunc,
1424 In.getOperand(1)));
1425 }
1426 }
1427 break;
1428 }
1429 }
1430
1431 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1432 break;
1433 }
1434 case ISD::AssertZext: {
1435 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1436 APInt InMask = APInt::getLowBitsSet(BitWidth,
1437 VT.getSizeInBits());
1438 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1439 KnownZero, KnownOne, TLO, Depth+1))
1440 return true;
1441 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1442 KnownZero |= ~InMask & NewMask;
1443 break;
1444 }
1445 case ISD::BIT_CONVERT:
1446 #if 0
1447 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1448 // is demanded, turn this into a FGETSIGN.
1449 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1450 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1451 !MVT::isVector(Op.getOperand(0).getValueType())) {
1452 // Only do this xform if FGETSIGN is valid or if before legalize.
1453 if (!TLO.AfterLegalize ||
1454 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1455 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1456 // place. We expect the SHL to be eliminated by other optimizations.
1457 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1458 Op.getOperand(0));
1459 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1460 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1461 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1462 Sign, ShAmt));
1463 }
1464 }
1465 #endif
1466 break;
1467 case ISD::ADD:
1468 case ISD::MUL:
1469 case ISD::SUB: {
1470 // Add, Sub, and Mul don't demand any bits in positions beyond that
1471 // of the highest bit demanded of them.
1472 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1473 BitWidth - NewMask.countLeadingZeros());
1474 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1475 KnownOne2, TLO, Depth+1))
1476 return true;
1477 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1478 KnownOne2, TLO, Depth+1))
1479 return true;
1480 // See if the operation should be performed at a smaller bit width.
1481 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1482 return true;
1483 }
1484 // FALL THROUGH
1485 default:
1486 // Just use ComputeMaskedBits to compute output bits.
1487 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1488 break;
1489 }
1490
1491 // If we know the value of all of the demanded bits, return this as a
1492 // constant.
1493 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1494 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1495
1496 return false;
1497 }
1498
1499 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1500 /// in Mask are known to be either zero or one and return them in the
1501 /// KnownZero/KnownOne bitsets.
1502 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1503 const APInt &Mask,
1504 APInt &KnownZero,
1505 APInt &KnownOne,
1506 const SelectionDAG &DAG,
1507 unsigned Depth) const {
1508 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1509 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1510 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1511 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1512 "Should use MaskedValueIsZero if you don't know whether Op"
1513 " is a target node!");
1514 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1515 }
1516
1517 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1518 /// targets that want to expose additional information about sign bits to the
1519 /// DAG Combiner.
1520 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1521 unsigned Depth) const {
1522 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1523 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1524 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1525 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1526 "Should use ComputeNumSignBits if you don't know whether Op"
1527 " is a target node!");
1528 return 1;
1529 }
1530
1531 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1532 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1533 /// determine which bit is set.
1534 ///
1535 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1536 // A left-shift of a constant one will have exactly one bit set, because
1537 // shifting the bit off the end is undefined.
1538 if (Val.getOpcode() == ISD::SHL)
1539 if (ConstantSDNode *C =
1540 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1541 if (C->getAPIntValue() == 1)
1542 return true;
1543
1544 // Similarly, a right-shift of a constant sign-bit will have exactly
1545 // one bit set.
1546 if (Val.getOpcode() == ISD::SRL)
1547 if (ConstantSDNode *C =
1548 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1549 if (C->getAPIntValue().isSignBit())
1550 return true;
1551
1552 // More could be done here, though the above checks are enough
1553 // to handle some common cases.
1554
1555 // Fall back to ComputeMaskedBits to catch other known cases.
1556 EVT OpVT = Val.getValueType();
1557 unsigned BitWidth = OpVT.getSizeInBits();
1558 APInt Mask = APInt::getAllOnesValue(BitWidth);
1559 APInt KnownZero, KnownOne;
1560 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1561 return (KnownZero.countPopulation() == BitWidth - 1) &&
1562 (KnownOne.countPopulation() == 1);
1563 }
1564
1565 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1566 /// and cc. If it is unable to simplify it, return a null SDValue.
1567 SDValue
1568 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1569 ISD::CondCode Cond, bool foldBooleans,
1570 DAGCombinerInfo &DCI, DebugLoc dl) const {
1571 SelectionDAG &DAG = DCI.DAG;
1572 LLVMContext &Context = *DAG.getContext();
1573
1574 // These setcc operations always fold.
1575 switch (Cond) {
1576 default: break;
1577 case ISD::SETFALSE:
1578 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1579 case ISD::SETTRUE:
1580 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1581 }
1582
1583 if (isa<ConstantSDNode>(N0.getNode())) {
1584 // Ensure that the constant occurs on the RHS, and fold constant
1585 // comparisons.
1586 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1587 }
1588
1589 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1590 const APInt &C1 = N1C->getAPIntValue();
1591
1592 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1593 // equality comparison, then we're just comparing whether X itself is
1594 // zero.
1595 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1596 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1597 N0.getOperand(1).getOpcode() == ISD::Constant) {
1598 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1599 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1600 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1601 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1602 // (srl (ctlz x), 5) == 0 -> X != 0
1603 // (srl (ctlz x), 5) != 1 -> X != 0
1604 Cond = ISD::SETNE;
1605 } else {
1606 // (srl (ctlz x), 5) != 0 -> X == 0
1607 // (srl (ctlz x), 5) == 1 -> X == 0
1608 Cond = ISD::SETEQ;
1609 }
1610 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1611 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1612 Zero, Cond);
1613 }
1614 }
1615
1616 // If the LHS is '(and load, const)', the RHS is 0,
1617 // the test is for equality or unsigned, and all 1 bits of the const are
1618 // in the same partial word, see if we can shorten the load.
1619 if (DCI.isBeforeLegalize() &&
1620 N0.getOpcode() == ISD::AND && C1 == 0 &&
1621 N0.getNode()->hasOneUse() &&
1622 isa<LoadSDNode>(N0.getOperand(0)) &&
1623 N0.getOperand(0).getNode()->hasOneUse() &&
1624 isa<ConstantSDNode>(N0.getOperand(1))) {
1625 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1626 uint64_t bestMask = 0;
1627 unsigned bestWidth = 0, bestOffset = 0;
1628 if (!Lod->isVolatile() && Lod->isUnindexed() &&
1629 // FIXME: This uses getZExtValue() below so it only works on i64 and
1630 // below.
1631 N0.getValueType().getSizeInBits() <= 64) {
1632 unsigned origWidth = N0.getValueType().getSizeInBits();
1633 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1634 // 8 bits, but have to be careful...
1635 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1636 origWidth = Lod->getMemoryVT().getSizeInBits();
1637 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1638 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1639 uint64_t newMask = (1ULL << width) - 1;
1640 for (unsigned offset=0; offset<origWidth/width; offset++) {
1641 if ((newMask & Mask) == Mask) {
1642 if (!TD->isLittleEndian())
1643 bestOffset = (origWidth/width - offset - 1) * (width/8);
1644 else
1645 bestOffset = (uint64_t)offset * (width/8);
1646 bestMask = Mask >> (offset * (width/8) * 8);
1647 bestWidth = width;
1648 break;
1649 }
1650 newMask = newMask << width;
1651 }
1652 }
1653 }
1654 if (bestWidth) {
1655 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1656 if (newVT.isRound()) {
1657 EVT PtrType = Lod->getOperand(1).getValueType();
1658 SDValue Ptr = Lod->getBasePtr();
1659 if (bestOffset != 0)
1660 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1661 DAG.getConstant(bestOffset, PtrType));
1662 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1663 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1664 Lod->getSrcValue(),
1665 Lod->getSrcValueOffset() + bestOffset,
1666 false, NewAlign);
1667 return DAG.getSetCC(dl, VT,
1668 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1669 DAG.getConstant(bestMask, newVT)),
1670 DAG.getConstant(0LL, newVT), Cond);
1671 }
1672 }
1673 }
1674
1675 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1676 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1677 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1678
1679 // If the comparison constant has bits in the upper part, the
1680 // zero-extended value could never match.
1681 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1682 C1.getBitWidth() - InSize))) {
1683 switch (Cond) {
1684 case ISD::SETUGT:
1685 case ISD::SETUGE:
1686 case ISD::SETEQ: return DAG.getConstant(0, VT);
1687 case ISD::SETULT:
1688 case ISD::SETULE:
1689 case ISD::SETNE: return DAG.getConstant(1, VT);
1690 case ISD::SETGT:
1691 case ISD::SETGE:
1692 // True if the sign bit of C1 is set.
1693 return DAG.getConstant(C1.isNegative(), VT);
1694 case ISD::SETLT:
1695 case ISD::SETLE:
1696 // True if the sign bit of C1 isn't set.
1697 return DAG.getConstant(C1.isNonNegative(), VT);
1698 default:
1699 break;
1700 }
1701 }
1702
1703 // Otherwise, we can perform the comparison with the low bits.
1704 switch (Cond) {
1705 case ISD::SETEQ:
1706 case ISD::SETNE:
1707 case ISD::SETUGT:
1708 case ISD::SETUGE:
1709 case ISD::SETULT:
1710 case ISD::SETULE: {
1711 EVT newVT = N0.getOperand(0).getValueType();
1712 if (DCI.isBeforeLegalizeOps() ||
1713 (isOperationLegal(ISD::SETCC, newVT) &&
1714 getCondCodeAction(Cond, newVT)==Legal))
1715 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1716 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1717 Cond);
1718 break;
1719 }
1720 default:
1721 break; // todo, be more careful with signed comparisons
1722 }
1723 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1724 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1725 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1726 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1727 EVT ExtDstTy = N0.getValueType();
1728 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1729
1730 // If the extended part has any inconsistent bits, it cannot ever
1731 // compare equal. In other words, they have to be all ones or all
1732 // zeros.
1733 APInt ExtBits =
1734 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1735 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1736 return DAG.getConstant(Cond == ISD::SETNE, VT);
1737
1738 SDValue ZextOp;
1739 EVT Op0Ty = N0.getOperand(0).getValueType();
1740 if (Op0Ty == ExtSrcTy) {
1741 ZextOp = N0.getOperand(0);
1742 } else {
1743 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1744 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1745 DAG.getConstant(Imm, Op0Ty));
1746 }
1747 if (!DCI.isCalledByLegalizer())
1748 DCI.AddToWorklist(ZextOp.getNode());
1749 // Otherwise, make this a use of a zext.
1750 return DAG.getSetCC(dl, VT, ZextOp,
1751 DAG.getConstant(C1 & APInt::getLowBitsSet(
1752 ExtDstTyBits,
1753 ExtSrcTyBits),
1754 ExtDstTy),
1755 Cond);
1756 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1757 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1758
1759 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1760 if (N0.getOpcode() == ISD::SETCC) {
1761 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1762 if (TrueWhenTrue)
1763 return N0;
1764
1765 // Invert the condition.
1766 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1767 CC = ISD::getSetCCInverse(CC,
1768 N0.getOperand(0).getValueType().isInteger());
1769 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1770 }
1771
1772 if ((N0.getOpcode() == ISD::XOR ||
1773 (N0.getOpcode() == ISD::AND &&
1774 N0.getOperand(0).getOpcode() == ISD::XOR &&
1775 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1776 isa<ConstantSDNode>(N0.getOperand(1)) &&
1777 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1778 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1779 // can only do this if the top bits are known zero.
1780 unsigned BitWidth = N0.getValueSizeInBits();
1781 if (DAG.MaskedValueIsZero(N0,
1782 APInt::getHighBitsSet(BitWidth,
1783 BitWidth-1))) {
1784 // Okay, get the un-inverted input value.
1785 SDValue Val;
1786 if (N0.getOpcode() == ISD::XOR)
1787 Val = N0.getOperand(0);
1788 else {
1789 assert(N0.getOpcode() == ISD::AND &&
1790 N0.getOperand(0).getOpcode() == ISD::XOR);
1791 // ((X^1)&1)^1 -> X & 1
1792 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1793 N0.getOperand(0).getOperand(0),
1794 N0.getOperand(1));
1795 }
1796 return DAG.getSetCC(dl, VT, Val, N1,
1797 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1798 }
1799 }
1800 }
1801
1802 APInt MinVal, MaxVal;
1803 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1804 if (ISD::isSignedIntSetCC(Cond)) {
1805 MinVal = APInt::getSignedMinValue(OperandBitSize);
1806 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1807 } else {
1808 MinVal = APInt::getMinValue(OperandBitSize);
1809 MaxVal = APInt::getMaxValue(OperandBitSize);
1810 }
1811
1812 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1813 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1814 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1815 // X >= C0 --> X > (C0-1)
1816 return DAG.getSetCC(dl, VT, N0,
1817 DAG.getConstant(C1-1, N1.getValueType()),
1818 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1819 }
1820
1821 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1822 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1823 // X <= C0 --> X < (C0+1)
1824 return DAG.getSetCC(dl, VT, N0,
1825 DAG.getConstant(C1+1, N1.getValueType()),
1826 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1827 }
1828
1829 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1830 return DAG.getConstant(0, VT); // X < MIN --> false
1831 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1832 return DAG.getConstant(1, VT); // X >= MIN --> true
1833 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1834 return DAG.getConstant(0, VT); // X > MAX --> false
1835 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1836 return DAG.getConstant(1, VT); // X <= MAX --> true
1837
1838 // Canonicalize setgt X, Min --> setne X, Min
1839 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1840 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1841 // Canonicalize setlt X, Max --> setne X, Max
1842 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1843 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1844
1845 // If we have setult X, 1, turn it into seteq X, 0
1846 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1847 return DAG.getSetCC(dl, VT, N0,
1848 DAG.getConstant(MinVal, N0.getValueType()),
1849 ISD::SETEQ);
1850 // If we have setugt X, Max-1, turn it into seteq X, Max
1851 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1852 return DAG.getSetCC(dl, VT, N0,
1853 DAG.getConstant(MaxVal, N0.getValueType()),
1854 ISD::SETEQ);
1855
1856 // If we have "setcc X, C0", check to see if we can shrink the immediate
1857 // by changing cc.
1858
1859 // SETUGT X, SINTMAX -> SETLT X, 0
1860 if (Cond == ISD::SETUGT &&
1861 C1 == APInt::getSignedMaxValue(OperandBitSize))
1862 return DAG.getSetCC(dl, VT, N0,
1863 DAG.getConstant(0, N1.getValueType()),
1864 ISD::SETLT);
1865
1866 // SETULT X, SINTMIN -> SETGT X, -1
1867 if (Cond == ISD::SETULT &&
1868 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1869 SDValue ConstMinusOne =
1870 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1871 N1.getValueType());
1872 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1873 }
1874
1875 // Fold bit comparisons when we can.
1876 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1877 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1878 if (ConstantSDNode *AndRHS =
1879 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1880 EVT ShiftTy = DCI.isBeforeLegalize() ?
1881 getPointerTy() : getShiftAmountTy();
1882 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1883 // Perform the xform if the AND RHS is a single bit.
1884 if (isPowerOf2_64(AndRHS->getZExtValue())) {
1885 return DAG.getNode(ISD::SRL, dl, VT, N0,
1886 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1887 ShiftTy));
1888 }
1889 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1890 // (X & 8) == 8 --> (X & 8) >> 3
1891 // Perform the xform if C1 is a single bit.
1892 if (C1.isPowerOf2()) {
1893 return DAG.getNode(ISD::SRL, dl, VT, N0,
1894 DAG.getConstant(C1.logBase2(), ShiftTy));
1895 }
1896 }
1897 }
1898 }
1899
1900 if (isa<ConstantFPSDNode>(N0.getNode())) {
1901 // Constant fold or commute setcc.
1902 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1903 if (O.getNode()) return O;
1904 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1905 // If the RHS of an FP comparison is a constant, simplify it away in
1906 // some cases.
1907 if (CFP->getValueAPF().isNaN()) {
1908 // If an operand is known to be a nan, we can fold it.
1909 switch (ISD::getUnorderedFlavor(Cond)) {
1910 default: llvm_unreachable("Unknown flavor!");
1911 case 0: // Known false.
1912 return DAG.getConstant(0, VT);
1913 case 1: // Known true.
1914 return DAG.getConstant(1, VT);
1915 case 2: // Undefined.
1916 return DAG.getUNDEF(VT);
1917 }
1918 }
1919
1920 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1921 // constant if knowing that the operand is non-nan is enough. We prefer to
1922 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1923 // materialize 0.0.
1924 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1925 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1926 }
1927
1928 if (N0 == N1) {
1929 // We can always fold X == X for integer setcc's.
1930 if (N0.getValueType().isInteger())
1931 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1932 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1933 if (UOF == 2) // FP operators that are undefined on NaNs.
1934 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1935 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1936 return DAG.getConstant(UOF, VT);
1937 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1938 // if it is not already.
1939 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1940 if (NewCond != Cond)
1941 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1942 }
1943
1944 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1945 N0.getValueType().isInteger()) {
1946 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1947 N0.getOpcode() == ISD::XOR) {
1948 // Simplify (X+Y) == (X+Z) --> Y == Z
1949 if (N0.getOpcode() == N1.getOpcode()) {
1950 if (N0.getOperand(0) == N1.getOperand(0))
1951 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1952 if (N0.getOperand(1) == N1.getOperand(1))
1953 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1954 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1955 // If X op Y == Y op X, try other combinations.
1956 if (N0.getOperand(0) == N1.getOperand(1))
1957 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1958 Cond);
1959 if (N0.getOperand(1) == N1.getOperand(0))
1960 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1961 Cond);
1962 }
1963 }
1964
1965 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1966 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1967 // Turn (X+C1) == C2 --> X == C2-C1
1968 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1969 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1970 DAG.getConstant(RHSC->getAPIntValue()-
1971 LHSR->getAPIntValue(),
1972 N0.getValueType()), Cond);
1973 }
1974
1975 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1976 if (N0.getOpcode() == ISD::XOR)
1977 // If we know that all of the inverted bits are zero, don't bother
1978 // performing the inversion.
1979 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1980 return
1981 DAG.getSetCC(dl, VT, N0.getOperand(0),
1982 DAG.getConstant(LHSR->getAPIntValue() ^
1983 RHSC->getAPIntValue(),
1984 N0.getValueType()),
1985 Cond);
1986 }
1987
1988 // Turn (C1-X) == C2 --> X == C1-C2
1989 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1990 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1991 return
1992 DAG.getSetCC(dl, VT, N0.getOperand(1),
1993 DAG.getConstant(SUBC->getAPIntValue() -
1994 RHSC->getAPIntValue(),
1995 N0.getValueType()),
1996 Cond);
1997 }
1998 }
1999 }
2000
2001 // Simplify (X+Z) == X --> Z == 0
2002 if (N0.getOperand(0) == N1)
2003 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2004 DAG.getConstant(0, N0.getValueType()), Cond);
2005 if (N0.getOperand(1) == N1) {
2006 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2007 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2008 DAG.getConstant(0, N0.getValueType()), Cond);
2009 else if (N0.getNode()->hasOneUse()) {
2010 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2011 // (Z-X) == X --> Z == X<<1
2012 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2013 N1,
2014 DAG.getConstant(1, getShiftAmountTy()));
2015 if (!DCI.isCalledByLegalizer())
2016 DCI.AddToWorklist(SH.getNode());
2017 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2018 }
2019 }
2020 }
2021
2022 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2023 N1.getOpcode() == ISD::XOR) {
2024 // Simplify X == (X+Z) --> Z == 0
2025 if (N1.getOperand(0) == N0) {
2026 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2027 DAG.getConstant(0, N1.getValueType()), Cond);
2028 } else if (N1.getOperand(1) == N0) {
2029 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2030 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2031 DAG.getConstant(0, N1.getValueType()), Cond);
2032 } else if (N1.getNode()->hasOneUse()) {
2033 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2034 // X == (Z-X) --> X<<1 == Z
2035 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2036 DAG.getConstant(1, getShiftAmountTy()));
2037 if (!DCI.isCalledByLegalizer())
2038 DCI.AddToWorklist(SH.getNode());
2039 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2040 }
2041 }
2042 }
2043
2044 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2045 // Note that where y is variable and is known to have at most
2046 // one bit set (for example, if it is z&1) we cannot do this;
2047 // the expressions are not equivalent when y==0.
2048 if (N0.getOpcode() == ISD::AND)
2049 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2050 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2051 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2052 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2053 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2054 }
2055 }
2056 if (N1.getOpcode() == ISD::AND)
2057 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2058 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2059 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2060 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2061 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2062 }
2063 }
2064 }
2065
2066 // Fold away ALL boolean setcc's.
2067 SDValue Temp;
2068 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2069 switch (Cond) {
2070 default: llvm_unreachable("Unknown integer setcc!");
2071 case ISD::SETEQ: // X == Y -> ~(X^Y)
2072 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2073 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2074 if (!DCI.isCalledByLegalizer())
2075 DCI.AddToWorklist(Temp.getNode());
2076 break;
2077 case ISD::SETNE: // X != Y --> (X^Y)
2078 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2079 break;
2080 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2081 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2082 Temp = DAG.getNOT(dl, N0, MVT::i1);
2083 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2084 if (!DCI.isCalledByLegalizer())
2085 DCI.AddToWorklist(Temp.getNode());
2086 break;
2087 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2088 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2089 Temp = DAG.getNOT(dl, N1, MVT::i1);
2090 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2091 if (!DCI.isCalledByLegalizer())
2092 DCI.AddToWorklist(Temp.getNode());
2093 break;
2094 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2095 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2096 Temp = DAG.getNOT(dl, N0, MVT::i1);
2097 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2098 if (!DCI.isCalledByLegalizer())
2099 DCI.AddToWorklist(Temp.getNode());
2100 break;
2101 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2102 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2103 Temp = DAG.getNOT(dl, N1, MVT::i1);
2104 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2105 break;
2106 }
2107 if (VT != MVT::i1) {
2108 if (!DCI.isCalledByLegalizer())
2109 DCI.AddToWorklist(N0.getNode());
2110 // FIXME: If running after legalize, we probably can't do this.
2111 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2112 }
2113 return N0;
2114 }
2115
2116 // Could not fold it.
2117 return SDValue();
2118 }
2119
2120 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2121 /// node is a GlobalAddress + offset.
2122 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2123 int64_t &Offset) const {
2124 if (isa<GlobalAddressSDNode>(N)) {
2125 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2126 GA = GASD->getGlobal();
2127 Offset += GASD->getOffset();
2128 return true;
2129 }
2130
2131 if (N->getOpcode() == ISD::ADD) {
2132 SDValue N1 = N->getOperand(0);
2133 SDValue N2 = N->getOperand(1);
2134 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2135 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2136 if (V) {
2137 Offset += V->getSExtValue();
2138 return true;
2139 }
2140 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2141 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2142 if (V) {
2143 Offset += V->getSExtValue();
2144 return true;
2145 }
2146 }
2147 }
2148 return false;
2149 }
2150
2151
2152 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
2153 /// location that is 'Dist' units away from the location that the 'Base' load
2154 /// is loading from.
2155 bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
2156 unsigned Bytes, int Dist,
2157 const MachineFrameInfo *MFI) const {
2158 if (LD->getChain() != Base->getChain())
2159 return false;
2160 EVT VT = LD->getValueType(0);
2161 if (VT.getSizeInBits() / 8 != Bytes)
2162 return false;
2163
2164 SDValue Loc = LD->getOperand(1);
2165 SDValue BaseLoc = Base->getOperand(1);
2166 if (Loc.getOpcode() == ISD::FrameIndex) {
2167 if (BaseLoc.getOpcode() != ISD::FrameIndex)
2168 return false;
2169 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
2170 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2171 int FS = MFI->getObjectSize(FI);
2172 int BFS = MFI->getObjectSize(BFI);
2173 if (FS != BFS || FS != (int)Bytes) return false;
2174 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2175 }
2176 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) {
2177 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1));
2178 if (V && (V->getSExtValue() == Dist*Bytes))
2179 return true;
2180 }
2181
2182 GlobalValue *GV1 = NULL;
2183 GlobalValue *GV2 = NULL;
2184 int64_t Offset1 = 0;
2185 int64_t Offset2 = 0;
2186 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2187 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2188 if (isGA1 && isGA2 && GV1 == GV2)
2189 return Offset1 == (Offset2 + Dist*Bytes);
2190 return false;
2191 }
2192
2193
2194 SDValue TargetLowering::
2195 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2196 // Default implementation: no optimization.
2197 return SDValue();
2198 }
2199
2200 //===----------------------------------------------------------------------===//
2201 // Inline Assembler Implementation Methods
2202 //===----------------------------------------------------------------------===//
2203
2204
2205 TargetLowering::ConstraintType
2206 TargetLowering::getConstraintType(const std::string &Constraint) const {
2207 // FIXME: lots more standard ones to handle.
2208 if (Constraint.size() == 1) {
2209 switch (Constraint[0]) {
2210 default: break;
2211 case 'r': return C_RegisterClass;
2212 case 'm': // memory
2213 case 'o': // offsetable
2214 case 'V': // not offsetable
2215 return C_Memory;
2216 case 'i': // Simple Integer or Relocatable Constant
2217 case 'n': // Simple Integer
2218 case 's': // Relocatable Constant
2219 case 'X': // Allow ANY value.
2220 case 'I': // Target registers.
2221 case 'J':
2222 case 'K':
2223 case 'L':
2224 case 'M':
2225 case 'N':
2226 case 'O':
2227 case 'P':
2228 return C_Other;
2229 }
2230 }
2231
2232 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2233 Constraint[Constraint.size()-1] == '}')
2234 return C_Register;
2235 return C_Unknown;
2236 }
2237
2238 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2239 /// with another that has more specific requirements based on the type of the
2240 /// corresponding operand.
2241 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2242 if (ConstraintVT.isInteger())
2243 return "r";
2244 if (ConstraintVT.isFloatingPoint())
2245 return "f"; // works for many targets
2246 return 0;
2247 }
2248
2249 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2250 /// vector. If it is invalid, don't add anything to Ops.
2251 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2252 char ConstraintLetter,
2253 bool hasMemory,
2254 std::vector<SDValue> &Ops,
2255 SelectionDAG &DAG) const {
2256 switch (ConstraintLetter) {
2257 default: break;
2258 case 'X': // Allows any operand; labels (basic block) use this.
2259 if (Op.getOpcode() == ISD::BasicBlock) {
2260 Ops.push_back(Op);
2261 return;
2262 }
2263 // fall through
2264 case 'i': // Simple Integer or Relocatable Constant
2265 case 'n': // Simple Integer
2266 case 's': { // Relocatable Constant
2267 // These operands are interested in values of the form (GV+C), where C may
2268 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2269 // is possible and fine if either GV or C are missing.
2270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2271 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2272
2273 // If we have "(add GV, C)", pull out GV/C
2274 if (Op.getOpcode() == ISD::ADD) {
2275 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2276 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2277 if (C == 0 || GA == 0) {
2278 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2279 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2280 }
2281 if (C == 0 || GA == 0)
2282 C = 0, GA = 0;
2283 }
2284
2285 // If we find a valid operand, map to the TargetXXX version so that the
2286 // value itself doesn't get selected.
2287 if (GA) { // Either &GV or &GV+C
2288 if (ConstraintLetter != 'n') {
2289 int64_t Offs = GA->getOffset();
2290 if (C) Offs += C->getZExtValue();
2291 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2292 Op.getValueType(), Offs));
2293 return;
2294 }
2295 }
2296 if (C) { // just C, no GV.
2297 // Simple constants are not allowed for 's'.
2298 if (ConstraintLetter != 's') {
2299 // gcc prints these as sign extended. Sign extend value to 64 bits
2300 // now; without this it would get ZExt'd later in
2301 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2302 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2303 MVT::i64));
2304 return;
2305 }
2306 }
2307 break;
2308 }
2309 }
2310 }
2311
2312 std::vector<unsigned> TargetLowering::
2313 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2314 EVT VT) const {
2315 return std::vector<unsigned>();
2316 }
2317
2318
2319 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2320 getRegForInlineAsmConstraint(const std::string &Constraint,
2321 EVT VT) const {
2322 if (Constraint[0] != '{')
2323 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2324 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2325
2326 // Remove the braces from around the name.
2327 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2328
2329 // Figure out which register class contains this reg.
2330 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2331 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2332 E = RI->regclass_end(); RCI != E; ++RCI) {
2333 const TargetRegisterClass *RC = *RCI;
2334
2335 // If none of the the value types for this register class are valid, we
2336 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2337 bool isLegal = false;
2338 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2339 I != E; ++I) {
2340 if (isTypeLegal(*I)) {
2341 isLegal = true;
2342 break;
2343 }
2344 }
2345
2346 if (!isLegal) continue;
2347
2348 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2349 I != E; ++I) {
2350 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
2351 return std::make_pair(*I, RC);
2352 }
2353 }
2354
2355 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2356 }
2357
2358 //===----------------------------------------------------------------------===//
2359 // Constraint Selection.
2360
2361 /// isMatchingInputConstraint - Return true of this is an input operand that is
2362 /// a matching constraint like "4".
2363 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2364 assert(!ConstraintCode.empty() && "No known constraint!");
2365 return isdigit(ConstraintCode[0]);
2366 }
2367
2368 /// getMatchedOperand - If this is an input matching constraint, this method
2369 /// returns the output operand it matches.
2370 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2371 assert(!ConstraintCode.empty() && "No known constraint!");
2372 return atoi(ConstraintCode.c_str());
2373 }
2374
2375
2376 /// getConstraintGenerality - Return an integer indicating how general CT
2377 /// is.
2378 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2379 switch (CT) {
2380 default: llvm_unreachable("Unknown constraint type!");
2381 case TargetLowering::C_Other:
2382 case TargetLowering::C_Unknown:
2383 return 0;
2384 case TargetLowering::C_Register:
2385 return 1;
2386 case TargetLowering::C_RegisterClass:
2387 return 2;
2388 case TargetLowering::C_Memory:
2389 return 3;
2390 }
2391 }
2392
2393 /// ChooseConstraint - If there are multiple different constraints that we
2394 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2395 /// This is somewhat tricky: constraints fall into four classes:
2396 /// Other -> immediates and magic values
2397 /// Register -> one specific register
2398 /// RegisterClass -> a group of regs
2399 /// Memory -> memory
2400 /// Ideally, we would pick the most specific constraint possible: if we have
2401 /// something that fits into a register, we would pick it. The problem here
2402 /// is that if we have something that could either be in a register or in
2403 /// memory that use of the register could cause selection of *other*
2404 /// operands to fail: they might only succeed if we pick memory. Because of
2405 /// this the heuristic we use is:
2406 ///
2407 /// 1) If there is an 'other' constraint, and if the operand is valid for
2408 /// that constraint, use it. This makes us take advantage of 'i'
2409 /// constraints when available.
2410 /// 2) Otherwise, pick the most general constraint present. This prefers
2411 /// 'm' over 'r', for example.
2412 ///
2413 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2414 bool hasMemory, const TargetLowering &TLI,
2415 SDValue Op, SelectionDAG *DAG) {
2416 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2417 unsigned BestIdx = 0;
2418 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2419 int BestGenerality = -1;
2420
2421 // Loop over the options, keeping track of the most general one.
2422 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2423 TargetLowering::ConstraintType CType =
2424 TLI.getConstraintType(OpInfo.Codes[i]);
2425
2426 // If this is an 'other' constraint, see if the operand is valid for it.
2427 // For example, on X86 we might have an 'rI' constraint. If the operand
2428 // is an integer in the range [0..31] we want to use I (saving a load
2429 // of a register), otherwise we must use 'r'.
2430 if (CType == TargetLowering::C_Other && Op.getNode()) {
2431 assert(OpInfo.Codes[i].size() == 1 &&
2432 "Unhandled multi-letter 'other' constraint");
2433 std::vector<SDValue> ResultOps;
2434 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2435 ResultOps, *DAG);
2436 if (!ResultOps.empty()) {
2437 BestType = CType;
2438 BestIdx = i;
2439 break;
2440 }
2441 }
2442
2443 // This constraint letter is more general than the previous one, use it.
2444 int Generality = getConstraintGenerality(CType);
2445 if (Generality > BestGenerality) {
2446 BestType = CType;
2447 BestIdx = i;
2448 BestGenerality = Generality;
2449 }
2450 }
2451
2452 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2453 OpInfo.ConstraintType = BestType;
2454 }
2455
2456 /// ComputeConstraintToUse - Determines the constraint code and constraint
2457 /// type to use for the specific AsmOperandInfo, setting
2458 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2459 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2460 SDValue Op,
2461 bool hasMemory,
2462 SelectionDAG *DAG) const {
2463 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2464
2465 // Single-letter constraints ('r') are very common.
2466 if (OpInfo.Codes.size() == 1) {
2467 OpInfo.ConstraintCode = OpInfo.Codes[0];
2468 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2469 } else {
2470 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2471 }
2472
2473 // 'X' matches anything.
2474 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2475 // Labels and constants are handled elsewhere ('X' is the only thing
2476 // that matches labels). For Functions, the type here is the type of
2477 // the result, which is not what we want to look at; leave them alone.
2478 Value *v = OpInfo.CallOperandVal;
2479 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2480 OpInfo.CallOperandVal = v;
2481 return;
2482 }
2483
2484 // Otherwise, try to resolve it to something we know about by looking at
2485 // the actual operand type.
2486 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2487 OpInfo.ConstraintCode = Repl;
2488 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2489 }
2490 }
2491 }
2492
2493 //===----------------------------------------------------------------------===//
2494 // Loop Strength Reduction hooks
2495 //===----------------------------------------------------------------------===//
2496
2497 /// isLegalAddressingMode - Return true if the addressing mode represented
2498 /// by AM is legal for this target, for a load/store of the specified type.
2499 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2500 const Type *Ty) const {
2501 // The default implementation of this implements a conservative RISCy, r+r and
2502 // r+i addr mode.
2503
2504 // Allows a sign-extended 16-bit immediate field.
2505 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2506 return false;
2507
2508 // No global is ever allowed as a base.
2509 if (AM.BaseGV)
2510 return false;
2511
2512 // Only support r+r,
2513 switch (AM.Scale) {
2514 case 0: // "r+i" or just "i", depending on HasBaseReg.
2515 break;
2516 case 1:
2517 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2518 return false;
2519 // Otherwise we have r+r or r+i.
2520 break;
2521 case 2:
2522 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2523 return false;
2524 // Allow 2*r as r+r.
2525 break;
2526 }
2527
2528 return true;
2529 }
2530
2531 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2532 /// return a DAG expression to select that will generate the same value by
2533 /// multiplying by a magic number. See:
2534 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2535 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2536 std::vector<SDNode*>* Created) const {
2537 EVT VT = N->getValueType(0);
2538 DebugLoc dl= N->getDebugLoc();
2539
2540 // Check to see if we can do this.
2541 // FIXME: We should be more aggressive here.
2542 if (!isTypeLegal(VT))
2543 return SDValue();
2544
2545 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2546 APInt::ms magics = d.magic();
2547
2548 // Multiply the numerator (operand 0) by the magic value
2549 // FIXME: We should support doing a MUL in a wider type
2550 SDValue Q;
2551 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2552 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2553 DAG.getConstant(magics.m, VT));
2554 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2555 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2556 N->getOperand(0),
2557 DAG.getConstant(magics.m, VT)).getNode(), 1);
2558 else
2559 return SDValue(); // No mulhs or equvialent
2560 // If d > 0 and m < 0, add the numerator
2561 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2562 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2563 if (Created)
2564 Created->push_back(Q.getNode());
2565 }
2566 // If d < 0 and m > 0, subtract the numerator.
2567 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2568 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2569 if (Created)
2570 Created->push_back(Q.getNode());
2571 }
2572 // Shift right algebraic if shift value is nonzero
2573 if (magics.s > 0) {
2574 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2575 DAG.getConstant(magics.s, getShiftAmountTy()));
2576 if (Created)
2577 Created->push_back(Q.getNode());
2578 }
2579 // Extract the sign bit and add it to the quotient
2580 SDValue T =
2581 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2582 getShiftAmountTy()));
2583 if (Created)
2584 Created->push_back(T.getNode());
2585 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2586 }
2587
2588 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2589 /// return a DAG expression to select that will generate the same value by
2590 /// multiplying by a magic number. See:
2591 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2592 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2593 std::vector<SDNode*>* Created) const {
2594 EVT VT = N->getValueType(0);
2595 DebugLoc dl = N->getDebugLoc();
2596
2597 // Check to see if we can do this.
2598 // FIXME: We should be more aggressive here.
2599 if (!isTypeLegal(VT))
2600 return SDValue();
2601
2602 // FIXME: We should use a narrower constant when the upper
2603 // bits are known to be zero.
2604 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2605 APInt::mu magics = N1C->getAPIntValue().magicu();
2606
2607 // Multiply the numerator (operand 0) by the magic value
2608 // FIXME: We should support doing a MUL in a wider type
2609 SDValue Q;
2610 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2611 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2612 DAG.getConstant(magics.m, VT));
2613 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2614 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2615 N->getOperand(0),
2616 DAG.getConstant(magics.m, VT)).getNode(), 1);
2617 else
2618 return SDValue(); // No mulhu or equvialent
2619 if (Created)
2620 Created->push_back(Q.getNode());
2621
2622 if (magics.a == 0) {
2623 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2624 "We shouldn't generate an undefined shift!");
2625 return DAG.getNode(ISD::SRL, dl, VT, Q,
2626 DAG.getConstant(magics.s, getShiftAmountTy()));
2627 } else {
2628 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2629 if (Created)
2630 Created->push_back(NPQ.getNode());
2631 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2632 DAG.getConstant(1, getShiftAmountTy()));
2633 if (Created)
2634 Created->push_back(NPQ.getNode());
2635 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2636 if (Created)
2637 Created->push_back(NPQ.getNode());
2638 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2639 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2640 }
2641 }
AVR Backend for LLVM