lib/Target/CellSPU/SPUISelLowering.h

   1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
  11 // a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPU_ISELLOWERING_H
  16 #define SPU_ISELLOWERING_H
  17
  18 #include "llvm/Target/TargetLowering.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "SPU.h"
  21
  22 namespace llvm {
  23   namespace SPUISD {
  24     enum NodeType {
  25       // Start the numbering where the builting ops and target ops leave off.
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27
  28       // Pseudo instructions:
  29       RET_FLAG,                 ///< Return with flag, matched by bi instruction
  30
  31       Hi,                       ///< High address component (upper 16)
  32       Lo,                       ///< Low address component (lower 16)
  33       PCRelAddr,                ///< Program counter relative address
  34       AFormAddr,                ///< A-form address (local store)
  35       IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
  36
  37       LDRESULT,                 ///< Load result (value, chain)
  38       CALL,                     ///< CALL instruction
  39       SHUFB,                    ///< Vector shuffle (permute)
  40       SHUFFLE_MASK,             ///< Shuffle mask
  41       CNTB,                     ///< Count leading ones in bytes
  42       PREFSLOT2VEC,             ///< Promote scalar->vector
  43       VEC2PREFSLOT,             ///< Extract element 0
  44       SHLQUAD_L_BITS,           ///< Rotate quad left, by bits
  45       SHLQUAD_L_BYTES,          ///< Rotate quad left, by bytes
  46       VEC_SHL,                  ///< Vector shift left
  47       VEC_SRL,                  ///< Vector shift right (logical)
  48       VEC_SRA,                  ///< Vector shift right (arithmetic)
  49       VEC_ROTL,                 ///< Vector rotate left
  50       VEC_ROTR,                 ///< Vector rotate right
  51       ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
  52       ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
  53       SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
  54       SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
  55       // Markers: These aren't used to generate target-dependent nodes, but
  56       // are used during instruction selection.
  57       ADD64_MARKER,             ///< i64 addition marker
  58       SUB64_MARKER,             ///< i64 subtraction marker
  59       MUL64_MARKER,             ///< i64 multiply marker
  60       LAST_SPUISD               ///< Last user-defined instruction
  61     };
  62   }
  63
  64   //! Utility functions specific to CellSPU:
  65   namespace SPU {
  66     SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
  67                              EVT ValueType);
  68     SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
  69                              EVT ValueType);
  70     SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
  71                              EVT ValueType);
  72     SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
  73                             EVT ValueType);
  74     SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
  75                               EVT ValueType);
  76     SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
  77     SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
  78
  79     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
  80                               const SPUTargetMachine &TM);
  81     //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
  82     SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
  83                              DebugLoc dl);
  84   }
  85
  86   class SPUTargetMachine;            // forward dec'l.
  87
  88   class SPUTargetLowering :
  89     public TargetLowering
  90   {
  91     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
  92     SPUTargetMachine &SPUTM;
  93
  94   public:
  95     //! The venerable constructor
  96     /*!
  97      This is where the CellSPU backend sets operation handling (i.e., legal,
  98      custom, expand or promote.)
  99      */
 100     SPUTargetLowering(SPUTargetMachine &TM);
 101
 102     //! Get the target machine
 103     SPUTargetMachine &getSPUTargetMachine() {
 104       return SPUTM;
 105     }
 106
 107     /// getTargetNodeName() - This method returns the name of a target specific
 108     /// DAG node.
 109     virtual const char *getTargetNodeName(unsigned Opcode) const;
 110
 111     /// getSetCCResultType - Return the ValueType for ISD::SETCC
 112     virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
 113
 114     //! Custom lowering hooks
 115     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
 116
 117     //! Custom lowering hook for nodes with illegal result types.
 118     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 119                                     SelectionDAG &DAG);
 120
 121     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 122
 123     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 124                                                 const APInt &Mask,
 125                                                 APInt &KnownZero,
 126                                                 APInt &KnownOne,
 127                                                 const SelectionDAG &DAG,
 128                                                 unsigned Depth = 0) const;
 129
 130     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
 131                                                    unsigned Depth = 0) const;
 132
 133     ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
 134
 135     std::pair<unsigned, const TargetRegisterClass*>
 136       getRegForInlineAsmConstraint(const std::string &Constraint,
 137                                    EVT VT) const;
 138
 139     void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
 140                                       bool hasMemory,
 141                                       std::vector<SDValue> &Ops,
 142                                       SelectionDAG &DAG) const;
 143
 144     /// isLegalAddressImmediate - Return true if the integer value can be used
 145     /// as the offset of the target addressing mode.
 146     virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
 147     virtual bool isLegalAddressImmediate(GlobalValue *) const;
 148
 149     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 150
 151     /// getFunctionAlignment - Return the Log2 alignment of this function.
 152     virtual unsigned getFunctionAlignment(const Function *F) const;
 153
 154     virtual SDValue
 155       LowerFormalArguments(SDValue Chain,
 156                            unsigned CallConv, bool isVarArg,
 157                            const SmallVectorImpl<ISD::InputArg> &Ins,
 158                            DebugLoc dl, SelectionDAG &DAG,
 159                            SmallVectorImpl<SDValue> &InVals);
 160
 161     virtual SDValue
 162       LowerCall(SDValue Chain, SDValue Callee,
 163                 unsigned CallConv, bool isVarArg,
 164                 bool isTailCall,
 165                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 166                 const SmallVectorImpl<ISD::InputArg> &Ins,
 167                 DebugLoc dl, SelectionDAG &DAG,
 168                 SmallVectorImpl<SDValue> &InVals);
 169
 170     virtual SDValue
 171       LowerReturn(SDValue Chain,
 172                   unsigned CallConv, bool isVarArg,
 173                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 174                   DebugLoc dl, SelectionDAG &DAG);
 175   };
 176 }
 177
 178 #endif