lib/Target/CellSPU/SPUInstrInfo.cpp

   1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SPURegisterNames.h"
  15 #include "SPUInstrInfo.h"
  16 #include "SPUInstrBuilder.h"
  17 #include "SPUTargetMachine.h"
  18 #include "SPUGenInstrInfo.inc"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/Support/Streams.h"
  21 #include "llvm/Support/Debug.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23
  24 using namespace llvm;
  25
  26 namespace {
  27   //! Predicate for an unconditional branch instruction
  28   inline bool isUncondBranch(const MachineInstr *I) {
  29     unsigned opc = I->getOpcode();
  30
  31     return (opc == SPU::BR
  32             || opc == SPU::BRA
  33             || opc == SPU::BI);
  34   }
  35
  36   //! Predicate for a conditional branch instruction
  37   inline bool isCondBranch(const MachineInstr *I) {
  38     unsigned opc = I->getOpcode();
  39
  40     return (opc == SPU::BRNZr32
  41             || opc == SPU::BRNZv4i32
  42             || opc == SPU::BRZr32
  43             || opc == SPU::BRZv4i32
  44             || opc == SPU::BRHNZr16
  45             || opc == SPU::BRHNZv8i16
  46             || opc == SPU::BRHZr16
  47             || opc == SPU::BRHZv8i16);
  48   }
  49 }
  50
  51 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
  52   : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
  53     TM(tm),
  54     RI(*TM.getSubtargetImpl(), *this)
  55 { /* NOP */ }
  56
  57 bool
  58 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
  59                           unsigned& sourceReg,
  60                           unsigned& destReg,
  61                           unsigned& SrcSR, unsigned& DstSR) const {
  62   SrcSR = DstSR = 0;  // No sub-registers.
  63
  64   switch (MI.getOpcode()) {
  65   default:
  66     break;
  67   case SPU::ORIv4i32:
  68   case SPU::ORIr32:
  69   case SPU::ORHIv8i16:
  70   case SPU::ORHIr16:
  71   case SPU::ORHIi8i16:
  72   case SPU::ORBIv16i8:
  73   case SPU::ORBIr8:
  74   case SPU::ORIi16i32:
  75   case SPU::ORIi8i32:
  76   case SPU::AHIvec:
  77   case SPU::AHIr16:
  78   case SPU::AIv4i32:
  79     assert(MI.getNumOperands() == 3 &&
  80            MI.getOperand(0).isReg() &&
  81            MI.getOperand(1).isReg() &&
  82            MI.getOperand(2).isImm() &&
  83            "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
  84     if (MI.getOperand(2).getImm() == 0) {
  85       sourceReg = MI.getOperand(1).getReg();
  86       destReg = MI.getOperand(0).getReg();
  87       return true;
  88     }
  89     break;
  90   case SPU::AIr32:
  91     assert(MI.getNumOperands() == 3 &&
  92            "wrong number of operands to AIr32");
  93     if (MI.getOperand(0).isReg() &&
  94         MI.getOperand(1).isReg() &&
  95         (MI.getOperand(2).isImm() &&
  96          MI.getOperand(2).getImm() == 0)) {
  97       sourceReg = MI.getOperand(1).getReg();
  98       destReg = MI.getOperand(0).getReg();
  99       return true;
 100     }
 101     break;
 102   case SPU::LRr8:
 103   case SPU::LRr16:
 104   case SPU::LRr32:
 105   case SPU::LRf32:
 106   case SPU::LRr64:
 107   case SPU::LRf64:
 108   case SPU::LRr128:
 109   case SPU::LRv16i8:
 110   case SPU::LRv8i16:
 111   case SPU::LRv4i32:
 112   case SPU::LRv4f32:
 113   case SPU::LRv2i64:
 114   case SPU::LRv2f64:
 115   case SPU::ORv16i8_i8:
 116   case SPU::ORv8i16_i16:
 117   case SPU::ORv4i32_i32:
 118   case SPU::ORv2i64_i64:
 119   case SPU::ORv4f32_f32:
 120   case SPU::ORv2f64_f64:
 121   case SPU::ORi8_v16i8:
 122   case SPU::ORi16_v8i16:
 123   case SPU::ORi32_v4i32:
 124   case SPU::ORi64_v2i64:
 125   case SPU::ORf32_v4f32:
 126   case SPU::ORf64_v2f64:
 127 /*
 128   case SPU::ORi128_r64:
 129   case SPU::ORi128_f64:
 130   case SPU::ORi128_r32:
 131   case SPU::ORi128_f32:
 132   case SPU::ORi128_r16:
 133   case SPU::ORi128_r8:
 134 */
 135   case SPU::ORi128_vec:
 136 /*
 137   case SPU::ORr64_i128:
 138   case SPU::ORf64_i128:
 139   case SPU::ORr32_i128:
 140   case SPU::ORf32_i128:
 141   case SPU::ORr16_i128:
 142   case SPU::ORr8_i128:
 143 */
 144   case SPU::ORvec_i128:
 145 /*
 146   case SPU::ORr16_r32:
 147   case SPU::ORr8_r32:
 148   case SPU::ORf32_r32:
 149   case SPU::ORr32_f32:
 150   case SPU::ORr32_r16:
 151   case SPU::ORr32_r8:
 152   case SPU::ORr16_r64:
 153   case SPU::ORr8_r64:
 154   case SPU::ORr64_r16:
 155   case SPU::ORr64_r8:
 156 */
 157   case SPU::ORr64_r32:
 158   case SPU::ORr32_r64:
 159   case SPU::ORf32_r32:
 160   case SPU::ORr32_f32:
 161   case SPU::ORf64_r64:
 162   case SPU::ORr64_f64: {
 163     assert(MI.getNumOperands() == 2 &&
 164            MI.getOperand(0).isReg() &&
 165            MI.getOperand(1).isReg() &&
 166            "invalid SPU OR<type>_<vec> or LR instruction!");
 167     if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
 168       sourceReg = MI.getOperand(1).getReg();
 169       destReg = MI.getOperand(0).getReg();
 170       return true;
 171     }
 172     break;
 173   }
 174   case SPU::ORv16i8:
 175   case SPU::ORv8i16:
 176   case SPU::ORv4i32:
 177   case SPU::ORv2i64:
 178   case SPU::ORr8:
 179   case SPU::ORr16:
 180   case SPU::ORr32:
 181   case SPU::ORr64:
 182   case SPU::ORr128:
 183   case SPU::ORf32:
 184   case SPU::ORf64:
 185     assert(MI.getNumOperands() == 3 &&
 186            MI.getOperand(0).isReg() &&
 187            MI.getOperand(1).isReg() &&
 188            MI.getOperand(2).isReg() &&
 189            "invalid SPU OR(vec|r32|r64|gprc) instruction!");
 190     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
 191       sourceReg = MI.getOperand(1).getReg();
 192       destReg = MI.getOperand(0).getReg();
 193       return true;
 194     }
 195     break;
 196   }
 197
 198   return false;
 199 }
 200
 201 unsigned
 202 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
 203                                   int &FrameIndex) const {
 204   switch (MI->getOpcode()) {
 205   default: break;
 206   case SPU::LQDv16i8:
 207   case SPU::LQDv8i16:
 208   case SPU::LQDv4i32:
 209   case SPU::LQDv4f32:
 210   case SPU::LQDv2f64:
 211   case SPU::LQDr128:
 212   case SPU::LQDr64:
 213   case SPU::LQDr32:
 214   case SPU::LQDr16: {
 215     const MachineOperand MOp1 = MI->getOperand(1);
 216     const MachineOperand MOp2 = MI->getOperand(2);
 217     if (MOp1.isImm() && MOp2.isFI()) {
 218       FrameIndex = MOp2.getIndex();
 219       return MI->getOperand(0).getReg();
 220     }
 221     break;
 222   }
 223   }
 224   return 0;
 225 }
 226
 227 unsigned
 228 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
 229                                  int &FrameIndex) const {
 230   switch (MI->getOpcode()) {
 231   default: break;
 232   case SPU::STQDv16i8:
 233   case SPU::STQDv8i16:
 234   case SPU::STQDv4i32:
 235   case SPU::STQDv4f32:
 236   case SPU::STQDv2f64:
 237   case SPU::STQDr128:
 238   case SPU::STQDr64:
 239   case SPU::STQDr32:
 240   case SPU::STQDr16:
 241   case SPU::STQDr8: {
 242     const MachineOperand MOp1 = MI->getOperand(1);
 243     const MachineOperand MOp2 = MI->getOperand(2);
 244     if (MOp1.isImm() && MOp2.isFI()) {
 245       FrameIndex = MOp2.getIndex();
 246       return MI->getOperand(0).getReg();
 247     }
 248     break;
 249   }
 250   }
 251   return 0;
 252 }
 253
 254 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 255                                    MachineBasicBlock::iterator MI,
 256                                    unsigned DestReg, unsigned SrcReg,
 257                                    const TargetRegisterClass *DestRC,
 258                                    const TargetRegisterClass *SrcRC) const
 259 {
 260   // We support cross register class moves for our aliases, such as R3 in any
 261   // reg class to any other reg class containing R3.  This is required because
 262   // we instruction select bitconvert i64 -> f64 as a noop for example, so our
 263   // types have no specific meaning.
 264
 265   DebugLoc DL = DebugLoc::getUnknownLoc();
 266   if (MI != MBB.end()) DL = MI->getDebugLoc();
 267
 268   if (DestRC == SPU::R8CRegisterClass) {
 269     BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
 270   } else if (DestRC == SPU::R16CRegisterClass) {
 271     BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
 272   } else if (DestRC == SPU::R32CRegisterClass) {
 273     BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
 274   } else if (DestRC == SPU::R32FPRegisterClass) {
 275     BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
 276   } else if (DestRC == SPU::R64CRegisterClass) {
 277     BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
 278   } else if (DestRC == SPU::R64FPRegisterClass) {
 279     BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
 280   } else if (DestRC == SPU::GPRCRegisterClass) {
 281     BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
 282   } else if (DestRC == SPU::VECREGRegisterClass) {
 283     BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
 284   } else {
 285     // Attempt to copy unknown/unsupported register class!
 286     return false;
 287   }
 288
 289   return true;
 290 }
 291
 292 void
 293 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 294                                      MachineBasicBlock::iterator MI,
 295                                      unsigned SrcReg, bool isKill, int FrameIdx,
 296                                      const TargetRegisterClass *RC) const
 297 {
 298   unsigned opc;
 299   bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
 300   if (RC == SPU::GPRCRegisterClass) {
 301     opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
 302   } else if (RC == SPU::R64CRegisterClass) {
 303     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 304   } else if (RC == SPU::R64FPRegisterClass) {
 305     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 306   } else if (RC == SPU::R32CRegisterClass) {
 307     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 308   } else if (RC == SPU::R32FPRegisterClass) {
 309     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 310   } else if (RC == SPU::R16CRegisterClass) {
 311     opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
 312   } else if (RC == SPU::R8CRegisterClass) {
 313     opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
 314   } else if (RC == SPU::VECREGRegisterClass) {
 315     opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
 316   } else {
 317     llvm_unreachable("Unknown regclass!");
 318   }
 319
 320   DebugLoc DL = DebugLoc::getUnknownLoc();
 321   if (MI != MBB.end()) DL = MI->getDebugLoc();
 322   addFrameReference(BuildMI(MBB, MI, DL, get(opc))
 323                     .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
 324 }
 325
 326 void
 327 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 328                                         MachineBasicBlock::iterator MI,
 329                                         unsigned DestReg, int FrameIdx,
 330                                         const TargetRegisterClass *RC) const
 331 {
 332   unsigned opc;
 333   bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
 334   if (RC == SPU::GPRCRegisterClass) {
 335     opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
 336   } else if (RC == SPU::R64CRegisterClass) {
 337     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 338   } else if (RC == SPU::R64FPRegisterClass) {
 339     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 340   } else if (RC == SPU::R32CRegisterClass) {
 341     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 342   } else if (RC == SPU::R32FPRegisterClass) {
 343     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 344   } else if (RC == SPU::R16CRegisterClass) {
 345     opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
 346   } else if (RC == SPU::R8CRegisterClass) {
 347     opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
 348   } else if (RC == SPU::VECREGRegisterClass) {
 349     opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
 350   } else {
 351     llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
 352   }
 353
 354   DebugLoc DL = DebugLoc::getUnknownLoc();
 355   if (MI != MBB.end()) DL = MI->getDebugLoc();
 356   addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
 357 }
 358
 359 //! Return true if the specified load or store can be folded
 360 bool
 361 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
 362                                    const SmallVectorImpl<unsigned> &Ops) const {
 363   if (Ops.size() != 1) return false;
 364
 365   // Make sure this is a reg-reg copy.
 366   unsigned Opc = MI->getOpcode();
 367
 368   switch (Opc) {
 369   case SPU::ORv16i8:
 370   case SPU::ORv8i16:
 371   case SPU::ORv4i32:
 372   case SPU::ORv2i64:
 373   case SPU::ORr8:
 374   case SPU::ORr16:
 375   case SPU::ORr32:
 376   case SPU::ORr64:
 377   case SPU::ORf32:
 378   case SPU::ORf64:
 379     if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
 380       return true;
 381     break;
 382   }
 383
 384   return false;
 385 }
 386
 387 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
 388 /// copy instructions, turning them into load/store instructions.
 389 MachineInstr *
 390 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 391                                     MachineInstr *MI,
 392                                     const SmallVectorImpl<unsigned> &Ops,
 393                                     int FrameIndex) const
 394 {
 395   if (Ops.size() != 1) return 0;
 396
 397   unsigned OpNum = Ops[0];
 398   unsigned Opc = MI->getOpcode();
 399   MachineInstr *NewMI = 0;
 400
 401   switch (Opc) {
 402   case SPU::ORv16i8:
 403   case SPU::ORv8i16:
 404   case SPU::ORv4i32:
 405   case SPU::ORv2i64:
 406   case SPU::ORr8:
 407   case SPU::ORr16:
 408   case SPU::ORr32:
 409   case SPU::ORr64:
 410   case SPU::ORf32:
 411   case SPU::ORf64:
 412     if (OpNum == 0) {  // move -> store
 413       unsigned InReg = MI->getOperand(1).getReg();
 414       bool isKill = MI->getOperand(1).isKill();
 415       bool isUndef = MI->getOperand(1).isUndef();
 416       if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
 417         MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
 418                                           get(SPU::STQDr32));
 419
 420         MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef));
 421         NewMI = addFrameReference(MIB, FrameIndex);
 422       }
 423     } else {           // move -> load
 424       unsigned OutReg = MI->getOperand(0).getReg();
 425       bool isDead = MI->getOperand(0).isDead();
 426       bool isUndef = MI->getOperand(0).isUndef();
 427       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
 428
 429       MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
 430                  getUndefRegState(isUndef));
 431       Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
 432         ? SPU::STQDr32 : SPU::STQXr32;
 433       NewMI = addFrameReference(MIB, FrameIndex);
 434     break;
 435   }
 436   }
 437
 438   return NewMI;
 439 }
 440
 441 //! Branch analysis
 442 /*!
 443   \note This code was kiped from PPC. There may be more branch analysis for
 444   CellSPU than what's currently done here.
 445  */
 446 bool
 447 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 448                             MachineBasicBlock *&FBB,
 449                             SmallVectorImpl<MachineOperand> &Cond,
 450                             bool AllowModify) const {
 451   // If the block has no terminators, it just falls into the block after it.
 452   MachineBasicBlock::iterator I = MBB.end();
 453   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 454     return false;
 455
 456   // Get the last instruction in the block.
 457   MachineInstr *LastInst = I;
 458
 459   // If there is only one terminator instruction, process it.
 460   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 461     if (isUncondBranch(LastInst)) {
 462       TBB = LastInst->getOperand(0).getMBB();
 463       return false;
 464     } else if (isCondBranch(LastInst)) {
 465       // Block ends with fall-through condbranch.
 466       TBB = LastInst->getOperand(1).getMBB();
 467       DEBUG(cerr << "Pushing LastInst:               ");
 468       DEBUG(LastInst->dump());
 469       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
 470       Cond.push_back(LastInst->getOperand(0));
 471       return false;
 472     }
 473     // Otherwise, don't know what this is.
 474     return true;
 475   }
 476
 477   // Get the instruction before it if it's a terminator.
 478   MachineInstr *SecondLastInst = I;
 479
 480   // If there are three terminators, we don't know what sort of block this is.
 481   if (SecondLastInst && I != MBB.begin() &&
 482       isUnpredicatedTerminator(--I))
 483     return true;
 484
 485   // If the block ends with a conditional and unconditional branch, handle it.
 486   if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 487     TBB =  SecondLastInst->getOperand(1).getMBB();
 488     DEBUG(cerr << "Pushing SecondLastInst:         ");
 489     DEBUG(SecondLastInst->dump());
 490     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
 491     Cond.push_back(SecondLastInst->getOperand(0));
 492     FBB = LastInst->getOperand(0).getMBB();
 493     return false;
 494   }
 495
 496   // If the block ends with two unconditional branches, handle it.  The second
 497   // one is not executed, so remove it.
 498   if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 499     TBB = SecondLastInst->getOperand(0).getMBB();
 500     I = LastInst;
 501     if (AllowModify)
 502       I->eraseFromParent();
 503     return false;
 504   }
 505
 506   // Otherwise, can't handle this.
 507   return true;
 508 }
 509
 510 unsigned
 511 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 512   MachineBasicBlock::iterator I = MBB.end();
 513   if (I == MBB.begin())
 514     return 0;
 515   --I;
 516   if (!isCondBranch(I) && !isUncondBranch(I))
 517     return 0;
 518
 519   // Remove the first branch.
 520   DEBUG(cerr << "Removing branch:                ");
 521   DEBUG(I->dump());
 522   I->eraseFromParent();
 523   I = MBB.end();
 524   if (I == MBB.begin())
 525     return 1;
 526
 527   --I;
 528   if (!(isCondBranch(I) || isUncondBranch(I)))
 529     return 1;
 530
 531   // Remove the second branch.
 532   DEBUG(cerr << "Removing second branch:         ");
 533   DEBUG(I->dump());
 534   I->eraseFromParent();
 535   return 2;
 536 }
 537
 538 unsigned
 539 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 540                            MachineBasicBlock *FBB,
 541                            const SmallVectorImpl<MachineOperand> &Cond) const {
 542   // FIXME this should probably have a DebugLoc argument
 543   DebugLoc dl = DebugLoc::getUnknownLoc();
 544   // Shouldn't be a fall through.
 545   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 546   assert((Cond.size() == 2 || Cond.size() == 0) &&
 547          "SPU branch conditions have two components!");
 548
 549   // One-way branch.
 550   if (FBB == 0) {
 551     if (Cond.empty()) {
 552       // Unconditional branch
 553       MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
 554       MIB.addMBB(TBB);
 555
 556       DEBUG(cerr << "Inserted one-way uncond branch: ");
 557       DEBUG((*MIB).dump());
 558     } else {
 559       // Conditional branch
 560       MachineInstrBuilder  MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
 561       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 562
 563       DEBUG(cerr << "Inserted one-way cond branch:   ");
 564       DEBUG((*MIB).dump());
 565     }
 566     return 1;
 567   } else {
 568     MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
 569     MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
 570
 571     // Two-way Conditional Branch.
 572     MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 573     MIB2.addMBB(FBB);
 574
 575     DEBUG(cerr << "Inserted conditional branch:    ");
 576     DEBUG((*MIB).dump());
 577     DEBUG(cerr << "part 2: ");
 578     DEBUG((*MIB2).dump());
 579    return 2;
 580   }
 581 }
 582
 583 bool
 584 SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 585   return (!MBB.empty() && isUncondBranch(&MBB.back()));
 586 }
 587 //! Reverses a branch's condition, returning false on success.
 588 bool
 589 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
 590   const {
 591   // Pretty brainless way of inverting the condition, but it works, considering
 592   // there are only two conditions...
 593   static struct {
 594     unsigned Opc;               //! The incoming opcode
 595     unsigned RevCondOpc;        //! The reversed condition opcode
 596   } revconds[] = {
 597     { SPU::BRNZr32, SPU::BRZr32 },
 598     { SPU::BRNZv4i32, SPU::BRZv4i32 },
 599     { SPU::BRZr32, SPU::BRNZr32 },
 600     { SPU::BRZv4i32, SPU::BRNZv4i32 },
 601     { SPU::BRHNZr16, SPU::BRHZr16 },
 602     { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
 603     { SPU::BRHZr16, SPU::BRHNZr16 },
 604     { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
 605   };
 606
 607   unsigned Opc = unsigned(Cond[0].getImm());
 608   // Pretty dull mapping between the two conditions that SPU can generate:
 609   for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
 610     if (revconds[i].Opc == Opc) {
 611       Cond[0].setImm(revconds[i].RevCondOpc);
 612       return false;
 613     }
 614   }
 615
 616   return true;
 617 }