lib/Target/Mips/MipsInstrInfo.cpp

   1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MipsInstrInfo.h"
  15 #include "MipsTargetMachine.h"
  16 #include "MipsMachineFunction.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "MipsGenInstrInfo.inc"
  22
  23 using namespace llvm;
  24
  25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
  26   : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
  27     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
  28
  29 static bool isZeroImm(const MachineOperand &op) {
  30   return op.isImm() && op.getImm() == 0;
  31 }
  32
  33 /// Return true if the instruction is a register to register move and
  34 /// leave the source and dest operands in the passed parameters.
  35 bool MipsInstrInfo::
  36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
  37             unsigned &SrcSubIdx, unsigned &DstSubIdx) const
  38 {
  39   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
  40
  41   // addu $dst, $src, $zero || addu $dst, $zero, $src
  42   // or   $dst, $src, $zero || or   $dst, $zero, $src
  43   if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
  44     if (MI.getOperand(1).getReg() == Mips::ZERO) {
  45       DstReg = MI.getOperand(0).getReg();
  46       SrcReg = MI.getOperand(2).getReg();
  47       return true;
  48     } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
  49       DstReg = MI.getOperand(0).getReg();
  50       SrcReg = MI.getOperand(1).getReg();
  51       return true;
  52     }
  53   }
  54
  55   // mov $fpDst, $fpSrc
  56   // mfc $gpDst, $fpSrc
  57   // mtc $fpDst, $gpSrc
  58   if (MI.getOpcode() == Mips::FMOV_S32 ||
  59       MI.getOpcode() == Mips::FMOV_D32 ||
  60       MI.getOpcode() == Mips::MFC1 ||
  61       MI.getOpcode() == Mips::MTC1 ||
  62       MI.getOpcode() == Mips::MOVCCRToCCR) {
  63     DstReg = MI.getOperand(0).getReg();
  64     SrcReg = MI.getOperand(1).getReg();
  65     return true;
  66   }
  67
  68   // addiu $dst, $src, 0
  69   if (MI.getOpcode() == Mips::ADDiu) {
  70     if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
  71       DstReg = MI.getOperand(0).getReg();
  72       SrcReg = MI.getOperand(1).getReg();
  73       return true;
  74     }
  75   }
  76
  77   return false;
  78 }
  79
  80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  81 /// load from a stack slot, return the virtual or physical register number of
  82 /// the destination along with the FrameIndex of the loaded stack slot.  If
  83 /// not, return 0.  This predicate must return 0 if the instruction has
  84 /// any side effects other than loading from the stack slot.
  85 unsigned MipsInstrInfo::
  86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
  87 {
  88   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
  89       (MI->getOpcode() == Mips::LDC1)) {
  90     if ((MI->getOperand(2).isFI()) && // is a stack slot
  91         (MI->getOperand(1).isImm()) &&  // the imm is zero
  92         (isZeroImm(MI->getOperand(1)))) {
  93       FrameIndex = MI->getOperand(2).getIndex();
  94       return MI->getOperand(0).getReg();
  95     }
  96   }
  97
  98   return 0;
  99 }
 100
 101 /// isStoreToStackSlot - If the specified machine instruction is a direct
 102 /// store to a stack slot, return the virtual or physical register number of
 103 /// the source reg along with the FrameIndex of the loaded stack slot.  If
 104 /// not, return 0.  This predicate must return 0 if the instruction has
 105 /// any side effects other than storing to the stack slot.
 106 unsigned MipsInstrInfo::
 107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
 108 {
 109   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
 110       (MI->getOpcode() == Mips::SDC1)) {
 111     if ((MI->getOperand(2).isFI()) && // is a stack slot
 112         (MI->getOperand(1).isImm()) &&  // the imm is zero
 113         (isZeroImm(MI->getOperand(1)))) {
 114       FrameIndex = MI->getOperand(2).getIndex();
 115       return MI->getOperand(0).getReg();
 116     }
 117   }
 118   return 0;
 119 }
 120
 121 /// insertNoop - If data hazard condition is found insert the target nop
 122 /// instruction.
 123 void MipsInstrInfo::
 124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
 125 {
 126   DebugLoc DL = DebugLoc::getUnknownLoc();
 127   if (MI != MBB.end()) DL = MI->getDebugLoc();
 128   BuildMI(MBB, MI, DL, get(Mips::NOP));
 129 }
 130
 131 bool MipsInstrInfo::
 132 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 133              unsigned DestReg, unsigned SrcReg,
 134              const TargetRegisterClass *DestRC,
 135              const TargetRegisterClass *SrcRC) const {
 136   DebugLoc DL = DebugLoc::getUnknownLoc();
 137   if (I != MBB.end()) DL = I->getDebugLoc();
 138
 139   if (DestRC != SrcRC) {
 140
 141     // Copy to/from FCR31 condition register
 142     if ((DestRC == Mips::CPURegsRegisterClass) &&
 143         (SrcRC == Mips::CCRRegisterClass))
 144       BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
 145     else if ((DestRC == Mips::CCRRegisterClass) &&
 146         (SrcRC == Mips::CPURegsRegisterClass))
 147       BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
 148
 149     // Moves between coprocessors and cpu
 150     else if ((DestRC == Mips::CPURegsRegisterClass) &&
 151         (SrcRC == Mips::FGR32RegisterClass))
 152       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
 153     else if ((DestRC == Mips::FGR32RegisterClass) &&
 154              (SrcRC == Mips::CPURegsRegisterClass))
 155       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
 156
 157     // Move from/to Hi/Lo registers
 158     else if ((DestRC == Mips::HILORegisterClass) &&
 159              (SrcRC == Mips::CPURegsRegisterClass)) {
 160       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
 161       BuildMI(MBB, I, DL, get(Opc), DestReg);
 162     } else if ((SrcRC == Mips::HILORegisterClass) &&
 163                (DestRC == Mips::CPURegsRegisterClass)) {
 164       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
 165       BuildMI(MBB, I, DL, get(Opc), DestReg);
 166
 167     // Can't copy this register
 168     } else
 169       return false;
 170
 171     return true;
 172   }
 173
 174   if (DestRC == Mips::CPURegsRegisterClass)
 175     BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
 176       .addReg(SrcReg);
 177   else if (DestRC == Mips::FGR32RegisterClass)
 178     BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
 179   else if (DestRC == Mips::AFGR64RegisterClass)
 180     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
 181   else if (DestRC == Mips::CCRRegisterClass)
 182     BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
 183   else
 184     // Can't copy this register
 185     return false;
 186
 187   return true;
 188 }
 189
 190 void MipsInstrInfo::
 191 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 192                     unsigned SrcReg, bool isKill, int FI,
 193                     const TargetRegisterClass *RC) const {
 194   unsigned Opc;
 195
 196   DebugLoc DL = DebugLoc::getUnknownLoc();
 197   if (I != MBB.end()) DL = I->getDebugLoc();
 198
 199   if (RC == Mips::CPURegsRegisterClass)
 200     Opc = Mips::SW;
 201   else if (RC == Mips::FGR32RegisterClass)
 202     Opc = Mips::SWC1;
 203   else {
 204     assert(RC == Mips::AFGR64RegisterClass);
 205     Opc = Mips::SDC1;
 206   }
 207
 208   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
 209           .addImm(0).addFrameIndex(FI);
 210 }
 211
 212 void MipsInstrInfo::
 213 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 214                      unsigned DestReg, int FI,
 215                      const TargetRegisterClass *RC) const
 216 {
 217   unsigned Opc;
 218   if (RC == Mips::CPURegsRegisterClass)
 219     Opc = Mips::LW;
 220   else if (RC == Mips::FGR32RegisterClass)
 221     Opc = Mips::LWC1;
 222   else {
 223     assert(RC == Mips::AFGR64RegisterClass);
 224     Opc = Mips::LDC1;
 225   }
 226
 227   DebugLoc DL = DebugLoc::getUnknownLoc();
 228   if (I != MBB.end()) DL = I->getDebugLoc();
 229   BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
 230 }
 231
 232 MachineInstr *MipsInstrInfo::
 233 foldMemoryOperandImpl(MachineFunction &MF,
 234                       MachineInstr* MI,
 235                       const SmallVectorImpl<unsigned> &Ops, int FI) const
 236 {
 237   if (Ops.size() != 1) return NULL;
 238
 239   MachineInstr *NewMI = NULL;
 240
 241   switch (MI->getOpcode()) {
 242   case Mips::ADDu:
 243     if ((MI->getOperand(0).isReg()) &&
 244         (MI->getOperand(1).isReg()) &&
 245         (MI->getOperand(1).getReg() == Mips::ZERO) &&
 246         (MI->getOperand(2).isReg())) {
 247       if (Ops[0] == 0) {    // COPY -> STORE
 248         unsigned SrcReg = MI->getOperand(2).getReg();
 249         bool isKill = MI->getOperand(2).isKill();
 250         bool isUndef = MI->getOperand(2).isUndef();
 251         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
 252           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 253           .addImm(0).addFrameIndex(FI);
 254       } else {              // COPY -> LOAD
 255         unsigned DstReg = MI->getOperand(0).getReg();
 256         bool isDead = MI->getOperand(0).isDead();
 257         bool isUndef = MI->getOperand(0).isUndef();
 258         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
 259           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
 260                   getUndefRegState(isUndef))
 261           .addImm(0).addFrameIndex(FI);
 262       }
 263     }
 264     break;
 265   case Mips::FMOV_S32:
 266   case Mips::FMOV_D32:
 267     if ((MI->getOperand(0).isReg()) &&
 268         (MI->getOperand(1).isReg())) {
 269       const TargetRegisterClass
 270         *RC = RI.getRegClass(MI->getOperand(0).getReg());
 271       unsigned StoreOpc, LoadOpc;
 272
 273       if (RC == Mips::FGR32RegisterClass) {
 274         LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
 275       } else {
 276         assert(RC == Mips::AFGR64RegisterClass);
 277         LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
 278       }
 279
 280       if (Ops[0] == 0) {    // COPY -> STORE
 281         unsigned SrcReg = MI->getOperand(1).getReg();
 282         bool isKill = MI->getOperand(1).isKill();
 283         bool isUndef = MI->getOperand(2).isUndef();
 284         NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
 285           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 286           .addImm(0).addFrameIndex(FI) ;
 287       } else {              // COPY -> LOAD
 288         unsigned DstReg = MI->getOperand(0).getReg();
 289         bool isDead = MI->getOperand(0).isDead();
 290         bool isUndef = MI->getOperand(0).isUndef();
 291         NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
 292           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
 293                   getUndefRegState(isUndef))
 294           .addImm(0).addFrameIndex(FI);
 295       }
 296     }
 297     break;
 298   }
 299
 300   return NewMI;
 301 }
 302
 303 //===----------------------------------------------------------------------===//
 304 // Branch Analysis
 305 //===----------------------------------------------------------------------===//
 306
 307 /// GetCondFromBranchOpc - Return the Mips CC that matches
 308 /// the correspondent Branch instruction opcode.
 309 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
 310 {
 311   switch (BrOpc) {
 312   default: return Mips::COND_INVALID;
 313   case Mips::BEQ  : return Mips::COND_E;
 314   case Mips::BNE  : return Mips::COND_NE;
 315   case Mips::BGTZ : return Mips::COND_GZ;
 316   case Mips::BGEZ : return Mips::COND_GEZ;
 317   case Mips::BLTZ : return Mips::COND_LZ;
 318   case Mips::BLEZ : return Mips::COND_LEZ;
 319
 320   // We dont do fp branch analysis yet!
 321   case Mips::BC1T :
 322   case Mips::BC1F : return Mips::COND_INVALID;
 323   }
 324 }
 325
 326 /// GetCondBranchFromCond - Return the Branch instruction
 327 /// opcode that matches the cc.
 328 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
 329 {
 330   switch (CC) {
 331   default: llvm_unreachable("Illegal condition code!");
 332   case Mips::COND_E   : return Mips::BEQ;
 333   case Mips::COND_NE  : return Mips::BNE;
 334   case Mips::COND_GZ  : return Mips::BGTZ;
 335   case Mips::COND_GEZ : return Mips::BGEZ;
 336   case Mips::COND_LZ  : return Mips::BLTZ;
 337   case Mips::COND_LEZ : return Mips::BLEZ;
 338
 339   case Mips::FCOND_F:
 340   case Mips::FCOND_UN:
 341   case Mips::FCOND_EQ:
 342   case Mips::FCOND_UEQ:
 343   case Mips::FCOND_OLT:
 344   case Mips::FCOND_ULT:
 345   case Mips::FCOND_OLE:
 346   case Mips::FCOND_ULE:
 347   case Mips::FCOND_SF:
 348   case Mips::FCOND_NGLE:
 349   case Mips::FCOND_SEQ:
 350   case Mips::FCOND_NGL:
 351   case Mips::FCOND_LT:
 352   case Mips::FCOND_NGE:
 353   case Mips::FCOND_LE:
 354   case Mips::FCOND_NGT: return Mips::BC1T;
 355
 356   case Mips::FCOND_T:
 357   case Mips::FCOND_OR:
 358   case Mips::FCOND_NEQ:
 359   case Mips::FCOND_OGL:
 360   case Mips::FCOND_UGE:
 361   case Mips::FCOND_OGE:
 362   case Mips::FCOND_UGT:
 363   case Mips::FCOND_OGT:
 364   case Mips::FCOND_ST:
 365   case Mips::FCOND_GLE:
 366   case Mips::FCOND_SNE:
 367   case Mips::FCOND_GL:
 368   case Mips::FCOND_NLT:
 369   case Mips::FCOND_GE:
 370   case Mips::FCOND_NLE:
 371   case Mips::FCOND_GT: return Mips::BC1F;
 372   }
 373 }
 374
 375 /// GetOppositeBranchCondition - Return the inverse of the specified
 376 /// condition, e.g. turning COND_E to COND_NE.
 377 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
 378 {
 379   switch (CC) {
 380   default: llvm_unreachable("Illegal condition code!");
 381   case Mips::COND_E   : return Mips::COND_NE;
 382   case Mips::COND_NE  : return Mips::COND_E;
 383   case Mips::COND_GZ  : return Mips::COND_LEZ;
 384   case Mips::COND_GEZ : return Mips::COND_LZ;
 385   case Mips::COND_LZ  : return Mips::COND_GEZ;
 386   case Mips::COND_LEZ : return Mips::COND_GZ;
 387   case Mips::FCOND_F  : return Mips::FCOND_T;
 388   case Mips::FCOND_UN : return Mips::FCOND_OR;
 389   case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
 390   case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
 391   case Mips::FCOND_OLT: return Mips::FCOND_UGE;
 392   case Mips::FCOND_ULT: return Mips::FCOND_OGE;
 393   case Mips::FCOND_OLE: return Mips::FCOND_UGT;
 394   case Mips::FCOND_ULE: return Mips::FCOND_OGT;
 395   case Mips::FCOND_SF:  return Mips::FCOND_ST;
 396   case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
 397   case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
 398   case Mips::FCOND_NGL: return Mips::FCOND_GL;
 399   case Mips::FCOND_LT:  return Mips::FCOND_NLT;
 400   case Mips::FCOND_NGE: return Mips::FCOND_GE;
 401   case Mips::FCOND_LE:  return Mips::FCOND_NLE;
 402   case Mips::FCOND_NGT: return Mips::FCOND_GT;
 403   }
 404 }
 405
 406 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
 407                                   MachineBasicBlock *&TBB,
 408                                   MachineBasicBlock *&FBB,
 409                                   SmallVectorImpl<MachineOperand> &Cond,
 410                                   bool AllowModify) const
 411 {
 412   // If the block has no terminators, it just falls into the block after it.
 413   MachineBasicBlock::iterator I = MBB.end();
 414   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 415     return false;
 416
 417   // Get the last instruction in the block.
 418   MachineInstr *LastInst = I;
 419
 420   // If there is only one terminator instruction, process it.
 421   unsigned LastOpc = LastInst->getOpcode();
 422   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 423     if (!LastInst->getDesc().isBranch())
 424       return true;
 425
 426     // Unconditional branch
 427     if (LastOpc == Mips::J) {
 428       TBB = LastInst->getOperand(0).getMBB();
 429       return false;
 430     }
 431
 432     Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
 433     if (BranchCode == Mips::COND_INVALID)
 434       return true;  // Can't handle indirect branch.
 435
 436     // Conditional branch
 437     // Block ends with fall-through condbranch.
 438     if (LastOpc != Mips::COND_INVALID) {
 439       int LastNumOp = LastInst->getNumOperands();
 440
 441       TBB = LastInst->getOperand(LastNumOp-1).getMBB();
 442       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 443
 444       for (int i=0; i<LastNumOp-1; i++) {
 445         Cond.push_back(LastInst->getOperand(i));
 446       }
 447
 448       return false;
 449     }
 450   }
 451
 452   // Get the instruction before it if it is a terminator.
 453   MachineInstr *SecondLastInst = I;
 454
 455   // If there are three terminators, we don't know what sort of block this is.
 456   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
 457     return true;
 458
 459   // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
 460   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
 461   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
 462
 463   if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
 464     int SecondNumOp = SecondLastInst->getNumOperands();
 465
 466     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
 467     Cond.push_back(MachineOperand::CreateImm(BranchCode));
 468
 469     for (int i=0; i<SecondNumOp-1; i++) {
 470       Cond.push_back(SecondLastInst->getOperand(i));
 471     }
 472
 473     FBB = LastInst->getOperand(0).getMBB();
 474     return false;
 475   }
 476
 477   // If the block ends with two unconditional branches, handle it. The last
 478   // one is not executed, so remove it.
 479   if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
 480     TBB = SecondLastInst->getOperand(0).getMBB();
 481     I = LastInst;
 482     if (AllowModify)
 483       I->eraseFromParent();
 484     return false;
 485   }
 486
 487   // Otherwise, can't handle this.
 488   return true;
 489 }
 490
 491 unsigned MipsInstrInfo::
 492 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 493              MachineBasicBlock *FBB,
 494              const SmallVectorImpl<MachineOperand> &Cond) const {
 495   // FIXME this should probably have a DebugLoc argument
 496   DebugLoc dl = DebugLoc::getUnknownLoc();
 497   // Shouldn't be a fall through.
 498   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 499   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
 500          "Mips branch conditions can have two|three components!");
 501
 502   if (FBB == 0) { // One way branch.
 503     if (Cond.empty()) {
 504       // Unconditional branch?
 505       BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
 506     } else {
 507       // Conditional branch.
 508       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 509       const TargetInstrDesc &TID = get(Opc);
 510
 511       if (TID.getNumOperands() == 3)
 512         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
 513                           .addReg(Cond[2].getReg())
 514                           .addMBB(TBB);
 515       else
 516         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
 517                           .addMBB(TBB);
 518
 519     }
 520     return 1;
 521   }
 522
 523   // Two-way Conditional branch.
 524   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 525   const TargetInstrDesc &TID = get(Opc);
 526
 527   if (TID.getNumOperands() == 3)
 528     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
 529                       .addMBB(TBB);
 530   else
 531     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 532
 533   BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
 534   return 2;
 535 }
 536
 537 unsigned MipsInstrInfo::
 538 RemoveBranch(MachineBasicBlock &MBB) const
 539 {
 540   MachineBasicBlock::iterator I = MBB.end();
 541   if (I == MBB.begin()) return 0;
 542   --I;
 543   if (I->getOpcode() != Mips::J &&
 544       GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 545     return 0;
 546
 547   // Remove the branch.
 548   I->eraseFromParent();
 549
 550   I = MBB.end();
 551
 552   if (I == MBB.begin()) return 1;
 553   --I;
 554   if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 555     return 1;
 556
 557   // Remove the branch.
 558   I->eraseFromParent();
 559   return 2;
 560 }
 561
 562 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
 563 /// fall-through into its successor block.
 564 bool MipsInstrInfo::
 565 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
 566 {
 567   if (MBB.empty()) return false;
 568
 569   switch (MBB.back().getOpcode()) {
 570   case Mips::RET:     // Return.
 571   case Mips::JR:      // Indirect branch.
 572   case Mips::J:       // Uncond branch.
 573     return true;
 574   default: return false;
 575   }
 576 }
 577
 578 /// ReverseBranchCondition - Return the inverse opcode of the
 579 /// specified Branch instruction.
 580 bool MipsInstrInfo::
 581 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
 582 {
 583   assert( (Cond.size() == 3 || Cond.size() == 2) &&
 584           "Invalid Mips branch condition!");
 585   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
 586   return false;
 587 }
 588
 589 /// getGlobalBaseReg - Return a virtual register initialized with the
 590 /// the global base register value. Output instructions required to
 591 /// initialize the register in the function entry block, if necessary.
 592 ///
 593 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
 594   MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
 595   unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
 596   if (GlobalBaseReg != 0)
 597     return GlobalBaseReg;
 598
 599   // Insert the set of GlobalBaseReg into the first MBB of the function
 600   MachineBasicBlock &FirstMBB = MF->front();
 601   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 602   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 603   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 604
 605   GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
 606   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
 607                               Mips::CPURegsRegisterClass,
 608                               Mips::CPURegsRegisterClass);
 609   assert(Ok && "Couldn't assign to global base register!");
 610   Ok = Ok; // Silence warning when assertions are turned off.
 611   RegInfo.addLiveIn(Mips::GP);
 612
 613   MipsFI->setGlobalBaseReg(GlobalBaseReg);
 614   return GlobalBaseReg;
 615 }