lib/Target/PIC16/PIC16ISelLowering.h

   1 //===-- PIC16ISelLowering.h - PIC16 DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef PIC16ISELLOWERING_H
  16 #define PIC16ISELLOWERING_H
  17
  18 #include "PIC16.h"
  19 #include "PIC16Subtarget.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/Target/TargetLowering.h"
  22 #include <map>
  23
  24 namespace llvm {
  25   namespace PIC16ISD {
  26     enum NodeType {
  27       // Start the numbering from where ISD NodeType finishes.
  28       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  29
  30       Lo,            // Low 8-bits of GlobalAddress.
  31       Hi,            // High 8-bits of GlobalAddress.
  32       PIC16Load,
  33       PIC16LdArg,   // This is replica of PIC16Load but used to load function
  34                     // arguments and is being used for facilitating for some
  35                     // store removal optimizations.
  36
  37       PIC16LdWF,
  38       PIC16Store,
  39       PIC16StWF,
  40       Banksel,
  41       MTLO,          // Move to low part of FSR
  42       MTHI,          // Move to high part of FSR
  43       MTPCLATH,      // Move to PCLATCH
  44       PIC16Connect,  // General connector for PIC16 nodes
  45       BCF,
  46       LSLF,          // PIC16 Logical shift left
  47       LRLF,          // PIC16 Logical shift right
  48       RLF,           // Rotate left through carry
  49       RRF,           // Rotate right through carry
  50       CALL,          // PIC16 Call instruction
  51       CALLW,         // PIC16 CALLW instruction
  52       SUBCC,         // Compare for equality or inequality.
  53       SELECT_ICC,    // Psuedo to be caught in schedular and expanded to brcond.
  54       BRCOND,        // Conditional branch.
  55       RET,           // Return.
  56       Dummy
  57     };
  58
  59     // Keep track of different address spaces.
  60     enum AddressSpace {
  61       RAM_SPACE = 0,   // RAM address space
  62       ROM_SPACE = 1    // ROM address space number is 1
  63     };
  64     enum PIC16Libcall {
  65       MUL_I8 = RTLIB::UNKNOWN_LIBCALL + 1,
  66       SRA_I8,
  67       SLL_I8,
  68       SRL_I8,
  69       PIC16UnknownCall
  70     };
  71   }
  72
  73
  74   //===--------------------------------------------------------------------===//
  75   // TargetLowering Implementation
  76   //===--------------------------------------------------------------------===//
  77   class PIC16TargetLowering : public TargetLowering {
  78   public:
  79     explicit PIC16TargetLowering(PIC16TargetMachine &TM);
  80
  81     /// getTargetNodeName - This method returns the name of a target specific
  82     /// DAG node.
  83     virtual const char *getTargetNodeName(unsigned Opcode) const;
  84     /// getSetCCResultType - Return the ISD::SETCC ValueType
  85     virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const;
  86     SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
  87     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
  88     SDValue LowerADD(SDValue Op, SelectionDAG &DAG);
  89     SDValue LowerSUB(SDValue Op, SelectionDAG &DAG);
  90     SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG);
  91     // Call returns
  92     SDValue
  93     LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
  94                           const SmallVectorImpl<ISD::InputArg> &Ins,
  95                           DebugLoc dl, SelectionDAG &DAG,
  96                           SmallVectorImpl<SDValue> &InVals);
  97     SDValue
  98     LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
  99                              SDValue DataAddr_Lo, SDValue DataAddr_Hi,
 100                             const SmallVectorImpl<ISD::InputArg> &Ins,
 101                             DebugLoc dl, SelectionDAG &DAG,
 102                             SmallVectorImpl<SDValue> &InVals);
 103
 104     // Call arguments
 105     SDValue
 106     LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
 107                              const SmallVectorImpl<ISD::OutputArg> &Outs,
 108                              DebugLoc dl, SelectionDAG &DAG);
 109
 110     SDValue
 111     LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
 112                                SDValue DataAddr_Lo, SDValue DataAddr_Hi,
 113                                const SmallVectorImpl<ISD::OutputArg> &Outs,
 114                                const SmallVectorImpl<ISD::InputArg> &Ins,
 115                                DebugLoc dl, SelectionDAG &DAG);
 116
 117     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
 118     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
 119     SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
 120                         SelectionDAG &DAG, DebugLoc dl);
 121     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
 122                                                   MachineBasicBlock *MBB) const;
 123
 124
 125     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
 126     virtual void ReplaceNodeResults(SDNode *N,
 127                                     SmallVectorImpl<SDValue> &Results,
 128                                     SelectionDAG &DAG);
 129     virtual void LowerOperationWrapper(SDNode *N,
 130                                        SmallVectorImpl<SDValue> &Results,
 131                                        SelectionDAG &DAG);
 132
 133     virtual SDValue
 134     LowerFormalArguments(SDValue Chain,
 135                          unsigned CallConv,
 136                          bool isVarArg,
 137                          const SmallVectorImpl<ISD::InputArg> &Ins,
 138                          DebugLoc dl, SelectionDAG &DAG,
 139                          SmallVectorImpl<SDValue> &InVals);
 140
 141     virtual SDValue
 142       LowerCall(SDValue Chain, SDValue Callee,
 143                 unsigned CallConv, bool isVarArg, bool isTailCall,
 144                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 145                 const SmallVectorImpl<ISD::InputArg> &Ins,
 146                 DebugLoc dl, SelectionDAG &DAG,
 147                 SmallVectorImpl<SDValue> &InVals);
 148
 149     virtual SDValue
 150       LowerReturn(SDValue Chain,
 151                   unsigned CallConv, bool isVarArg,
 152                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 153                   DebugLoc dl, SelectionDAG &DAG);
 154
 155     SDValue ExpandStore(SDNode *N, SelectionDAG &DAG);
 156     SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG);
 157     SDValue ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG);
 158     SDValue ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG);
 159     SDValue ExpandFrameIndex(SDNode *N, SelectionDAG &DAG);
 160
 161     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 162     SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 163     SDValue PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 164
 165     // This function returns the Tmp Offset for FrameIndex. If any TmpOffset
 166     // already exists for the FI then it returns the same else it creates the
 167     // new offset and returns.
 168     unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size);
 169     void ResetTmpOffsetMap() { FiTmpOffsetMap.clear(); SetTmpSize(0); }
 170     void InitReservedFrameCount(const Function *F);
 171
 172     // Return the size of Tmp variable
 173     unsigned GetTmpSize() { return TmpSize; }
 174     void SetTmpSize(unsigned Size) { TmpSize = Size; }
 175
 176     /// getFunctionAlignment - Return the Log2 alignment of this function.
 177     virtual unsigned getFunctionAlignment(const Function *) const {
 178       // FIXME: The function never seems to be aligned.
 179       return 1;
 180     }
 181   private:
 182     // If the Node is a BUILD_PAIR representing a direct Address,
 183     // then this function will return true.
 184     bool isDirectAddress(const SDValue &Op);
 185
 186     // If the Node is a DirectAddress in ROM_SPACE then this
 187     // function will return true
 188     bool isRomAddress(const SDValue &Op);
 189
 190     // Extract the Lo and Hi component of Op.
 191     void GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo,
 192                           SDValue &Hi);
 193
 194
 195     // Load pointer can be a direct or indirect address. In PIC16 direct
 196     // addresses need Banksel and Indirect addresses need to be loaded to
 197     // FSR first. Handle address specific cases here.
 198     void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
 199                          SDValue &NewPtr, unsigned &Offset, DebugLoc dl);
 200
 201     // FrameIndex should be broken down into ExternalSymbol and FrameOffset.
 202     void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES,
 203                             int &Offset);
 204
 205     // For indirect calls data address of the callee frame need to be
 206     // extracted. This function fills the arguments DataAddr_Lo and
 207     // DataAddr_Hi with the address of the callee frame.
 208     void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
 209                         SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
 210                         SelectionDAG &DAG);
 211
 212     // We can not have both operands of a binary operation in W.
 213     // This function is used to put one operand on stack and generate a load.
 214     SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
 215
 216     // This function checks if we need to put an operand of an operation on
 217     // stack and generate a load or not.
 218     bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp);
 219
 220     /// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
 221     /// make the right decision when generating code for different targets.
 222     const PIC16Subtarget *Subtarget;
 223
 224
 225     // Extending the LIB Call framework of LLVM
 226     // to hold the names of PIC16Libcalls.
 227     const char *PIC16LibcallNames[PIC16ISD::PIC16UnknownCall];
 228
 229     // To set and retrieve the lib call names.
 230     void setPIC16LibcallName(PIC16ISD::PIC16Libcall Call, const char *Name);
 231     const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call);
 232
 233     // Make PIC16 Libcall.
 234     SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, EVT RetVT,
 235                              const SDValue *Ops, unsigned NumOps, bool isSigned,
 236                              SelectionDAG &DAG, DebugLoc dl);
 237
 238     // Check if operation has a direct load operand.
 239     inline bool isDirectLoad(const SDValue Op);
 240
 241   private:
 242     // The frameindexes generated for spill/reload are stack based.
 243     // This maps maintain zero based indexes for these FIs.
 244     std::map<unsigned, unsigned> FiTmpOffsetMap;
 245     unsigned TmpSize;
 246
 247     // These are the frames for return value and argument passing
 248     // These FrameIndices will be expanded to foo.frame external symbol
 249     // and all others will be expanded to foo.tmp external symbol.
 250     unsigned ReservedFrameCount;
 251   };
 252 } // namespace llvm
 253
 254 #endif // PIC16ISELLOWERING_H