lib/Target/PIC16/PIC16InstrInfo.cpp

   1 //===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PIC16.h"
  15 #include "PIC16InstrInfo.h"
  16 #include "PIC16TargetMachine.h"
  17 #include "PIC16GenInstrInfo.inc"
  18 #include "llvm/Function.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24 #include <cstdio>
  25
  26
  27 using namespace llvm;
  28
  29 // FIXME: Add the subtarget support on this constructor.
  30 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
  31   : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
  32     TM(tm),
  33     RegInfo(*this, *TM.getSubtargetImpl()) {}
  34
  35
  36 /// isStoreToStackSlot - If the specified machine instruction is a direct
  37 /// store to a stack slot, return the virtual or physical register number of
  38 /// the source reg along with the FrameIndex of the loaded stack slot.
  39 /// If not, return 0.  This predicate must return 0 if the instruction has
  40 /// any side effects other than storing to the stack slot.
  41 unsigned PIC16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  42                                             int &FrameIndex) const {
  43   if (MI->getOpcode() == PIC16::movwf
  44       && MI->getOperand(0).isReg()
  45       && MI->getOperand(1).isSymbol()) {
  46     FrameIndex = MI->getOperand(1).getIndex();
  47     return MI->getOperand(0).getReg();
  48   }
  49   return 0;
  50 }
  51
  52 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  53 /// load from a stack slot, return the virtual or physical register number of
  54 /// the dest reg along with the FrameIndex of the stack slot.
  55 /// If not, return 0.  This predicate must return 0 if the instruction has
  56 /// any side effects other than storing to the stack slot.
  57 unsigned PIC16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  58                                             int &FrameIndex) const {
  59   if (MI->getOpcode() == PIC16::movf
  60       && MI->getOperand(0).isReg()
  61       && MI->getOperand(1).isSymbol()) {
  62     FrameIndex = MI->getOperand(1).getIndex();
  63     return MI->getOperand(0).getReg();
  64   }
  65   return 0;
  66 }
  67
  68
  69 void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
  70                                          MachineBasicBlock::iterator I,
  71                                          unsigned SrcReg, bool isKill, int FI,
  72                                          const TargetRegisterClass *RC) const {
  73   PIC16TargetLowering *PTLI = TM.getTargetLowering();
  74   DebugLoc DL = DebugLoc::getUnknownLoc();
  75   if (I != MBB.end()) DL = I->getDebugLoc();
  76
  77   const Function *Func = MBB.getParent()->getFunction();
  78   const std::string FuncName = Func->getName();
  79
  80   const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
  81
  82   // On the order of operands here: think "movwf SrcReg, tmp_slot, offset".
  83   if (RC == PIC16::GPRRegisterClass) {
  84     //MachineFunction &MF = *MBB.getParent();
  85     //MachineRegisterInfo &RI = MF.getRegInfo();
  86     BuildMI(MBB, I, DL, get(PIC16::movwf))
  87       .addReg(SrcReg, getKillRegState(isKill))
  88       .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
  89       .addExternalSymbol(tmpName)
  90       .addImm(1); // Emit banksel for it.
  91   }
  92   else if (RC == PIC16::FSR16RegisterClass) {
  93     // This is a 16-bit register and the frameindex given by llvm is of
  94     // size two here. Break this index N into two zero based indexes and
  95     // put one into the map. The second one is always obtained by adding 1
  96     // to the first zero based index. In fact it is going to use 3 slots
  97     // as saving FSRs corrupts W also and hence we need to save/restore W also.
  98
  99     unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
 100                                                  : PIC16::save_fsr1;
 101     BuildMI(MBB, I, DL, get(opcode))
 102       .addReg(SrcReg, getKillRegState(isKill))
 103       .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
 104       .addExternalSymbol(tmpName)
 105       .addImm(1); // Emit banksel for it.
 106   }
 107   else
 108     llvm_unreachable("Can't store this register to stack slot");
 109 }
 110
 111 void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 112                                           MachineBasicBlock::iterator I,
 113                                           unsigned DestReg, int FI,
 114                                           const TargetRegisterClass *RC) const {
 115   PIC16TargetLowering *PTLI = TM.getTargetLowering();
 116   DebugLoc DL = DebugLoc::getUnknownLoc();
 117   if (I != MBB.end()) DL = I->getDebugLoc();
 118
 119   const Function *Func = MBB.getParent()->getFunction();
 120   const std::string FuncName = Func->getName();
 121
 122   const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
 123
 124   // On the order of operands here: think "movf FrameIndex, W".
 125   if (RC == PIC16::GPRRegisterClass) {
 126     //MachineFunction &MF = *MBB.getParent();
 127     //MachineRegisterInfo &RI = MF.getRegInfo();
 128     BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
 129       .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
 130       .addExternalSymbol(tmpName)
 131       .addImm(1); // Emit banksel for it.
 132   }
 133   else if (RC == PIC16::FSR16RegisterClass) {
 134     // This is a 16-bit register and the frameindex given by llvm is of
 135     // size two here. Break this index N into two zero based indexes and
 136     // put one into the map. The second one is always obtained by adding 1
 137     // to the first zero based index. In fact it is going to use 3 slots
 138     // as saving FSRs corrupts W also and hence we need to save/restore W also.
 139
 140     unsigned opcode = (DestReg == PIC16::FSR0) ? PIC16::restore_fsr0
 141                                                  : PIC16::restore_fsr1;
 142     BuildMI(MBB, I, DL, get(opcode), DestReg)
 143       .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
 144       .addExternalSymbol(tmpName)
 145       .addImm(1); // Emit banksel for it.
 146   }
 147   else
 148     llvm_unreachable("Can't load this register from stack slot");
 149 }
 150
 151 bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
 152                                    MachineBasicBlock::iterator I,
 153                                    unsigned DestReg, unsigned SrcReg,
 154                                    const TargetRegisterClass *DestRC,
 155                                    const TargetRegisterClass *SrcRC) const {
 156   DebugLoc DL = DebugLoc::getUnknownLoc();
 157   if (I != MBB.end()) DL = I->getDebugLoc();
 158
 159   if (DestRC == PIC16::FSR16RegisterClass) {
 160     BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
 161     return true;
 162   }
 163
 164   if (DestRC == PIC16::GPRRegisterClass) {
 165     BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg);
 166     return true;
 167   }
 168
 169   // Not yet supported.
 170   return false;
 171 }
 172
 173 bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
 174                                  unsigned &SrcReg, unsigned &DestReg,
 175                                  unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
 176   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
 177
 178   if (MI.getOpcode() == PIC16::copy_fsr
 179       || MI.getOpcode() == PIC16::copy_w) {
 180     DestReg = MI.getOperand(0).getReg();
 181     SrcReg = MI.getOperand(1).getReg();
 182     return true;
 183   }
 184
 185   return false;
 186 }
 187
 188 /// InsertBranch - Insert a branch into the end of the specified
 189 /// MachineBasicBlock.  This operands to this method are the same as those
 190 /// returned by AnalyzeBranch.  This is invoked in cases where AnalyzeBranch
 191 /// returns success and when an unconditional branch (TBB is non-null, FBB is
 192 /// null, Cond is empty) needs to be inserted. It returns the number of
 193 /// instructions inserted.
 194 unsigned PIC16InstrInfo::
 195 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 196              MachineBasicBlock *FBB,
 197              const SmallVectorImpl<MachineOperand> &Cond) const {
 198   // Shouldn't be a fall through.
 199   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 200
 201   if (FBB == 0) { // One way branch.
 202     if (Cond.empty()) {
 203       // Unconditional branch?
 204       DebugLoc dl = DebugLoc::getUnknownLoc();
 205       BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
 206     }
 207     return 1;
 208   }
 209
 210   // FIXME: If the there are some conditions specified then conditional branch
 211   // should be generated.
 212   // For the time being no instruction is being generated therefore
 213   // returning NULL.
 214   return 0;
 215 }