lib/Target/Sparc/SparcInstrInfo.cpp

   1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Sparc implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SparcInstrInfo.h"
  15 #include "SparcSubtarget.h"
  16 #include "Sparc.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "SparcGenInstrInfo.inc"
  22 using namespace llvm;
  23
  24 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
  25   : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
  26     RI(ST, *this), Subtarget(ST) {
  27 }
  28
  29 static bool isZeroImm(const MachineOperand &op) {
  30   return op.isImm() && op.getImm() == 0;
  31 }
  32
  33 /// Return true if the instruction is a register to register move and
  34 /// leave the source and dest operands in the passed parameters.
  35 ///
  36 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
  37                                  unsigned &SrcReg, unsigned &DstReg,
  38                                  unsigned &SrcSR, unsigned &DstSR) const {
  39   SrcSR = DstSR = 0; // No sub-registers.
  40
  41   // We look for 3 kinds of patterns here:
  42   // or with G0 or 0
  43   // add with G0 or 0
  44   // fmovs or FpMOVD (pseudo double move).
  45   if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
  46     if (MI.getOperand(1).getReg() == SP::G0) {
  47       DstReg = MI.getOperand(0).getReg();
  48       SrcReg = MI.getOperand(2).getReg();
  49       return true;
  50     } else if (MI.getOperand(2).getReg() == SP::G0) {
  51       DstReg = MI.getOperand(0).getReg();
  52       SrcReg = MI.getOperand(1).getReg();
  53       return true;
  54     }
  55   } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
  56              isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
  57     DstReg = MI.getOperand(0).getReg();
  58     SrcReg = MI.getOperand(1).getReg();
  59     return true;
  60   } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
  61              MI.getOpcode() == SP::FMOVD) {
  62     SrcReg = MI.getOperand(1).getReg();
  63     DstReg = MI.getOperand(0).getReg();
  64     return true;
  65   }
  66   return false;
  67 }
  68
  69 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  70 /// load from a stack slot, return the virtual or physical register number of
  71 /// the destination along with the FrameIndex of the loaded stack slot.  If
  72 /// not, return 0.  This predicate must return 0 if the instruction has
  73 /// any side effects other than loading from the stack slot.
  74 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  75                                              int &FrameIndex) const {
  76   if (MI->getOpcode() == SP::LDri ||
  77       MI->getOpcode() == SP::LDFri ||
  78       MI->getOpcode() == SP::LDDFri) {
  79     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
  80         MI->getOperand(2).getImm() == 0) {
  81       FrameIndex = MI->getOperand(1).getIndex();
  82       return MI->getOperand(0).getReg();
  83     }
  84   }
  85   return 0;
  86 }
  87
  88 /// isStoreToStackSlot - If the specified machine instruction is a direct
  89 /// store to a stack slot, return the virtual or physical register number of
  90 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  91 /// not, return 0.  This predicate must return 0 if the instruction has
  92 /// any side effects other than storing to the stack slot.
  93 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  94                                             int &FrameIndex) const {
  95   if (MI->getOpcode() == SP::STri ||
  96       MI->getOpcode() == SP::STFri ||
  97       MI->getOpcode() == SP::STDFri) {
  98     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
  99         MI->getOperand(1).getImm() == 0) {
 100       FrameIndex = MI->getOperand(0).getIndex();
 101       return MI->getOperand(2).getReg();
 102     }
 103   }
 104   return 0;
 105 }
 106
 107 unsigned
 108 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
 109                              MachineBasicBlock *FBB,
 110                              const SmallVectorImpl<MachineOperand> &Cond)const{
 111   // FIXME this should probably take a DebugLoc argument
 112   DebugLoc dl = DebugLoc::getUnknownLoc();
 113   // Can only insert uncond branches so far.
 114   assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
 115   BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
 116   return 1;
 117 }
 118
 119 bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 120                                   MachineBasicBlock::iterator I,
 121                                   unsigned DestReg, unsigned SrcReg,
 122                                   const TargetRegisterClass *DestRC,
 123                                   const TargetRegisterClass *SrcRC) const {
 124   if (DestRC != SrcRC) {
 125     // Not yet supported!
 126     return false;
 127   }
 128
 129   DebugLoc DL = DebugLoc::getUnknownLoc();
 130   if (I != MBB.end()) DL = I->getDebugLoc();
 131
 132   if (DestRC == SP::IntRegsRegisterClass)
 133     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
 134   else if (DestRC == SP::FPRegsRegisterClass)
 135     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
 136   else if (DestRC == SP::DFPRegsRegisterClass)
 137     BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
 138       .addReg(SrcReg);
 139   else
 140     // Can't copy this register
 141     return false;
 142
 143   return true;
 144 }
 145
 146 void SparcInstrInfo::
 147 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 148                     unsigned SrcReg, bool isKill, int FI,
 149                     const TargetRegisterClass *RC) const {
 150   DebugLoc DL = DebugLoc::getUnknownLoc();
 151   if (I != MBB.end()) DL = I->getDebugLoc();
 152
 153   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
 154   if (RC == SP::IntRegsRegisterClass)
 155     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
 156       .addReg(SrcReg, getKillRegState(isKill));
 157   else if (RC == SP::FPRegsRegisterClass)
 158     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
 159       .addReg(SrcReg,  getKillRegState(isKill));
 160   else if (RC == SP::DFPRegsRegisterClass)
 161     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
 162       .addReg(SrcReg,  getKillRegState(isKill));
 163   else
 164     llvm_unreachable("Can't store this register to stack slot");
 165 }
 166
 167 void SparcInstrInfo::
 168 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 169                      unsigned DestReg, int FI,
 170                      const TargetRegisterClass *RC) const {
 171   DebugLoc DL = DebugLoc::getUnknownLoc();
 172   if (I != MBB.end()) DL = I->getDebugLoc();
 173
 174   if (RC == SP::IntRegsRegisterClass)
 175     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
 176   else if (RC == SP::FPRegsRegisterClass)
 177     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
 178   else if (RC == SP::DFPRegsRegisterClass)
 179     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
 180   else
 181     llvm_unreachable("Can't load this register from stack slot");
 182 }
 183
 184 MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 185                                                     MachineInstr* MI,
 186                                           const SmallVectorImpl<unsigned> &Ops,
 187                                                     int FI) const {
 188   if (Ops.size() != 1) return NULL;
 189
 190   unsigned OpNum = Ops[0];
 191   bool isFloat = false;
 192   MachineInstr *NewMI = NULL;
 193   switch (MI->getOpcode()) {
 194   case SP::ORrr:
 195     if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
 196         MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
 197       if (OpNum == 0)    // COPY -> STORE
 198         NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
 199           .addFrameIndex(FI)
 200           .addImm(0)
 201           .addReg(MI->getOperand(2).getReg());
 202       else               // COPY -> LOAD
 203         NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
 204                         MI->getOperand(0).getReg())
 205           .addFrameIndex(FI)
 206           .addImm(0);
 207     }
 208     break;
 209   case SP::FMOVS:
 210     isFloat = true;
 211     // FALLTHROUGH
 212   case SP::FMOVD:
 213     if (OpNum == 0) { // COPY -> STORE
 214       unsigned SrcReg = MI->getOperand(1).getReg();
 215       bool isKill = MI->getOperand(1).isKill();
 216       bool isUndef = MI->getOperand(1).isUndef();
 217       NewMI = BuildMI(MF, MI->getDebugLoc(),
 218                       get(isFloat ? SP::STFri : SP::STDFri))
 219         .addFrameIndex(FI)
 220         .addImm(0)
 221         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
 222     } else {             // COPY -> LOAD
 223       unsigned DstReg = MI->getOperand(0).getReg();
 224       bool isDead = MI->getOperand(0).isDead();
 225       bool isUndef = MI->getOperand(0).isUndef();
 226       NewMI = BuildMI(MF, MI->getDebugLoc(),
 227                       get(isFloat ? SP::LDFri : SP::LDDFri))
 228         .addReg(DstReg, RegState::Define |
 229                 getDeadRegState(isDead) | getUndefRegState(isUndef))
 230         .addFrameIndex(FI)
 231         .addImm(0);
 232     }
 233     break;
 234   }
 235
 236   return NewMI;
 237 }