lib/Target/Sparc/SparcInstrInfo.h

   1 //===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Sparc implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SPARCINSTRUCTIONINFO_H
  15 #define SPARCINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "SparcRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 /// SPII - This namespace holds all of the target specific flags that
  23 /// instruction info tracks.
  24 ///
  25 namespace SPII {
  26   enum {
  27     Pseudo = (1<<0),
  28     Load = (1<<1),
  29     Store = (1<<2),
  30     DelaySlot = (1<<3)
  31   };
  32 }
  33
  34 class SparcInstrInfo : public TargetInstrInfoImpl {
  35   const SparcRegisterInfo RI;
  36   const SparcSubtarget& Subtarget;
  37 public:
  38   explicit SparcInstrInfo(SparcSubtarget &ST);
  39
  40   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  41   /// such, whenever a client has an instance of instruction info, it should
  42   /// always be able to get register info as well (through this method).
  43   ///
  44   virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
  45
  46   /// Return true if the instruction is a register to register move and return
  47   /// the source and dest operands and their sub-register indices by reference.
  48   virtual bool isMoveInstr(const MachineInstr &MI,
  49                            unsigned &SrcReg, unsigned &DstReg,
  50                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  51
  52   /// isLoadFromStackSlot - If the specified machine instruction is a direct
  53   /// load from a stack slot, return the virtual or physical register number of
  54   /// the destination along with the FrameIndex of the loaded stack slot.  If
  55   /// not, return 0.  This predicate must return 0 if the instruction has
  56   /// any side effects other than loading from the stack slot.
  57   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  58                                        int &FrameIndex) const;
  59
  60   /// isStoreToStackSlot - If the specified machine instruction is a direct
  61   /// store to a stack slot, return the virtual or physical register number of
  62   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  63   /// not, return 0.  This predicate must return 0 if the instruction has
  64   /// any side effects other than storing to the stack slot.
  65   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  66                                       int &FrameIndex) const;
  67
  68
  69   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  70                                 MachineBasicBlock *FBB,
  71                             const SmallVectorImpl<MachineOperand> &Cond) const;
  72
  73   virtual bool copyRegToReg(MachineBasicBlock &MBB,
  74                             MachineBasicBlock::iterator I,
  75                             unsigned DestReg, unsigned SrcReg,
  76                             const TargetRegisterClass *DestRC,
  77                             const TargetRegisterClass *SrcRC) const;
  78
  79   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  80                                    MachineBasicBlock::iterator MBBI,
  81                                    unsigned SrcReg, bool isKill, int FrameIndex,
  82                                    const TargetRegisterClass *RC) const;
  83
  84   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  85                                     MachineBasicBlock::iterator MBBI,
  86                                     unsigned DestReg, int FrameIndex,
  87                                     const TargetRegisterClass *RC) const;
  88
  89   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  90                                               MachineInstr* MI,
  91                                            const SmallVectorImpl<unsigned> &Ops,
  92                                               int FrameIndex) const;
  93
  94   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  95                                               MachineInstr* MI,
  96                                            const SmallVectorImpl<unsigned> &Ops,
  97                                               MachineInstr* LoadMI) const {
  98     return 0;
  99   }
 100 };
 101
 102 }
 103
 104 #endif