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Change allowsUnalignedMemoryAccesses to take type argument since some targets
[llvm/avr.git] / lib / Target / SystemZ / SystemZISelLowering.cpp
blob279e22b653310f6d4e3500b86472cf95fda0d4f0
1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "systemz-lower"
15
16 #include "SystemZISelLowering.h"
17 #include "SystemZ.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/ADT/VectorExtras.h"
38 using namespace llvm;
39
40 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
41 TargetLowering(tm, new TargetLoweringObjectFileELF()),
42 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
43
44 RegInfo = TM.getRegisterInfo();
45
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
48 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
49 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
50 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
51
52 if (!UseSoftFloat) {
53 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
54 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
55
56 addLegalFPImmediate(APFloat(+0.0)); // lzer
57 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
58 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
59 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
60 }
61
62 // Compute derived properties from the register classes
63 computeRegisterProperties();
64
65 // Set shifts properties
66 setShiftAmountType(MVT::i64);
67
68 // Provide all sorts of operation actions
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
72
73 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
76
77 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
80
81 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
82 setSchedulingPreference(SchedulingForLatency);
83 setBooleanContents(ZeroOrOneBooleanContent);
84
85 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
86 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
87 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
88 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
89 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
94 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
96
97 setOperationAction(ISD::SDIV, MVT::i32, Expand);
98 setOperationAction(ISD::UDIV, MVT::i32, Expand);
99 setOperationAction(ISD::SDIV, MVT::i64, Expand);
100 setOperationAction(ISD::UDIV, MVT::i64, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
102 setOperationAction(ISD::UREM, MVT::i32, Expand);
103 setOperationAction(ISD::SREM, MVT::i64, Expand);
104 setOperationAction(ISD::UREM, MVT::i64, Expand);
105
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
107
108 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
110 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
112 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
113 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
114
115 // FIXME: Can we lower these 2 efficiently?
116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
120 setOperationAction(ISD::SELECT, MVT::i32, Expand);
121 setOperationAction(ISD::SELECT, MVT::i64, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
128
129 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
130 // unsigned.
131 setOperationAction(ISD::MULHS, MVT::i64, Expand);
132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
133
134 // Lower some FP stuff
135 setOperationAction(ISD::FSIN, MVT::f32, Expand);
136 setOperationAction(ISD::FSIN, MVT::f64, Expand);
137 setOperationAction(ISD::FCOS, MVT::f32, Expand);
138 setOperationAction(ISD::FCOS, MVT::f64, Expand);
139 setOperationAction(ISD::FREM, MVT::f32, Expand);
140 setOperationAction(ISD::FREM, MVT::f64, Expand);
141
142 // We have only 64-bit bitconverts
143 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
144 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
145
146 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
147 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
148 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
149 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
150
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 }
153
154 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
155 switch (Op.getOpcode()) {
156 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
157 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
158 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
159 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
160 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
161 default:
162 llvm_unreachable("Should not custom lower this!");
163 return SDValue();
164 }
165 }
166
167 //===----------------------------------------------------------------------===//
168 // Calling Convention Implementation
169 //===----------------------------------------------------------------------===//
170
171 #include "SystemZGenCallingConv.inc"
172
173 SDValue
174 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
175 unsigned CallConv,
176 bool isVarArg,
177 const SmallVectorImpl<ISD::InputArg>
178 &Ins,
179 DebugLoc dl,
180 SelectionDAG &DAG,
181 SmallVectorImpl<SDValue> &InVals) {
182
183 switch (CallConv) {
184 default:
185 llvm_unreachable("Unsupported calling convention");
186 case CallingConv::C:
187 case CallingConv::Fast:
188 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
189 }
190 }
191
192 SDValue
193 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
194 unsigned CallConv, bool isVarArg,
195 bool isTailCall,
196 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 const SmallVectorImpl<ISD::InputArg> &Ins,
198 DebugLoc dl, SelectionDAG &DAG,
199 SmallVectorImpl<SDValue> &InVals) {
200
201 switch (CallConv) {
202 default:
203 llvm_unreachable("Unsupported calling convention");
204 case CallingConv::Fast:
205 case CallingConv::C:
206 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
207 Outs, Ins, dl, DAG, InVals);
208 }
209 }
210
211 /// LowerCCCArguments - transform physical registers into virtual registers and
212 /// generate load operations for arguments places on the stack.
213 // FIXME: struct return stuff
214 // FIXME: varargs
215 SDValue
216 SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
217 unsigned CallConv,
218 bool isVarArg,
219 const SmallVectorImpl<ISD::InputArg>
220 &Ins,
221 DebugLoc dl,
222 SelectionDAG &DAG,
223 SmallVectorImpl<SDValue> &InVals) {
224
225 MachineFunction &MF = DAG.getMachineFunction();
226 MachineFrameInfo *MFI = MF.getFrameInfo();
227 MachineRegisterInfo &RegInfo = MF.getRegInfo();
228
229 // Assign locations to all of the incoming arguments.
230 SmallVector<CCValAssign, 16> ArgLocs;
231 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
232 ArgLocs, *DAG.getContext());
233 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
234
235 if (isVarArg)
236 llvm_report_error("Varargs not supported yet");
237
238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
239 SDValue ArgValue;
240 CCValAssign &VA = ArgLocs[i];
241 EVT LocVT = VA.getLocVT();
242 if (VA.isRegLoc()) {
243 // Arguments passed in registers
244 TargetRegisterClass *RC;
245 switch (LocVT.getSimpleVT().SimpleTy) {
246 default:
247 #ifndef NDEBUG
248 cerr << "LowerFormalArguments Unhandled argument type: "
249 << LocVT.getSimpleVT().SimpleTy
250 << "\n";
251 #endif
252 llvm_unreachable(0);
253 case MVT::i64:
254 RC = SystemZ::GR64RegisterClass;
255 break;
256 case MVT::f32:
257 RC = SystemZ::FP32RegisterClass;
258 break;
259 case MVT::f64:
260 RC = SystemZ::FP64RegisterClass;
261 break;
262 }
263
264 unsigned VReg = RegInfo.createVirtualRegister(RC);
265 RegInfo.addLiveIn(VA.getLocReg(), VReg);
266 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
267 } else {
268 // Sanity check
269 assert(VA.isMemLoc());
270
271 // Create the nodes corresponding to a load from this parameter slot.
272 // Create the frame index object for this incoming parameter...
273 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
274 VA.getLocMemOffset());
275
276 // Create the SelectionDAG nodes corresponding to a load
277 // from this parameter
278 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
279 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
280 PseudoSourceValue::getFixedStack(FI), 0);
281 }
282
283 // If this is an 8/16/32-bit value, it is really passed promoted to 64
284 // bits. Insert an assert[sz]ext to capture this, then truncate to the
285 // right size.
286 if (VA.getLocInfo() == CCValAssign::SExt)
287 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
288 DAG.getValueType(VA.getValVT()));
289 else if (VA.getLocInfo() == CCValAssign::ZExt)
290 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
291 DAG.getValueType(VA.getValVT()));
292
293 if (VA.getLocInfo() != CCValAssign::Full)
294 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
295
296 InVals.push_back(ArgValue);
297 }
298
299 return Chain;
300 }
301
302 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
303 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
304 /// TODO: sret.
305 SDValue
306 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
307 unsigned CallConv, bool isVarArg,
308 bool isTailCall,
309 const SmallVectorImpl<ISD::OutputArg>
310 &Outs,
311 const SmallVectorImpl<ISD::InputArg> &Ins,
312 DebugLoc dl, SelectionDAG &DAG,
313 SmallVectorImpl<SDValue> &InVals) {
314
315 MachineFunction &MF = DAG.getMachineFunction();
316
317 // Offset to first argument stack slot.
318 const unsigned FirstArgOffset = 160;
319
320 // Analyze operands of the call, assigning locations to each operand.
321 SmallVector<CCValAssign, 16> ArgLocs;
322 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
323 ArgLocs, *DAG.getContext());
324
325 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
326
327 // Get a count of how many bytes are to be pushed on the stack.
328 unsigned NumBytes = CCInfo.getNextStackOffset();
329
330 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
331 getPointerTy(), true));
332
333 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
334 SmallVector<SDValue, 12> MemOpChains;
335 SDValue StackPtr;
336
337 // Walk the register/memloc assignments, inserting copies/loads.
338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
339 CCValAssign &VA = ArgLocs[i];
340
341 SDValue Arg = Outs[i].Val;
342
343 // Promote the value if needed.
344 switch (VA.getLocInfo()) {
345 default: assert(0 && "Unknown loc info!");
346 case CCValAssign::Full: break;
347 case CCValAssign::SExt:
348 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
349 break;
350 case CCValAssign::ZExt:
351 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
352 break;
353 case CCValAssign::AExt:
354 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
355 break;
356 }
357
358 // Arguments that can be passed on register must be kept at RegsToPass
359 // vector
360 if (VA.isRegLoc()) {
361 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
362 } else {
363 assert(VA.isMemLoc());
364
365 if (StackPtr.getNode() == 0)
366 StackPtr =
367 DAG.getCopyFromReg(Chain, dl,
368 (RegInfo->hasFP(MF) ?
369 SystemZ::R11D : SystemZ::R15D),
370 getPointerTy());
371
372 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
373 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
374 StackPtr,
375 DAG.getIntPtrConstant(Offset));
376
377 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
378 PseudoSourceValue::getStack(), Offset));
379 }
380 }
381
382 // Transform all store nodes into one single node because all store nodes are
383 // independent of each other.
384 if (!MemOpChains.empty())
385 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
386 &MemOpChains[0], MemOpChains.size());
387
388 // Build a sequence of copy-to-reg nodes chained together with token chain and
389 // flag operands which copy the outgoing args into registers. The InFlag in
390 // necessary since all emited instructions must be stuck together.
391 SDValue InFlag;
392 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
393 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
394 RegsToPass[i].second, InFlag);
395 InFlag = Chain.getValue(1);
396 }
397
398 // If the callee is a GlobalAddress node (quite common, every direct call is)
399 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
400 // Likewise ExternalSymbol -> TargetExternalSymbol.
401 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
402 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
403 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
404 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
405
406 // Returns a chain & a flag for retval copy to use.
407 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
408 SmallVector<SDValue, 8> Ops;
409 Ops.push_back(Chain);
410 Ops.push_back(Callee);
411
412 // Add argument registers to the end of the list so that they are
413 // known live into the call.
414 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
415 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
416 RegsToPass[i].second.getValueType()));
417
418 if (InFlag.getNode())
419 Ops.push_back(InFlag);
420
421 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
422 InFlag = Chain.getValue(1);
423
424 // Create the CALLSEQ_END node.
425 Chain = DAG.getCALLSEQ_END(Chain,
426 DAG.getConstant(NumBytes, getPointerTy(), true),
427 DAG.getConstant(0, getPointerTy(), true),
428 InFlag);
429 InFlag = Chain.getValue(1);
430
431 // Handle result values, copying them out of physregs into vregs that we
432 // return.
433 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
434 DAG, InVals);
435 }
436
437 /// LowerCallResult - Lower the result values of a call into the
438 /// appropriate copies out of appropriate physical registers.
439 ///
440 SDValue
441 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
442 unsigned CallConv, bool isVarArg,
443 const SmallVectorImpl<ISD::InputArg>
444 &Ins,
445 DebugLoc dl, SelectionDAG &DAG,
446 SmallVectorImpl<SDValue> &InVals) {
447
448 // Assign locations to each value returned by this call.
449 SmallVector<CCValAssign, 16> RVLocs;
450 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
451 *DAG.getContext());
452
453 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
454
455 // Copy all of the result registers out of their specified physreg.
456 for (unsigned i = 0; i != RVLocs.size(); ++i) {
457 CCValAssign &VA = RVLocs[i];
458
459 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
460 VA.getLocVT(), InFlag).getValue(1);
461 SDValue RetValue = Chain.getValue(0);
462 InFlag = Chain.getValue(2);
463
464 // If this is an 8/16/32-bit value, it is really passed promoted to 64
465 // bits. Insert an assert[sz]ext to capture this, then truncate to the
466 // right size.
467 if (VA.getLocInfo() == CCValAssign::SExt)
468 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
469 DAG.getValueType(VA.getValVT()));
470 else if (VA.getLocInfo() == CCValAssign::ZExt)
471 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
472 DAG.getValueType(VA.getValVT()));
473
474 if (VA.getLocInfo() != CCValAssign::Full)
475 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
476
477 InVals.push_back(RetValue);
478 }
479
480 return Chain;
481 }
482
483
484 SDValue
485 SystemZTargetLowering::LowerReturn(SDValue Chain,
486 unsigned CallConv, bool isVarArg,
487 const SmallVectorImpl<ISD::OutputArg> &Outs,
488 DebugLoc dl, SelectionDAG &DAG) {
489
490 // CCValAssign - represent the assignment of the return value to a location
491 SmallVector<CCValAssign, 16> RVLocs;
492
493 // CCState - Info about the registers and stack slot.
494 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
495 RVLocs, *DAG.getContext());
496
497 // Analize return values.
498 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
499
500 // If this is the first return lowered for this function, add the regs to the
501 // liveout set for the function.
502 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
503 for (unsigned i = 0; i != RVLocs.size(); ++i)
504 if (RVLocs[i].isRegLoc())
505 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
506 }
507
508 SDValue Flag;
509
510 // Copy the result values into the output registers.
511 for (unsigned i = 0; i != RVLocs.size(); ++i) {
512 CCValAssign &VA = RVLocs[i];
513 SDValue ResValue = Outs[i].Val;
514 assert(VA.isRegLoc() && "Can only return in registers!");
515
516 // If this is an 8/16/32-bit value, it is really should be passed promoted
517 // to 64 bits.
518 if (VA.getLocInfo() == CCValAssign::SExt)
519 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
520 else if (VA.getLocInfo() == CCValAssign::ZExt)
521 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
522 else if (VA.getLocInfo() == CCValAssign::AExt)
523 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
524
525 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
526
527 // Guarantee that all emitted copies are stuck together,
528 // avoiding something bad.
529 Flag = Chain.getValue(1);
530 }
531
532 if (Flag.getNode())
533 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
534
535 // Return Void
536 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
537 }
538
539 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
540 ISD::CondCode CC, SDValue &SystemZCC,
541 SelectionDAG &DAG) {
542 // FIXME: Emit a test if RHS is zero
543
544 bool isUnsigned = false;
545 SystemZCC::CondCodes TCC;
546 switch (CC) {
547 default:
548 llvm_unreachable("Invalid integer condition!");
549 case ISD::SETEQ:
550 case ISD::SETOEQ:
551 TCC = SystemZCC::E;
552 break;
553 case ISD::SETUEQ:
554 TCC = SystemZCC::NLH;
555 break;
556 case ISD::SETNE:
557 case ISD::SETONE:
558 TCC = SystemZCC::NE;
559 break;
560 case ISD::SETUNE:
561 TCC = SystemZCC::LH;
562 break;
563 case ISD::SETO:
564 TCC = SystemZCC::O;
565 break;
566 case ISD::SETUO:
567 TCC = SystemZCC::NO;
568 break;
569 case ISD::SETULE:
570 if (LHS.getValueType().isFloatingPoint()) {
571 TCC = SystemZCC::NH;
572 break;
573 }
574 isUnsigned = true; // FALLTHROUGH
575 case ISD::SETLE:
576 case ISD::SETOLE:
577 TCC = SystemZCC::LE;
578 break;
579 case ISD::SETUGE:
580 if (LHS.getValueType().isFloatingPoint()) {
581 TCC = SystemZCC::NL;
582 break;
583 }
584 isUnsigned = true; // FALLTHROUGH
585 case ISD::SETGE:
586 case ISD::SETOGE:
587 TCC = SystemZCC::HE;
588 break;
589 case ISD::SETUGT:
590 if (LHS.getValueType().isFloatingPoint()) {
591 TCC = SystemZCC::NLE;
592 break;
593 }
594 isUnsigned = true; // FALLTHROUGH
595 case ISD::SETGT:
596 case ISD::SETOGT:
597 TCC = SystemZCC::H;
598 break;
599 case ISD::SETULT:
600 if (LHS.getValueType().isFloatingPoint()) {
601 TCC = SystemZCC::NHE;
602 break;
603 }
604 isUnsigned = true; // FALLTHROUGH
605 case ISD::SETLT:
606 case ISD::SETOLT:
607 TCC = SystemZCC::L;
608 break;
609 }
610
611 SystemZCC = DAG.getConstant(TCC, MVT::i32);
612
613 DebugLoc dl = LHS.getDebugLoc();
614 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
615 dl, MVT::Flag, LHS, RHS);
616 }
617
618
619 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
620 SDValue Chain = Op.getOperand(0);
621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
622 SDValue LHS = Op.getOperand(2);
623 SDValue RHS = Op.getOperand(3);
624 SDValue Dest = Op.getOperand(4);
625 DebugLoc dl = Op.getDebugLoc();
626
627 SDValue SystemZCC;
628 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
629 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
630 Chain, Dest, SystemZCC, Flag);
631 }
632
633 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
634 SDValue LHS = Op.getOperand(0);
635 SDValue RHS = Op.getOperand(1);
636 SDValue TrueV = Op.getOperand(2);
637 SDValue FalseV = Op.getOperand(3);
638 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
639 DebugLoc dl = Op.getDebugLoc();
640
641 SDValue SystemZCC;
642 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
643
644 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
645 SmallVector<SDValue, 4> Ops;
646 Ops.push_back(TrueV);
647 Ops.push_back(FalseV);
648 Ops.push_back(SystemZCC);
649 Ops.push_back(Flag);
650
651 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
652 }
653
654 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
655 SelectionDAG &DAG) {
656 DebugLoc dl = Op.getDebugLoc();
657 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
658 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
659
660 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
661 bool ExtraLoadRequired =
662 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
663
664 SDValue Result;
665 if (!IsPic && !ExtraLoadRequired) {
666 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
667 Offset = 0;
668 } else {
669 unsigned char OpFlags = 0;
670 if (ExtraLoadRequired)
671 OpFlags = SystemZII::MO_GOTENT;
672
673 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
674 }
675
676 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
677 getPointerTy(), Result);
678
679 if (ExtraLoadRequired)
680 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
681 PseudoSourceValue::getGOT(), 0);
682
683 // If there was a non-zero offset that we didn't fold, create an explicit
684 // addition for it.
685 if (Offset != 0)
686 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
687 DAG.getConstant(Offset, getPointerTy()));
688
689 return Result;
690 }
691
692 // FIXME: PIC here
693 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
694 SelectionDAG &DAG) {
695 DebugLoc dl = Op.getDebugLoc();
696 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
697 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
698
699 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
700 }
701
702
703 // FIXME: PIC here
704 // FIXME: This is just dirty hack. We need to lower cpool properly
705 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
706 SelectionDAG &DAG) {
707 DebugLoc dl = Op.getDebugLoc();
708 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
709
710 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
711 CP->getAlignment(),
712 CP->getOffset());
713
714 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
715 }
716
717 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
718 switch (Opcode) {
719 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
720 case SystemZISD::CALL: return "SystemZISD::CALL";
721 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
722 case SystemZISD::CMP: return "SystemZISD::CMP";
723 case SystemZISD::UCMP: return "SystemZISD::UCMP";
724 case SystemZISD::SELECT: return "SystemZISD::SELECT";
725 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
726 default: return NULL;
727 }
728 }
729
730 //===----------------------------------------------------------------------===//
731 // Other Lowering Code
732 //===----------------------------------------------------------------------===//
733
734 MachineBasicBlock*
735 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
736 MachineBasicBlock *BB) const {
737 const SystemZInstrInfo &TII = *TM.getInstrInfo();
738 DebugLoc dl = MI->getDebugLoc();
739 assert((MI->getOpcode() == SystemZ::Select32 ||
740 MI->getOpcode() == SystemZ::SelectF32 ||
741 MI->getOpcode() == SystemZ::Select64 ||
742 MI->getOpcode() == SystemZ::SelectF64) &&
743 "Unexpected instr type to insert");
744
745 // To "insert" a SELECT instruction, we actually have to insert the diamond
746 // control-flow pattern. The incoming instruction knows the destination vreg
747 // to set, the condition code register to branch on, the true/false values to
748 // select between, and a branch opcode to use.
749 const BasicBlock *LLVM_BB = BB->getBasicBlock();
750 MachineFunction::iterator I = BB;
751 ++I;
752
753 // thisMBB:
754 // ...
755 // TrueVal = ...
756 // cmpTY ccX, r1, r2
757 // jCC copy1MBB
758 // fallthrough --> copy0MBB
759 MachineBasicBlock *thisMBB = BB;
760 MachineFunction *F = BB->getParent();
761 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
762 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
763 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
764 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
765 F->insert(I, copy0MBB);
766 F->insert(I, copy1MBB);
767 // Update machine-CFG edges by transferring all successors of the current
768 // block to the new block which will contain the Phi node for the select.
769 copy1MBB->transferSuccessors(BB);
770 // Next, add the true and fallthrough blocks as its successors.
771 BB->addSuccessor(copy0MBB);
772 BB->addSuccessor(copy1MBB);
773
774 // copy0MBB:
775 // %FalseValue = ...
776 // # fallthrough to copy1MBB
777 BB = copy0MBB;
778
779 // Update machine-CFG edges
780 BB->addSuccessor(copy1MBB);
781
782 // copy1MBB:
783 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
784 // ...
785 BB = copy1MBB;
786 BuildMI(BB, dl, TII.get(SystemZ::PHI),
787 MI->getOperand(0).getReg())
788 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
789 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
790
791 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
792 return BB;
793 }
AVR Backend for LLVM