lib/Target/X86/X86CodeEmitter.cpp

   1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the X86 machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "x86-emitter"
  16 #include "X86InstrInfo.h"
  17 #include "X86JITInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "X86TargetMachine.h"
  20 #include "X86Relocations.h"
  21 #include "X86.h"
  22 #include "llvm/PassManager.h"
  23 #include "llvm/CodeGen/MachineCodeEmitter.h"
  24 #include "llvm/CodeGen/JITCodeEmitter.h"
  25 #include "llvm/CodeGen/ObjectCodeEmitter.h"
  26 #include "llvm/CodeGen/MachineFunctionPass.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineModuleInfo.h"
  29 #include "llvm/CodeGen/Passes.h"
  30 #include "llvm/Function.h"
  31 #include "llvm/ADT/Statistic.h"
  32 #include "llvm/Support/Compiler.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/raw_ostream.h"
  36 #include "llvm/Target/TargetOptions.h"
  37 using namespace llvm;
  38
  39 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  40
  41 namespace {
  42 template<class CodeEmitter>
  43   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
  44     const X86InstrInfo  *II;
  45     const TargetData    *TD;
  46     X86TargetMachine    &TM;
  47     CodeEmitter         &MCE;
  48     intptr_t PICBaseOffset;
  49     bool Is64BitMode;
  50     bool IsPIC;
  51   public:
  52     static char ID;
  53     explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
  54       : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
  55       MCE(mce), PICBaseOffset(0), Is64BitMode(false),
  56       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  57     Emitter(X86TargetMachine &tm, CodeEmitter &mce,
  58             const X86InstrInfo &ii, const TargetData &td, bool is64)
  59       : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
  60       MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
  61       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  62
  63     bool runOnMachineFunction(MachineFunction &MF);
  64
  65     virtual const char *getPassName() const {
  66       return "X86 Machine Code Emitter";
  67     }
  68
  69     void emitInstruction(const MachineInstr &MI,
  70                          const TargetInstrDesc *Desc);
  71
  72     void getAnalysisUsage(AnalysisUsage &AU) const {
  73       AU.setPreservesAll();
  74       AU.addRequired<MachineModuleInfo>();
  75       MachineFunctionPass::getAnalysisUsage(AU);
  76     }
  77
  78   private:
  79     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
  80     void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
  81                            intptr_t Disp = 0, intptr_t PCAdj = 0,
  82                            bool NeedStub = false, bool Indirect = false);
  83     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
  84     void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
  85                               intptr_t PCAdj = 0);
  86     void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
  87                               intptr_t PCAdj = 0);
  88
  89     void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
  90                                intptr_t Adj = 0, bool IsPCRel = true);
  91
  92     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
  93     void emitRegModRMByte(unsigned RegOpcodeField);
  94     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
  95     void emitConstant(uint64_t Val, unsigned Size);
  96
  97     void emitMemModRMByte(const MachineInstr &MI,
  98                           unsigned Op, unsigned RegOpcodeField,
  99                           intptr_t PCAdj = 0);
 100
 101     unsigned getX86RegNum(unsigned RegNo) const;
 102   };
 103
 104 template<class CodeEmitter>
 105   char Emitter<CodeEmitter>::ID = 0;
 106 }
 107
 108 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 109 /// to the specified templated MachineCodeEmitter object.
 110
 111 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
 112                                              MachineCodeEmitter &MCE) {
 113   return new Emitter<MachineCodeEmitter>(TM, MCE);
 114 }
 115 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
 116                                                 JITCodeEmitter &JCE) {
 117   return new Emitter<JITCodeEmitter>(TM, JCE);
 118 }
 119 FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
 120                                                    ObjectCodeEmitter &OCE) {
 121   return new Emitter<ObjectCodeEmitter>(TM, OCE);
 122 }
 123
 124 template<class CodeEmitter>
 125 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
 126
 127   MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
 128
 129   II = TM.getInstrInfo();
 130   TD = TM.getTargetData();
 131   Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
 132   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
 133
 134   do {
 135     DEBUG(errs() << "JITTing function '"
 136           << MF.getFunction()->getName() << "'\n");
 137     MCE.startFunction(MF);
 138     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 139          MBB != E; ++MBB) {
 140       MCE.StartMachineBasicBlock(MBB);
 141       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 142            I != E; ++I) {
 143         const TargetInstrDesc &Desc = I->getDesc();
 144         emitInstruction(*I, &Desc);
 145         // MOVPC32r is basically a call plus a pop instruction.
 146         if (Desc.getOpcode() == X86::MOVPC32r)
 147           emitInstruction(*I, &II->get(X86::POP32r));
 148         NumEmitted++;  // Keep track of the # of mi's emitted
 149       }
 150     }
 151   } while (MCE.finishFunction(MF));
 152
 153   return false;
 154 }
 155
 156 /// emitPCRelativeBlockAddress - This method keeps track of the information
 157 /// necessary to resolve the address of this block later and emits a dummy
 158 /// value.
 159 ///
 160 template<class CodeEmitter>
 161 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
 162   // Remember where this reference was and where it is to so we can
 163   // deal with it later.
 164   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 165                                              X86::reloc_pcrel_word, MBB));
 166   MCE.emitWordLE(0);
 167 }
 168
 169 /// emitGlobalAddress - Emit the specified address to the code stream assuming
 170 /// this is part of a "take the address of a global" instruction.
 171 ///
 172 template<class CodeEmitter>
 173 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 174                                 intptr_t Disp /* = 0 */,
 175                                 intptr_t PCAdj /* = 0 */,
 176                                 bool NeedStub /* = false */,
 177                                 bool Indirect /* = false */) {
 178   intptr_t RelocCST = Disp;
 179   if (Reloc == X86::reloc_picrel_word)
 180     RelocCST = PICBaseOffset;
 181   else if (Reloc == X86::reloc_pcrel_word)
 182     RelocCST = PCAdj;
 183   MachineRelocation MR = Indirect
 184     ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
 185                                            GV, RelocCST, NeedStub)
 186     : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
 187                                GV, RelocCST, NeedStub);
 188   MCE.addRelocation(MR);
 189   // The relocated value will be added to the displacement
 190   if (Reloc == X86::reloc_absolute_dword)
 191     MCE.emitDWordLE(Disp);
 192   else
 193     MCE.emitWordLE((int32_t)Disp);
 194 }
 195
 196 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 197 /// be emitted to the current location in the function, and allow it to be PC
 198 /// relative.
 199 template<class CodeEmitter>
 200 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
 201                                                      unsigned Reloc) {
 202   intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
 203   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 204                                                  Reloc, ES, RelocCST));
 205   if (Reloc == X86::reloc_absolute_dword)
 206     MCE.emitDWordLE(0);
 207   else
 208     MCE.emitWordLE(0);
 209 }
 210
 211 /// emitConstPoolAddress - Arrange for the address of an constant pool
 212 /// to be emitted to the current location in the function, and allow it to be PC
 213 /// relative.
 214 template<class CodeEmitter>
 215 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
 216                                    intptr_t Disp /* = 0 */,
 217                                    intptr_t PCAdj /* = 0 */) {
 218   intptr_t RelocCST = 0;
 219   if (Reloc == X86::reloc_picrel_word)
 220     RelocCST = PICBaseOffset;
 221   else if (Reloc == X86::reloc_pcrel_word)
 222     RelocCST = PCAdj;
 223   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 224                                                     Reloc, CPI, RelocCST));
 225   // The relocated value will be added to the displacement
 226   if (Reloc == X86::reloc_absolute_dword)
 227     MCE.emitDWordLE(Disp);
 228   else
 229     MCE.emitWordLE((int32_t)Disp);
 230 }
 231
 232 /// emitJumpTableAddress - Arrange for the address of a jump table to
 233 /// be emitted to the current location in the function, and allow it to be PC
 234 /// relative.
 235 template<class CodeEmitter>
 236 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
 237                                    intptr_t PCAdj /* = 0 */) {
 238   intptr_t RelocCST = 0;
 239   if (Reloc == X86::reloc_picrel_word)
 240     RelocCST = PICBaseOffset;
 241   else if (Reloc == X86::reloc_pcrel_word)
 242     RelocCST = PCAdj;
 243   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 244                                                     Reloc, JTI, RelocCST));
 245   // The relocated value will be added to the displacement
 246   if (Reloc == X86::reloc_absolute_dword)
 247     MCE.emitDWordLE(0);
 248   else
 249     MCE.emitWordLE(0);
 250 }
 251
 252 template<class CodeEmitter>
 253 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
 254   return II->getRegisterInfo().getX86RegNum(RegNo);
 255 }
 256
 257 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
 258                                       unsigned RM) {
 259   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
 260   return RM | (RegOpcode << 3) | (Mod << 6);
 261 }
 262
 263 template<class CodeEmitter>
 264 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
 265                                             unsigned RegOpcodeFld){
 266   MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
 267 }
 268
 269 template<class CodeEmitter>
 270 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
 271   MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
 272 }
 273
 274 template<class CodeEmitter>
 275 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
 276                                        unsigned Index,
 277                                        unsigned Base) {
 278   // SIB byte is in the same format as the ModRMByte...
 279   MCE.emitByte(ModRMByte(SS, Index, Base));
 280 }
 281
 282 template<class CodeEmitter>
 283 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
 284   // Output the constant in little endian byte order...
 285   for (unsigned i = 0; i != Size; ++i) {
 286     MCE.emitByte(Val & 255);
 287     Val >>= 8;
 288   }
 289 }
 290
 291 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
 292 /// sign-extended field.
 293 static bool isDisp8(int Value) {
 294   return Value == (signed char)Value;
 295 }
 296
 297 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
 298                               const TargetMachine &TM) {
 299   // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
 300   // mechanism as 32-bit mode.
 301   if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
 302       !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
 303     return false;
 304
 305   // Return true if this is a reference to a stub containing the address of the
 306   // global, not the global itself.
 307   return isGlobalStubReference(GVOp.getTargetFlags());
 308 }
 309
 310 template<class CodeEmitter>
 311 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
 312                                                  int DispVal,
 313                                                  intptr_t Adj /* = 0 */,
 314                                                  bool IsPCRel /* = true */) {
 315   // If this is a simple integer displacement that doesn't require a relocation,
 316   // emit it now.
 317   if (!RelocOp) {
 318     emitConstant(DispVal, 4);
 319     return;
 320   }
 321
 322   // Otherwise, this is something that requires a relocation.  Emit it as such
 323   // now.
 324   if (RelocOp->isGlobal()) {
 325     // In 64-bit static small code model, we could potentially emit absolute.
 326     // But it's probably not beneficial. If the MCE supports using RIP directly
 327     // do it, otherwise fallback to absolute (this is determined by IsPCRel).
 328     //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
 329     //  89 04 25 00 00 00 00  mov    %eax,0x0      # Absolute
 330     unsigned rt = Is64BitMode ?
 331       (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
 332       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 333     bool NeedStub = isa<Function>(RelocOp->getGlobal());
 334     bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
 335     emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
 336                       Adj, NeedStub, Indirect);
 337   } else if (RelocOp->isCPI()) {
 338     unsigned rt = Is64BitMode ?
 339       (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
 340       : (IsPCRel ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 341     emitConstPoolAddress(RelocOp->getIndex(), rt,
 342                          RelocOp->getOffset(), Adj);
 343   } else if (RelocOp->isJTI()) {
 344     unsigned rt = Is64BitMode ?
 345       (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
 346       : (IsPCRel ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 347     emitJumpTableAddress(RelocOp->getIndex(), rt, Adj);
 348   } else {
 349     llvm_unreachable("Unknown value to relocate!");
 350   }
 351 }
 352
 353 template<class CodeEmitter>
 354 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
 355                                unsigned Op, unsigned RegOpcodeField,
 356                                intptr_t PCAdj) {
 357   const MachineOperand &Op3 = MI.getOperand(Op+3);
 358   int DispVal = 0;
 359   const MachineOperand *DispForReloc = 0;
 360
 361   // Figure out what sort of displacement we have to handle here.
 362   if (Op3.isGlobal()) {
 363     DispForReloc = &Op3;
 364   } else if (Op3.isCPI()) {
 365     if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
 366       DispForReloc = &Op3;
 367     } else {
 368       DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
 369       DispVal += Op3.getOffset();
 370     }
 371   } else if (Op3.isJTI()) {
 372     if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
 373       DispForReloc = &Op3;
 374     } else {
 375       DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
 376     }
 377   } else {
 378     DispVal = Op3.getImm();
 379   }
 380
 381   const MachineOperand &Base     = MI.getOperand(Op);
 382   const MachineOperand &Scale    = MI.getOperand(Op+1);
 383   const MachineOperand &IndexReg = MI.getOperand(Op+2);
 384
 385   unsigned BaseReg = Base.getReg();
 386
 387   // Indicate that the displacement will use an pcrel or absolute reference
 388   // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
 389   // while others, unless explicit asked to use RIP, use absolute references.
 390   bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
 391
 392   // Is a SIB byte needed?
 393   // If no BaseReg, issue a RIP relative instruction only if the MCE can
 394   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
 395   // 2-7) and absolute references.
 396   if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
 397       IndexReg.getReg() == 0 &&
 398       ((BaseReg == 0 && MCE.earlyResolveAddresses()) || BaseReg == X86::RIP ||
 399        (BaseReg != 0 && getX86RegNum(BaseReg) != N86::ESP))) {
 400     if (BaseReg == 0 || BaseReg == X86::RIP) {  // Just a displacement?
 401       // Emit special case [disp32] encoding
 402       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
 403       emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
 404     } else {
 405       unsigned BaseRegNo = getX86RegNum(BaseReg);
 406       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
 407         // Emit simple indirect register encoding... [EAX] f.e.
 408         MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
 409       } else if (!DispForReloc && isDisp8(DispVal)) {
 410         // Emit the disp8 encoding... [REG+disp8]
 411         MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
 412         emitConstant(DispVal, 1);
 413       } else {
 414         // Emit the most general non-SIB encoding: [REG+disp32]
 415         MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
 416         emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
 417       }
 418     }
 419
 420   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
 421     assert(IndexReg.getReg() != X86::ESP &&
 422            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
 423
 424     bool ForceDisp32 = false;
 425     bool ForceDisp8  = false;
 426     if (BaseReg == 0) {
 427       // If there is no base register, we emit the special case SIB byte with
 428       // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
 429       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 430       ForceDisp32 = true;
 431     } else if (DispForReloc) {
 432       // Emit the normal disp32 encoding.
 433       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 434       ForceDisp32 = true;
 435     } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
 436       // Emit no displacement ModR/M byte
 437       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 438     } else if (isDisp8(DispVal)) {
 439       // Emit the disp8 encoding...
 440       MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
 441       ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
 442     } else {
 443       // Emit the normal disp32 encoding...
 444       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 445     }
 446
 447     // Calculate what the SS field value should be...
 448     static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
 449     unsigned SS = SSTable[Scale.getImm()];
 450
 451     if (BaseReg == 0) {
 452       // Handle the SIB byte for the case where there is no base, see Intel
 453       // Manual 2A, table 2-7. The displacement has already been output.
 454       unsigned IndexRegNo;
 455       if (IndexReg.getReg())
 456         IndexRegNo = getX86RegNum(IndexReg.getReg());
 457       else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
 458         IndexRegNo = 4;
 459       emitSIBByte(SS, IndexRegNo, 5);
 460     } else {
 461       unsigned BaseRegNo = getX86RegNum(BaseReg);
 462       unsigned IndexRegNo;
 463       if (IndexReg.getReg())
 464         IndexRegNo = getX86RegNum(IndexReg.getReg());
 465       else
 466         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 467       emitSIBByte(SS, IndexRegNo, BaseRegNo);
 468     }
 469
 470     // Do we need to output a displacement?
 471     if (ForceDisp8) {
 472       emitConstant(DispVal, 1);
 473     } else if (DispVal != 0 || ForceDisp32) {
 474       emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
 475     }
 476   }
 477 }
 478
 479 template<class CodeEmitter>
 480 void Emitter<CodeEmitter>::emitInstruction(
 481                               const MachineInstr &MI,
 482                               const TargetInstrDesc *Desc) {
 483   DEBUG(errs() << MI);
 484
 485   MCE.processDebugLoc(MI.getDebugLoc());
 486
 487   unsigned Opcode = Desc->Opcode;
 488
 489   // Emit the lock opcode prefix as needed.
 490   if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
 491
 492   // Emit segment override opcode prefix as needed.
 493   switch (Desc->TSFlags & X86II::SegOvrMask) {
 494   case X86II::FS:
 495     MCE.emitByte(0x64);
 496     break;
 497   case X86II::GS:
 498     MCE.emitByte(0x65);
 499     break;
 500   default: llvm_unreachable("Invalid segment!");
 501   case 0: break;  // No segment override!
 502   }
 503
 504   // Emit the repeat opcode prefix as needed.
 505   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
 506
 507   // Emit the operand size opcode prefix as needed.
 508   if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
 509
 510   // Emit the address size opcode prefix as needed.
 511   if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
 512
 513   bool Need0FPrefix = false;
 514   switch (Desc->TSFlags & X86II::Op0Mask) {
 515   case X86II::TB:  // Two-byte opcode prefix
 516   case X86II::T8:  // 0F 38
 517   case X86II::TA:  // 0F 3A
 518     Need0FPrefix = true;
 519     break;
 520   case X86II::TF: // F2 0F 38
 521     MCE.emitByte(0xF2);
 522     Need0FPrefix = true;
 523     break;
 524   case X86II::REP: break; // already handled.
 525   case X86II::XS:   // F3 0F
 526     MCE.emitByte(0xF3);
 527     Need0FPrefix = true;
 528     break;
 529   case X86II::XD:   // F2 0F
 530     MCE.emitByte(0xF2);
 531     Need0FPrefix = true;
 532     break;
 533   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
 534   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
 535     MCE.emitByte(0xD8+
 536                  (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
 537                                    >> X86II::Op0Shift));
 538     break; // Two-byte opcode prefix
 539   default: llvm_unreachable("Invalid prefix!");
 540   case 0: break;  // No prefix!
 541   }
 542
 543   if (Is64BitMode) {
 544     // REX prefix
 545     unsigned REX = X86InstrInfo::determineREX(MI);
 546     if (REX)
 547       MCE.emitByte(0x40 | REX);
 548   }
 549
 550   // 0x0F escape code must be emitted just before the opcode.
 551   if (Need0FPrefix)
 552     MCE.emitByte(0x0F);
 553
 554   switch (Desc->TSFlags & X86II::Op0Mask) {
 555   case X86II::TF:  // F2 0F 38
 556   case X86II::T8:  // 0F 38
 557     MCE.emitByte(0x38);
 558     break;
 559   case X86II::TA:    // 0F 3A
 560     MCE.emitByte(0x3A);
 561     break;
 562   }
 563
 564   // If this is a two-address instruction, skip one of the register operands.
 565   unsigned NumOps = Desc->getNumOperands();
 566   unsigned CurOp = 0;
 567   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
 568     ++CurOp;
 569   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
 570     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
 571     --NumOps;
 572
 573   unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
 574   switch (Desc->TSFlags & X86II::FormMask) {
 575   default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
 576   case X86II::Pseudo:
 577     // Remember the current PC offset, this is the PIC relocation
 578     // base address.
 579     switch (Opcode) {
 580     default:
 581       llvm_unreachable("psuedo instructions should be removed before code emission");
 582       break;
 583     case TargetInstrInfo::INLINEASM: {
 584       // We allow inline assembler nodes with empty bodies - they can
 585       // implicitly define registers, which is ok for JIT.
 586       if (MI.getOperand(0).getSymbolName()[0]) {
 587         llvm_report_error("JIT does not support inline asm!");
 588       }
 589       break;
 590     }
 591     case TargetInstrInfo::DBG_LABEL:
 592     case TargetInstrInfo::EH_LABEL:
 593       MCE.emitLabel(MI.getOperand(0).getImm());
 594       break;
 595     case TargetInstrInfo::IMPLICIT_DEF:
 596     case TargetInstrInfo::DECLARE:
 597     case X86::DWARF_LOC:
 598     case X86::FP_REG_KILL:
 599       break;
 600     case X86::MOVPC32r: {
 601       // This emits the "call" portion of this pseudo instruction.
 602       MCE.emitByte(BaseOpcode);
 603       emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
 604       // Remember PIC base.
 605       PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
 606       X86JITInfo *JTI = TM.getJITInfo();
 607       JTI->setPICBase(MCE.getCurrentPCValue());
 608       break;
 609     }
 610     }
 611     CurOp = NumOps;
 612     break;
 613   case X86II::RawFrm:
 614     MCE.emitByte(BaseOpcode);
 615
 616     if (CurOp != NumOps) {
 617       const MachineOperand &MO = MI.getOperand(CurOp++);
 618
 619       DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n");
 620       DEBUG(errs() << "isMBB " << MO.isMBB() << "\n");
 621       DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n");
 622       DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n");
 623       DEBUG(errs() << "isImm " << MO.isImm() << "\n");
 624
 625       if (MO.isMBB()) {
 626         emitPCRelativeBlockAddress(MO.getMBB());
 627       } else if (MO.isGlobal()) {
 628         // Assume undefined functions may be outside the Small codespace.
 629         bool NeedStub =
 630           (Is64BitMode &&
 631               (TM.getCodeModel() == CodeModel::Large ||
 632                TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
 633           Opcode == X86::TAILJMPd;
 634         emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
 635                           MO.getOffset(), 0, NeedStub);
 636       } else if (MO.isSymbol()) {
 637         emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
 638       } else if (MO.isImm()) {
 639         if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
 640           // Fix up immediate operand for pc relative calls.
 641           intptr_t Imm = (intptr_t)MO.getImm();
 642           Imm = Imm - MCE.getCurrentPCValue() - 4;
 643           emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
 644         } else
 645           emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
 646       } else {
 647         llvm_unreachable("Unknown RawFrm operand!");
 648       }
 649     }
 650     break;
 651
 652   case X86II::AddRegFrm:
 653     MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
 654
 655     if (CurOp != NumOps) {
 656       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 657       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 658       if (MO1.isImm())
 659         emitConstant(MO1.getImm(), Size);
 660       else {
 661         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 662           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 663         if (Opcode == X86::MOV64ri64i32)
 664           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 665         // This should not occur on Darwin for relocatable objects.
 666         if (Opcode == X86::MOV64ri)
 667           rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
 668         if (MO1.isGlobal()) {
 669           bool NeedStub = isa<Function>(MO1.getGlobal());
 670           bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
 671           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 672                             NeedStub, Indirect);
 673         } else if (MO1.isSymbol())
 674           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 675         else if (MO1.isCPI())
 676           emitConstPoolAddress(MO1.getIndex(), rt);
 677         else if (MO1.isJTI())
 678           emitJumpTableAddress(MO1.getIndex(), rt);
 679       }
 680     }
 681     break;
 682
 683   case X86II::MRMDestReg: {
 684     MCE.emitByte(BaseOpcode);
 685     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 686                      getX86RegNum(MI.getOperand(CurOp+1).getReg()));
 687     CurOp += 2;
 688     if (CurOp != NumOps)
 689       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 690     break;
 691   }
 692   case X86II::MRMDestMem: {
 693     MCE.emitByte(BaseOpcode);
 694     emitMemModRMByte(MI, CurOp,
 695                      getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
 696                                   .getReg()));
 697     CurOp +=  X86AddrNumOperands + 1;
 698     if (CurOp != NumOps)
 699       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 700     break;
 701   }
 702
 703   case X86II::MRMSrcReg:
 704     MCE.emitByte(BaseOpcode);
 705     emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
 706                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 707     CurOp += 2;
 708     if (CurOp != NumOps)
 709       emitConstant(MI.getOperand(CurOp++).getImm(),
 710                    X86InstrInfo::sizeOfImm(Desc));
 711     break;
 712
 713   case X86II::MRMSrcMem: {
 714     // FIXME: Maybe lea should have its own form?
 715     int AddrOperands;
 716     if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
 717         Opcode == X86::LEA16r || Opcode == X86::LEA32r)
 718       AddrOperands = X86AddrNumOperands - 1; // No segment register
 719     else
 720       AddrOperands = X86AddrNumOperands;
 721
 722     intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
 723       X86InstrInfo::sizeOfImm(Desc) : 0;
 724
 725     MCE.emitByte(BaseOpcode);
 726     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
 727                      PCAdj);
 728     CurOp += AddrOperands + 1;
 729     if (CurOp != NumOps)
 730       emitConstant(MI.getOperand(CurOp++).getImm(),
 731                    X86InstrInfo::sizeOfImm(Desc));
 732     break;
 733   }
 734
 735   case X86II::MRM0r: case X86II::MRM1r:
 736   case X86II::MRM2r: case X86II::MRM3r:
 737   case X86II::MRM4r: case X86II::MRM5r:
 738   case X86II::MRM6r: case X86II::MRM7r: {
 739     MCE.emitByte(BaseOpcode);
 740
 741     // Special handling of lfence, mfence, monitor, and mwait.
 742     if (Desc->getOpcode() == X86::LFENCE ||
 743         Desc->getOpcode() == X86::MFENCE ||
 744         Desc->getOpcode() == X86::MONITOR ||
 745         Desc->getOpcode() == X86::MWAIT) {
 746       emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 747
 748       switch (Desc->getOpcode()) {
 749       default: break;
 750       case X86::MONITOR:
 751         MCE.emitByte(0xC8);
 752         break;
 753       case X86::MWAIT:
 754         MCE.emitByte(0xC9);
 755         break;
 756       }
 757     } else {
 758       emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
 759                        (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 760     }
 761
 762     if (CurOp != NumOps) {
 763       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 764       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 765       if (MO1.isImm())
 766         emitConstant(MO1.getImm(), Size);
 767       else {
 768         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 769           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 770         if (Opcode == X86::MOV64ri32)
 771           rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
 772         if (MO1.isGlobal()) {
 773           bool NeedStub = isa<Function>(MO1.getGlobal());
 774           bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
 775           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 776                             NeedStub, Indirect);
 777         } else if (MO1.isSymbol())
 778           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 779         else if (MO1.isCPI())
 780           emitConstPoolAddress(MO1.getIndex(), rt);
 781         else if (MO1.isJTI())
 782           emitJumpTableAddress(MO1.getIndex(), rt);
 783       }
 784     }
 785     break;
 786   }
 787
 788   case X86II::MRM0m: case X86II::MRM1m:
 789   case X86II::MRM2m: case X86II::MRM3m:
 790   case X86II::MRM4m: case X86II::MRM5m:
 791   case X86II::MRM6m: case X86II::MRM7m: {
 792     intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
 793       (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
 794           X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
 795
 796     MCE.emitByte(BaseOpcode);
 797     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
 798                      PCAdj);
 799     CurOp += X86AddrNumOperands;
 800
 801     if (CurOp != NumOps) {
 802       const MachineOperand &MO = MI.getOperand(CurOp++);
 803       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 804       if (MO.isImm())
 805         emitConstant(MO.getImm(), Size);
 806       else {
 807         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 808           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 809         if (Opcode == X86::MOV64mi32)
 810           rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
 811         if (MO.isGlobal()) {
 812           bool NeedStub = isa<Function>(MO.getGlobal());
 813           bool Indirect = gvNeedsNonLazyPtr(MO, TM);
 814           emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
 815                             NeedStub, Indirect);
 816         } else if (MO.isSymbol())
 817           emitExternalSymbolAddress(MO.getSymbolName(), rt);
 818         else if (MO.isCPI())
 819           emitConstPoolAddress(MO.getIndex(), rt);
 820         else if (MO.isJTI())
 821           emitJumpTableAddress(MO.getIndex(), rt);
 822       }
 823     }
 824     break;
 825   }
 826
 827   case X86II::MRMInitReg:
 828     MCE.emitByte(BaseOpcode);
 829     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
 830     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 831                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 832     ++CurOp;
 833     break;
 834   }
 835
 836   if (!Desc->isVariadic() && CurOp != NumOps) {
 837 #ifndef NDEBUG
 838     errs() << "Cannot encode: " << MI << "\n";
 839 #endif
 840     llvm_unreachable(0);
 841   }
 842 }