lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the X86 specific subclass of TargetSubtarget.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "subtarget"
  15 #include "X86Subtarget.h"
  16 #include "X86InstrInfo.h"
  17 #include "X86GenSubtarget.inc"
  18 #include "llvm/GlobalValue.h"
  19 #include "llvm/Support/Debug.h"
  20 #include "llvm/Support/raw_ostream.h"
  21 #include "llvm/Target/TargetMachine.h"
  22 #include "llvm/Target/TargetOptions.h"
  23 using namespace llvm;
  24
  25 #if defined(_MSC_VER)
  26 #include <intrin.h>
  27 #endif
  28
  29 /// ClassifyGlobalReference - Classify a global variable reference for the
  30 /// current subtarget according to how we should reference it in a non-pcrel
  31 /// context.
  32 unsigned char X86Subtarget::
  33 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
  34   // DLLImport only exists on windows, it is implemented as a load from a
  35   // DLLIMPORT stub.
  36   if (GV->hasDLLImportLinkage())
  37     return X86II::MO_DLLIMPORT;
  38
  39   // GV with ghost linkage (in JIT lazy compilation mode) do not require an
  40   // extra load from stub.
  41   bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
  42
  43   // X86-64 in PIC mode.
  44   if (isPICStyleRIPRel()) {
  45     // Large model never uses stubs.
  46     if (TM.getCodeModel() == CodeModel::Large)
  47       return X86II::MO_NO_FLAG;
  48
  49     if (isTargetDarwin()) {
  50       // If symbol visibility is hidden, the extra load is not needed if
  51       // target is x86-64 or the symbol is definitely defined in the current
  52       // translation unit.
  53       if (GV->hasDefaultVisibility() &&
  54           (isDecl || GV->isWeakForLinker()))
  55         return X86II::MO_GOTPCREL;
  56     } else {
  57       assert(isTargetELF() && "Unknown rip-relative target");
  58
  59       // Extra load is needed for all externally visible.
  60       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
  61         return X86II::MO_GOTPCREL;
  62     }
  63
  64     return X86II::MO_NO_FLAG;
  65   }
  66
  67   if (isPICStyleGOT()) {   // 32-bit ELF targets.
  68     // Extra load is needed for all externally visible.
  69     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
  70       return X86II::MO_GOTOFF;
  71     return X86II::MO_GOT;
  72   }
  73
  74   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
  75     // Determine whether we have a stub reference and/or whether the reference
  76     // is relative to the PIC base or not.
  77
  78     // If this is a strong reference to a definition, it is definitely not
  79     // through a stub.
  80     if (!isDecl && !GV->isWeakForLinker())
  81       return X86II::MO_PIC_BASE_OFFSET;
  82
  83     // Unless we have a symbol with hidden visibility, we have to go through a
  84     // normal $non_lazy_ptr stub because this symbol might be resolved late.
  85     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
  86       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
  87
  88     // If symbol visibility is hidden, we have a stub for common symbol
  89     // references and external declarations.
  90     if (isDecl || GV->hasCommonLinkage()) {
  91       // Hidden $non_lazy_ptr reference.
  92       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
  93     }
  94
  95     // Otherwise, no stub.
  96     return X86II::MO_PIC_BASE_OFFSET;
  97   }
  98
  99   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
 100     // Determine whether we have a stub reference.
 101
 102     // If this is a strong reference to a definition, it is definitely not
 103     // through a stub.
 104     if (!isDecl && !GV->isWeakForLinker())
 105       return X86II::MO_NO_FLAG;
 106
 107     // Unless we have a symbol with hidden visibility, we have to go through a
 108     // normal $non_lazy_ptr stub because this symbol might be resolved late.
 109     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 110       return X86II::MO_DARWIN_NONLAZY;
 111
 112     // If symbol visibility is hidden, we have a stub for common symbol
 113     // references and external declarations.
 114     if (isDecl || GV->hasCommonLinkage()) {
 115       // Hidden $non_lazy_ptr reference.
 116       return X86II::MO_DARWIN_HIDDEN_NONLAZY;
 117     }
 118
 119     // Otherwise, no stub.
 120     return X86II::MO_NO_FLAG;
 121   }
 122
 123   // Direct static reference to global.
 124   return X86II::MO_NO_FLAG;
 125 }
 126
 127
 128 /// getBZeroEntry - This function returns the name of a function which has an
 129 /// interface like the non-standard bzero function, if such a function exists on
 130 /// the current subtarget and it is considered prefereable over memset with zero
 131 /// passed as the second argument. Otherwise it returns null.
 132 const char *X86Subtarget::getBZeroEntry() const {
 133   // Darwin 10 has a __bzero entry point for this purpose.
 134   if (getDarwinVers() >= 10)
 135     return "__bzero";
 136
 137   return 0;
 138 }
 139
 140 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
 141 /// to immediate address.
 142 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
 143   if (Is64Bit)
 144     return false;
 145   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
 146 }
 147
 148 /// getSpecialAddressLatency - For targets where it is beneficial to
 149 /// backschedule instructions that compute addresses, return a value
 150 /// indicating the number of scheduling cycles of backscheduling that
 151 /// should be attempted.
 152 unsigned X86Subtarget::getSpecialAddressLatency() const {
 153   // For x86 out-of-order targets, back-schedule address computations so
 154   // that loads and stores aren't blocked.
 155   // This value was chosen arbitrarily.
 156   return 200;
 157 }
 158
 159 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 160 /// specified arguments.  If we can't run cpuid on the host, return true.
 161 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
 162                           unsigned *rECX, unsigned *rEDX) {
 163 #if defined(__x86_64__) || defined(_M_AMD64)
 164   #if defined(__GNUC__)
 165     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
 166     asm ("movq\t%%rbx, %%rsi\n\t"
 167          "cpuid\n\t"
 168          "xchgq\t%%rbx, %%rsi\n\t"
 169          : "=a" (*rEAX),
 170            "=S" (*rEBX),
 171            "=c" (*rECX),
 172            "=d" (*rEDX)
 173          :  "a" (value));
 174     return false;
 175   #elif defined(_MSC_VER)
 176     int registers[4];
 177     __cpuid(registers, value);
 178     *rEAX = registers[0];
 179     *rEBX = registers[1];
 180     *rECX = registers[2];
 181     *rEDX = registers[3];
 182     return false;
 183   #endif
 184 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
 185   #if defined(__GNUC__)
 186     asm ("movl\t%%ebx, %%esi\n\t"
 187          "cpuid\n\t"
 188          "xchgl\t%%ebx, %%esi\n\t"
 189          : "=a" (*rEAX),
 190            "=S" (*rEBX),
 191            "=c" (*rECX),
 192            "=d" (*rEDX)
 193          :  "a" (value));
 194     return false;
 195   #elif defined(_MSC_VER)
 196     __asm {
 197       mov   eax,value
 198       cpuid
 199       mov   esi,rEAX
 200       mov   dword ptr [esi],eax
 201       mov   esi,rEBX
 202       mov   dword ptr [esi],ebx
 203       mov   esi,rECX
 204       mov   dword ptr [esi],ecx
 205       mov   esi,rEDX
 206       mov   dword ptr [esi],edx
 207     }
 208     return false;
 209   #endif
 210 #endif
 211   return true;
 212 }
 213
 214 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
 215   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
 216   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
 217   if (Family == 6 || Family == 0xf) {
 218     if (Family == 0xf)
 219       // Examine extended family ID if family ID is F.
 220       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
 221     // Examine extended model ID if family ID is 6 or F.
 222     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
 223   }
 224 }
 225
 226 void X86Subtarget::AutoDetectSubtargetFeatures() {
 227   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 228   union {
 229     unsigned u[3];
 230     char     c[12];
 231   } text;
 232
 233   if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
 234     return;
 235
 236   X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
 237
 238   if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
 239   if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
 240   if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
 241   if (ECX & 0x1)         X86SSELevel = SSE3;
 242   if ((ECX >> 9)  & 0x1) X86SSELevel = SSSE3;
 243   if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
 244   if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
 245
 246   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
 247   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
 248
 249   HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
 250   HasAVX = ((ECX >> 28) & 0x1);
 251
 252   if (IsIntel || IsAMD) {
 253     // Determine if bit test memory instructions are slow.
 254     unsigned Family = 0;
 255     unsigned Model  = 0;
 256     DetectFamilyModel(EAX, Family, Model);
 257     IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
 258
 259     X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 260     HasX86_64 = (EDX >> 29) & 0x1;
 261     HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
 262     HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
 263   }
 264 }
 265
 266 static const char *GetCurrentX86CPU() {
 267   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 268   if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
 269     return "generic";
 270   unsigned Family = 0;
 271   unsigned Model  = 0;
 272   DetectFamilyModel(EAX, Family, Model);
 273
 274   X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 275   bool Em64T = (EDX >> 29) & 0x1;
 276   bool HasSSE3 = (ECX & 0x1);
 277
 278   union {
 279     unsigned u[3];
 280     char     c[12];
 281   } text;
 282
 283   X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
 284   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
 285     switch (Family) {
 286       case 3:
 287         return "i386";
 288       case 4:
 289         return "i486";
 290       case 5:
 291         switch (Model) {
 292         case 4:  return "pentium-mmx";
 293         default: return "pentium";
 294         }
 295       case 6:
 296         switch (Model) {
 297         case 1:  return "pentiumpro";
 298         case 3:
 299         case 5:
 300         case 6:  return "pentium2";
 301         case 7:
 302         case 8:
 303         case 10:
 304         case 11: return "pentium3";
 305         case 9:
 306         case 13: return "pentium-m";
 307         case 14: return "yonah";
 308         case 15:
 309         case 22: // Celeron M 540
 310           return "core2";
 311         case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
 312           return "penryn";
 313         default: return "i686";
 314         }
 315       case 15: {
 316         switch (Model) {
 317         case 3:
 318         case 4:
 319         case 6: // same as 4, but 65nm
 320           return (Em64T) ? "nocona" : "prescott";
 321         case 26:
 322           return "corei7";
 323         case 28:
 324           return "atom";
 325         default:
 326           return (Em64T) ? "x86-64" : "pentium4";
 327         }
 328       }
 329
 330     default:
 331       return "generic";
 332     }
 333   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
 334     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
 335     // appears to be no way to generate the wide variety of AMD-specific targets
 336     // from the information returned from CPUID.
 337     switch (Family) {
 338       case 4:
 339         return "i486";
 340       case 5:
 341         switch (Model) {
 342         case 6:
 343         case 7:  return "k6";
 344         case 8:  return "k6-2";
 345         case 9:
 346         case 13: return "k6-3";
 347         default: return "pentium";
 348         }
 349       case 6:
 350         switch (Model) {
 351         case 4:  return "athlon-tbird";
 352         case 6:
 353         case 7:
 354         case 8:  return "athlon-mp";
 355         case 10: return "athlon-xp";
 356         default: return "athlon";
 357         }
 358       case 15:
 359         if (HasSSE3) {
 360           return "k8-sse3";
 361         } else {
 362           switch (Model) {
 363           case 1:  return "opteron";
 364           case 5:  return "athlon-fx"; // also opteron
 365           default: return "athlon64";
 366           }
 367         }
 368       case 16:
 369         return "amdfam10";
 370     default:
 371       return "generic";
 372     }
 373   } else {
 374     return "generic";
 375   }
 376 }
 377
 378 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
 379                            bool is64Bit)
 380   : PICStyle(PICStyles::None)
 381   , X86SSELevel(NoMMXSSE)
 382   , X863DNowLevel(NoThreeDNow)
 383   , HasX86_64(false)
 384   , HasSSE4A(false)
 385   , HasAVX(false)
 386   , HasFMA3(false)
 387   , HasFMA4(false)
 388   , IsBTMemSlow(false)
 389   , DarwinVers(0)
 390   , IsLinux(false)
 391   , stackAlignment(8)
 392   // FIXME: this is a known good value for Yonah. How about others?
 393   , MaxInlineSizeThreshold(128)
 394   , Is64Bit(is64Bit)
 395   , TargetType(isELF) { // Default to ELF unless otherwise specified.
 396
 397   // default to hard float ABI
 398   if (FloatABIType == FloatABI::Default)
 399     FloatABIType = FloatABI::Hard;
 400
 401   // Determine default and user specified characteristics
 402   if (!FS.empty()) {
 403     // If feature string is not empty, parse features string.
 404     std::string CPU = GetCurrentX86CPU();
 405     ParseSubtargetFeatures(FS, CPU);
 406     // All X86-64 CPUs also have SSE2, however user might request no SSE via
 407     // -mattr, so don't force SSELevel here.
 408   } else {
 409     // Otherwise, use CPUID to auto-detect feature set.
 410     AutoDetectSubtargetFeatures();
 411     // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
 412     if (Is64Bit && X86SSELevel < SSE2)
 413       X86SSELevel = SSE2;
 414   }
 415
 416   // If requesting codegen for X86-64, make sure that 64-bit features
 417   // are enabled.
 418   if (Is64Bit)
 419     HasX86_64 = true;
 420
 421   DEBUG(errs() << "Subtarget features: SSELevel " << X86SSELevel
 422                << ", 3DNowLevel " << X863DNowLevel
 423                << ", 64bit " << HasX86_64 << "\n");
 424   assert((!Is64Bit || HasX86_64) &&
 425          "64-bit code requested on a subtarget that doesn't support it!");
 426
 427   // Set the boolean corresponding to the current target triple, or the default
 428   // if one cannot be determined, to true.
 429   if (TT.length() > 5) {
 430     size_t Pos;
 431     if ((Pos = TT.find("-darwin")) != std::string::npos) {
 432       TargetType = isDarwin;
 433
 434       // Compute the darwin version number.
 435       if (isdigit(TT[Pos+7]))
 436         DarwinVers = atoi(&TT[Pos+7]);
 437       else
 438         DarwinVers = 8;  // Minimum supported darwin is Tiger.
 439     } else if (TT.find("linux") != std::string::npos) {
 440       // Linux doesn't imply ELF, but we don't currently support anything else.
 441       TargetType = isELF;
 442       IsLinux = true;
 443     } else if (TT.find("cygwin") != std::string::npos) {
 444       TargetType = isCygwin;
 445     } else if (TT.find("mingw") != std::string::npos) {
 446       TargetType = isMingw;
 447     } else if (TT.find("win32") != std::string::npos) {
 448       TargetType = isWindows;
 449     } else if (TT.find("windows") != std::string::npos) {
 450       TargetType = isWindows;
 451     } else if (TT.find("-cl") != std::string::npos) {
 452       TargetType = isDarwin;
 453       DarwinVers = 9;
 454     }
 455   }
 456
 457   // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
 458   // bit targets.
 459   if (TargetType == isDarwin || Is64Bit)
 460     stackAlignment = 16;
 461
 462   if (StackAlignment)
 463     stackAlignment = StackAlignment;
 464 }