Change allowsUnalignedMemoryAccesses to take type argument since some targets
[llvm/avr.git] / lib / Target / XCore / XCore.td
blob7a2dcdbf9fe58e202d7608242d42d137e0ba551a
1 //===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // Descriptions
21 //===----------------------------------------------------------------------===//
23 include "XCoreRegisterInfo.td"
24 include "XCoreInstrInfo.td"
25 include "XCoreCallingConv.td"
27 def XCoreInstrInfo : InstrInfo {
28   let TSFlagsFields = [];
29   let TSFlagsShifts = [];
32 //===----------------------------------------------------------------------===//
33 // XCore Subtarget features.
34 //===----------------------------------------------------------------------===//
36 def FeatureXS1A
37   : SubtargetFeature<"xs1a", "IsXS1A", "true",
38                      "Enable XS1A instructions">;
40 def FeatureXS1B
41   : SubtargetFeature<"xs1b", "IsXS1B", "true",
42                      "Enable XS1B instructions">;
44 //===----------------------------------------------------------------------===//
45 // XCore processors supported.
46 //===----------------------------------------------------------------------===//
48 class Proc<string Name, list<SubtargetFeature> Features>
49  : Processor<Name, NoItineraries, Features>;
51 def : Proc<"generic",      [FeatureXS1A]>;
52 def : Proc<"xs1a-generic", [FeatureXS1A]>;
53 def : Proc<"xs1b-generic", [FeatureXS1B]>;
55 //===----------------------------------------------------------------------===//
56 // Declare the target which we are implementing
57 //===----------------------------------------------------------------------===//
59 def XCore : Target {
60   // Pull in Instruction Info:
61   let InstructionSet = XCoreInstrInfo;