1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 ; This tests fcmp operations that do not map directly to NEON instructions.
5 ; une is implemented with VCEQ/VMVN
6 define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
10 %tmp1 = load <2 x float>* %A
11 %tmp2 = load <2 x float>* %B
12 %tmp3 = fcmp une <2 x float> %tmp1, %tmp2
13 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
17 ; olt is implemented with VCGT
18 define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
21 %tmp1 = load <2 x float>* %A
22 %tmp2 = load <2 x float>* %B
23 %tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
24 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
28 ; ole is implemented with VCGE
29 define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
32 %tmp1 = load <2 x float>* %A
33 %tmp2 = load <2 x float>* %B
34 %tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
35 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
39 ; uge is implemented with VCGT/VMVN
40 define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
44 %tmp1 = load <2 x float>* %A
45 %tmp2 = load <2 x float>* %B
46 %tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
47 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
51 ; ule is implemented with VCGT/VMVN
52 define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
56 %tmp1 = load <2 x float>* %A
57 %tmp2 = load <2 x float>* %B
58 %tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
59 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
63 ; ugt is implemented with VCGE/VMVN
64 define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
68 %tmp1 = load <2 x float>* %A
69 %tmp2 = load <2 x float>* %B
70 %tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
71 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
75 ; ult is implemented with VCGE/VMVN
76 define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
80 %tmp1 = load <2 x float>* %A
81 %tmp2 = load <2 x float>* %B
82 %tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
83 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
88 define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
94 %tmp1 = load <2 x float>* %A
95 %tmp2 = load <2 x float>* %B
96 %tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
97 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
101 ; one is implemented with VCGT/VCGT/VORR
102 define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
105 ;CHECK-NEXT: vcgt.f32
107 %tmp1 = load <2 x float>* %A
108 %tmp2 = load <2 x float>* %B
109 %tmp3 = fcmp one <2 x float> %tmp1, %tmp2
110 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
115 define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
118 ;CHECK-NEXT: vcgt.f32
121 %tmp1 = load <2 x float>* %A
122 %tmp2 = load <2 x float>* %B
123 %tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
124 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
128 ; ord is implemented with VCGT/VCGE/VORR
129 define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
132 ;CHECK-NEXT: vcgt.f32
134 %tmp1 = load <2 x float>* %A
135 %tmp2 = load <2 x float>* %B
136 %tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
137 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>