1 //===- LazyLiveness.cpp - Lazy, CFG-invariant liveness information --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass implements a lazy liveness analysis as per "Fast Liveness Checking
11 // for SSA-form Programs," by Boissinot, et al.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "lazyliveness"
16 #include "llvm/CodeGen/LazyLiveness.h"
17 #include "llvm/CodeGen/MachineDominators.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/ADT/DepthFirstIterator.h"
21 #include "llvm/ADT/PostOrderIterator.h"
24 char LazyLiveness::ID
= 0;
25 static RegisterPass
<LazyLiveness
> X("lazy-liveness", "Lazy Liveness Analysis");
27 void LazyLiveness::computeBackedgeChain(MachineFunction
& mf
,
28 MachineBasicBlock
* MBB
) {
29 SparseBitVector
<128> tmp
= rv
[MBB
];
30 tmp
.set(preorder
[MBB
]);
31 tmp
&= backedge_source
;
32 calculated
.set(preorder
[MBB
]);
34 for (SparseBitVector
<128>::iterator I
= tmp
.begin(); I
!= tmp
.end(); ++I
) {
35 assert(rev_preorder
.size() > *I
&& "Unknown block!");
37 MachineBasicBlock
* SrcMBB
= rev_preorder
[*I
];
39 for (MachineBasicBlock::succ_iterator SI
= SrcMBB
->succ_begin(),
40 SE
= SrcMBB
->succ_end(); SI
!= SE
; ++SI
) {
41 MachineBasicBlock
* TgtMBB
= *SI
;
43 if (backedges
.count(std::make_pair(SrcMBB
, TgtMBB
)) &&
44 !rv
[MBB
].test(preorder
[TgtMBB
])) {
45 if (!calculated
.test(preorder
[TgtMBB
]))
46 computeBackedgeChain(mf
, TgtMBB
);
48 tv
[MBB
].set(preorder
[TgtMBB
]);
49 SparseBitVector
<128> right
= tv
[TgtMBB
];
54 tv
[MBB
].reset(preorder
[MBB
]);
58 bool LazyLiveness::runOnMachineFunction(MachineFunction
&mf
) {
62 backedge_source
.clear();
63 backedge_target
.clear();
70 preorder
.resize(mf
.size());
71 rev_preorder
.reserve(mf
.size());
73 MRI
= &mf
.getRegInfo();
74 MachineDominatorTree
& MDT
= getAnalysis
<MachineDominatorTree
>();
76 // Step 0: Compute preorder numbering for all MBBs.
78 for (df_iterator
<MachineDomTreeNode
*> DI
= df_begin(MDT
.getRootNode()),
79 DE
= df_end(MDT
.getRootNode()); DI
!= DE
; ++DI
) {
80 preorder
[(*DI
)->getBlock()] = num
++;
81 rev_preorder
.push_back((*DI
)->getBlock());
84 // Step 1: Compute the transitive closure of the CFG, ignoring backedges.
85 for (po_iterator
<MachineBasicBlock
*> POI
= po_begin(&*mf
.begin()),
86 POE
= po_end(&*mf
.begin()); POI
!= POE
; ++POI
) {
87 MachineBasicBlock
* MBB
= *POI
;
88 SparseBitVector
<128>& entry
= rv
[MBB
];
89 entry
.set(preorder
[MBB
]);
91 for (MachineBasicBlock::succ_iterator SI
= MBB
->succ_begin(),
92 SE
= MBB
->succ_end(); SI
!= SE
; ++SI
) {
93 DenseMap
<MachineBasicBlock
*, SparseBitVector
<128> >::iterator SII
=
96 // Because we're iterating in postorder, any successor that does not yet
97 // have an rv entry must be on a backedge.
98 if (SII
!= rv
.end()) {
101 backedges
.insert(std::make_pair(MBB
, *SI
));
102 backedge_source
.set(preorder
[MBB
]);
103 backedge_target
.set(preorder
[*SI
]);
108 for (SparseBitVector
<128>::iterator I
= backedge_source
.begin();
109 I
!= backedge_source
.end(); ++I
)
110 computeBackedgeChain(mf
, rev_preorder
[*I
]);
112 for (po_iterator
<MachineBasicBlock
*> POI
= po_begin(&*mf
.begin()),
113 POE
= po_end(&*mf
.begin()); POI
!= POE
; ++POI
)
114 if (!backedge_target
.test(preorder
[*POI
]))
115 for (MachineBasicBlock::succ_iterator SI
= (*POI
)->succ_begin(),
116 SE
= (*POI
)->succ_end(); SI
!= SE
; ++SI
)
117 if (!backedges
.count(std::make_pair(*POI
, *SI
)) && tv
.count(*SI
)) {
118 SparseBitVector
<128> right
= tv
[*SI
];
122 for (po_iterator
<MachineBasicBlock
*> POI
= po_begin(&*mf
.begin()),
123 POE
= po_end(&*mf
.begin()); POI
!= POE
; ++POI
)
124 tv
[*POI
].set(preorder
[*POI
]);
129 bool LazyLiveness::vregLiveIntoMBB(unsigned vreg
, MachineBasicBlock
* MBB
) {
130 MachineDominatorTree
& MDT
= getAnalysis
<MachineDominatorTree
>();
132 MachineBasicBlock
* DefMBB
= MRI
->def_begin(vreg
)->getParent();
133 unsigned def
= preorder
[DefMBB
];
134 unsigned max_dom
= 0;
135 for (df_iterator
<MachineDomTreeNode
*> DI
= df_begin(MDT
[DefMBB
]),
136 DE
= df_end(MDT
[DefMBB
]); DI
!= DE
; ++DI
) {
137 if (preorder
[DI
->getBlock()] > max_dom
) {
138 max_dom
= preorder
[(*DI
)->getBlock()];
142 if (preorder
[MBB
] <= def
|| max_dom
< preorder
[MBB
])
145 SparseBitVector
<128>::iterator I
= tv
[MBB
].begin();
146 while (I
!= tv
[MBB
].end() && *I
<= def
) ++I
;
147 while (I
!= tv
[MBB
].end() && *I
< max_dom
) {
148 for (MachineRegisterInfo::use_iterator UI
= MRI
->use_begin(vreg
),
149 UE
= MachineRegisterInfo::use_end(); UI
!= UE
; ++UI
) {
150 MachineBasicBlock
* UseMBB
= UI
->getParent();
151 if (rv
[rev_preorder
[*I
]].test(preorder
[UseMBB
]))
155 for (df_iterator
<MachineDomTreeNode
*> DI
=
156 df_begin(MDT
[rev_preorder
[*I
]]), DE
= df_end(MDT
[rev_preorder
[*I
]]);
158 if (preorder
[DI
->getBlock()] > t_dom
) {
159 max_dom
= preorder
[(*DI
)->getBlock()];
162 while (I
!= tv
[MBB
].end() && *I
< t_dom
) ++I
;