lib/CodeGen/LowerSubregs.cpp

   1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a MachineFunction pass which runs after register
  11 // allocation that turns subreg insert/extract instructions into register
  12 // copies, as needed. This ensures correct codegen even if the coalescer
  13 // isn't able to remove all subreg instructions.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "lowersubregs"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/Compiler.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 using namespace llvm;
  31
  32 namespace {
  33   struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
  34    : public MachineFunctionPass {
  35     static char ID; // Pass identification, replacement for typeid
  36     LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
  37
  38     const char *getPassName() const {
  39       return "Subregister lowering instruction pass";
  40     }
  41
  42     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  43       AU.setPreservesCFG();
  44       AU.addPreservedID(MachineLoopInfoID);
  45       AU.addPreservedID(MachineDominatorsID);
  46       MachineFunctionPass::getAnalysisUsage(AU);
  47     }
  48
  49     /// runOnMachineFunction - pass entry point
  50     bool runOnMachineFunction(MachineFunction&);
  51
  52     bool LowerExtract(MachineInstr *MI);
  53     bool LowerInsert(MachineInstr *MI);
  54     bool LowerSubregToReg(MachineInstr *MI);
  55
  56     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
  57                           const TargetRegisterInfo &TRI);
  58     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
  59                           const TargetRegisterInfo &TRI);
  60   };
  61
  62   char LowerSubregsInstructionPass::ID = 0;
  63 }
  64
  65 FunctionPass *llvm::createLowerSubregsPass() {
  66   return new LowerSubregsInstructionPass();
  67 }
  68
  69 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
  70 /// and the lowered replacement instructions immediately precede it.
  71 /// Mark the replacement instructions with the dead flag.
  72 void
  73 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
  74                                               unsigned DstReg,
  75                                               const TargetRegisterInfo &TRI) {
  76   for (MachineBasicBlock::iterator MII =
  77         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  78     if (MII->addRegisterDead(DstReg, &TRI))
  79       break;
  80     assert(MII != MI->getParent()->begin() &&
  81            "copyRegToReg output doesn't reference destination register!");
  82   }
  83 }
  84
  85 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
  86 /// and the lowered replacement instructions immediately precede it.
  87 /// Mark the replacement instructions with the kill flag.
  88 void
  89 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
  90                                               unsigned SrcReg,
  91                                               const TargetRegisterInfo &TRI) {
  92   for (MachineBasicBlock::iterator MII =
  93         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  94     if (MII->addRegisterKilled(SrcReg, &TRI))
  95       break;
  96     assert(MII != MI->getParent()->begin() &&
  97            "copyRegToReg output doesn't reference source register!");
  98   }
  99 }
 100
 101 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
 102   MachineBasicBlock *MBB = MI->getParent();
 103   MachineFunction &MF = *MBB->getParent();
 104   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 105   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 106
 107   assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
 108          MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
 109          MI->getOperand(2).isImm() && "Malformed extract_subreg");
 110
 111   unsigned DstReg   = MI->getOperand(0).getReg();
 112   unsigned SuperReg = MI->getOperand(1).getReg();
 113   unsigned SubIdx   = MI->getOperand(2).getImm();
 114   unsigned SrcReg   = TRI.getSubReg(SuperReg, SubIdx);
 115
 116   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
 117          "Extract supperg source must be a physical register");
 118   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 119          "Extract destination must be in a physical register");
 120
 121   DOUT << "subreg: CONVERTING: " << *MI;
 122
 123   if (SrcReg == DstReg) {
 124     // No need to insert an identity copy instruction.
 125     if (MI->getOperand(1).isKill()) {
 126       // We must make sure the super-register gets killed.Replace the
 127       // instruction with IMPLICIT_DEF.
 128       MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
 129       MI->RemoveOperand(2);     // SubIdx
 130       DOUT << "subreg: replace by: " << *MI;
 131       return true;
 132     }
 133     DOUT << "subreg: eliminated!";
 134   } else {
 135     // Insert copy
 136     const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
 137     const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
 138     bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
 139     (void)Emitted;
 140     assert(Emitted && "Subreg and Dst must be of compatible register class");
 141     // Transfer the kill/dead flags, if needed.
 142     if (MI->getOperand(0).isDead())
 143       TransferDeadFlag(MI, DstReg, TRI);
 144     if (MI->getOperand(1).isKill())
 145       TransferKillFlag(MI, SrcReg, TRI);
 146
 147 #ifndef NDEBUG
 148     MachineBasicBlock::iterator dMI = MI;
 149     DOUT << "subreg: " << *(--dMI);
 150 #endif
 151   }
 152
 153   DOUT << "\n";
 154   MBB->erase(MI);
 155   return true;
 156 }
 157
 158 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
 159   MachineBasicBlock *MBB = MI->getParent();
 160   MachineFunction &MF = *MBB->getParent();
 161   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 162   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 163   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 164          MI->getOperand(1).isImm() &&
 165          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 166           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 167
 168   unsigned DstReg  = MI->getOperand(0).getReg();
 169   unsigned InsReg  = MI->getOperand(2).getReg();
 170   unsigned InsSIdx = MI->getOperand(2).getSubReg();
 171   unsigned SubIdx  = MI->getOperand(3).getImm();
 172
 173   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 174   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 175
 176   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 177          "Insert destination must be in a physical register");
 178   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 179          "Inserted value must be in a physical register");
 180
 181   DOUT << "subreg: CONVERTING: " << *MI;
 182
 183   if (DstSubReg == InsReg && InsSIdx == 0) {
 184     // No need to insert an identify copy instruction.
 185     // Watch out for case like this:
 186     // %RAX<def> = ...
 187     // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
 188     // The first def is defining RAX, not EAX so the top bits were not
 189     // zero extended.
 190     DOUT << "subreg: eliminated!";
 191   } else {
 192     // Insert sub-register copy
 193     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 194     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 195     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 196     // Transfer the kill/dead flags, if needed.
 197     if (MI->getOperand(0).isDead())
 198       TransferDeadFlag(MI, DstSubReg, TRI);
 199     if (MI->getOperand(2).isKill())
 200       TransferKillFlag(MI, InsReg, TRI);
 201
 202 #ifndef NDEBUG
 203     MachineBasicBlock::iterator dMI = MI;
 204     DOUT << "subreg: " << *(--dMI);
 205 #endif
 206   }
 207
 208   DOUT << "\n";
 209   MBB->erase(MI);
 210   return true;
 211 }
 212
 213 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
 214   MachineBasicBlock *MBB = MI->getParent();
 215   MachineFunction &MF = *MBB->getParent();
 216   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 217   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 218   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 219          (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
 220          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 221           MI->getOperand(3).isImm() && "Invalid insert_subreg");
 222
 223   unsigned DstReg = MI->getOperand(0).getReg();
 224 #ifndef NDEBUG
 225   unsigned SrcReg = MI->getOperand(1).getReg();
 226 #endif
 227   unsigned InsReg = MI->getOperand(2).getReg();
 228   unsigned SubIdx = MI->getOperand(3).getImm();
 229
 230   assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
 231   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 232   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 233   assert(DstSubReg && "invalid subregister index for register");
 234   assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
 235          "Insert superreg source must be in a physical register");
 236   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 237          "Inserted value must be in a physical register");
 238
 239   DOUT << "subreg: CONVERTING: " << *MI;
 240
 241   if (DstSubReg == InsReg) {
 242     // No need to insert an identity copy instruction. If the SrcReg was
 243     // <undef>, we need to make sure it is alive by inserting an IMPLICIT_DEF
 244     if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
 245       BuildMI(*MBB, MI, MI->getDebugLoc(),
 246               TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg)
 247         .addReg(InsReg, RegState::ImplicitKill);
 248     } else {
 249       DOUT << "subreg: eliminated!\n";
 250       MBB->erase(MI);
 251       return true;
 252     }
 253   } else {
 254     // Insert sub-register copy
 255     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 256     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 257     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 258     MachineBasicBlock::iterator CopyMI = MI;
 259     --CopyMI;
 260
 261     // Transfer the kill/dead flags, if needed.
 262     if (MI->getOperand(0).isDead()) {
 263       TransferDeadFlag(MI, DstSubReg, TRI);
 264       // Also add a SrcReg<imp-kill> of the super register.
 265       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
 266     } else if (MI->getOperand(1).isUndef()) {
 267       // If SrcReg was marked <undef> we must make sure it is alive after this
 268       // replacement.  Add a SrcReg<imp-def> operand.
 269       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
 270     }
 271
 272     // Make sure the inserted register gets killed
 273     if (MI->getOperand(2).isKill())
 274       TransferKillFlag(MI, InsReg, TRI);
 275   }
 276
 277 #ifndef NDEBUG
 278   MachineBasicBlock::iterator dMI = MI;
 279   DOUT << "subreg: " << *(--dMI);
 280 #endif
 281
 282   DOUT << "\n";
 283   MBB->erase(MI);
 284   return true;
 285 }
 286
 287 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 288 /// copies.
 289 ///
 290 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 291   DOUT << "Machine Function\n";
 292
 293   bool MadeChange = false;
 294
 295   DOUT << "********** LOWERING SUBREG INSTRS **********\n";
 296   DEBUG(errs() << "********** Function: "
 297         << MF.getFunction()->getName() << '\n');
 298
 299   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
 300        mbbi != mbbe; ++mbbi) {
 301     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
 302          mi != me;) {
 303       MachineInstr *MI = mi++;
 304
 305       if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
 306         MadeChange |= LowerExtract(MI);
 307       } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
 308         MadeChange |= LowerInsert(MI);
 309       } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
 310         MadeChange |= LowerSubregToReg(MI);
 311       }
 312     }
 313   }
 314
 315   return MadeChange;
 316 }