lib/Target/ARM/ARMAddressingModes.h

   1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ARM addressing mode implementation stuff.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
  15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
  16
  17 #include "llvm/CodeGen/SelectionDAGNodes.h"
  18 #include "llvm/Support/ErrorHandling.h"
  19 #include "llvm/Support/MathExtras.h"
  20 #include <cassert>
  21
  22 namespace llvm {
  23
  24 /// ARM_AM - ARM Addressing Mode Stuff
  25 namespace ARM_AM {
  26   enum ShiftOpc {
  27     no_shift = 0,
  28     asr,
  29     lsl,
  30     lsr,
  31     ror,
  32     rrx
  33   };
  34
  35   enum AddrOpc {
  36     add = '+', sub = '-'
  37   };
  38
  39   static inline const char *getShiftOpcStr(ShiftOpc Op) {
  40     switch (Op) {
  41     default: llvm_unreachable("Unknown shift opc!");
  42     case ARM_AM::asr: return "asr";
  43     case ARM_AM::lsl: return "lsl";
  44     case ARM_AM::lsr: return "lsr";
  45     case ARM_AM::ror: return "ror";
  46     case ARM_AM::rrx: return "rrx";
  47     }
  48   }
  49
  50   static inline ShiftOpc getShiftOpcForNode(SDValue N) {
  51     switch (N.getOpcode()) {
  52     default:          return ARM_AM::no_shift;
  53     case ISD::SHL:    return ARM_AM::lsl;
  54     case ISD::SRL:    return ARM_AM::lsr;
  55     case ISD::SRA:    return ARM_AM::asr;
  56     case ISD::ROTR:   return ARM_AM::ror;
  57     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
  58     // Can't handle RRX here, because it would require folding a flag into
  59     // the addressing mode.  :(  This causes us to miss certain things.
  60     //case ARMISD::RRX: return ARM_AM::rrx;
  61     }
  62   }
  63
  64   enum AMSubMode {
  65     bad_am_submode = 0,
  66     ia,
  67     ib,
  68     da,
  69     db
  70   };
  71
  72   static inline const char *getAMSubModeStr(AMSubMode Mode) {
  73     switch (Mode) {
  74     default: llvm_unreachable("Unknown addressing sub-mode!");
  75     case ARM_AM::ia: return "ia";
  76     case ARM_AM::ib: return "ib";
  77     case ARM_AM::da: return "da";
  78     case ARM_AM::db: return "db";
  79     }
  80   }
  81
  82   static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
  83     switch (Mode) {
  84     default: llvm_unreachable("Unknown addressing sub-mode!");
  85     case ARM_AM::ia: return isLD ? "fd" : "ea";
  86     case ARM_AM::ib: return isLD ? "ed" : "fa";
  87     case ARM_AM::da: return isLD ? "fa" : "ed";
  88     case ARM_AM::db: return isLD ? "ea" : "fd";
  89     }
  90   }
  91
  92   /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
  93   ///
  94   static inline unsigned rotr32(unsigned Val, unsigned Amt) {
  95     assert(Amt < 32 && "Invalid rotate amount");
  96     return (Val >> Amt) | (Val << ((32-Amt)&31));
  97   }
  98
  99   /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
 100   ///
 101   static inline unsigned rotl32(unsigned Val, unsigned Amt) {
 102     assert(Amt < 32 && "Invalid rotate amount");
 103     return (Val << Amt) | (Val >> ((32-Amt)&31));
 104   }
 105
 106   //===--------------------------------------------------------------------===//
 107   // Addressing Mode #1: shift_operand with registers
 108   //===--------------------------------------------------------------------===//
 109   //
 110   // This 'addressing mode' is used for arithmetic instructions.  It can
 111   // represent things like:
 112   //   reg
 113   //   reg [asr|lsl|lsr|ror|rrx] reg
 114   //   reg [asr|lsl|lsr|ror|rrx] imm
 115   //
 116   // This is stored three operands [rega, regb, opc].  The first is the base
 117   // reg, the second is the shift amount (or reg0 if not present or imm).  The
 118   // third operand encodes the shift opcode and the imm if a reg isn't present.
 119   //
 120   static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
 121     return ShOp | (Imm << 3);
 122   }
 123   static inline unsigned getSORegOffset(unsigned Op) {
 124     return Op >> 3;
 125   }
 126   static inline ShiftOpc getSORegShOp(unsigned Op) {
 127     return (ShiftOpc)(Op & 7);
 128   }
 129
 130   /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
 131   /// the 8-bit imm value.
 132   static inline unsigned getSOImmValImm(unsigned Imm) {
 133     return Imm & 0xFF;
 134   }
 135   /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
 136   /// the rotate amount.
 137   static inline unsigned getSOImmValRot(unsigned Imm) {
 138     return (Imm >> 8) * 2;
 139   }
 140
 141   /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
 142   /// computing the rotate amount to use.  If this immediate value cannot be
 143   /// handled with a single shifter-op, determine a good rotate amount that will
 144   /// take a maximal chunk of bits out of the immediate.
 145   static inline unsigned getSOImmValRotate(unsigned Imm) {
 146     // 8-bit (or less) immediates are trivially shifter_operands with a rotate
 147     // of zero.
 148     if ((Imm & ~255U) == 0) return 0;
 149
 150     // Use CTZ to compute the rotate amount.
 151     unsigned TZ = CountTrailingZeros_32(Imm);
 152
 153     // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
 154     // not 9.
 155     unsigned RotAmt = TZ & ~1;
 156
 157     // If we can handle this spread, return it.
 158     if ((rotr32(Imm, RotAmt) & ~255U) == 0)
 159       return (32-RotAmt)&31;  // HW rotates right, not left.
 160
 161     // For values like 0xF000000F, we should skip the first run of ones, then
 162     // retry the hunt.
 163     if (Imm & 1) {
 164       unsigned TrailingOnes = CountTrailingZeros_32(~Imm);
 165       if (TrailingOnes != 32) {  // Avoid overflow on 0xFFFFFFFF
 166         // Restart the search for a high-order bit after the initial seconds of
 167         // ones.
 168         unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1));
 169
 170         // Rotate amount must be even.
 171         unsigned RotAmt2 = TZ2 & ~1;
 172
 173         // If this fits, use it.
 174         if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0)
 175           return (32-RotAmt2)&31;  // HW rotates right, not left.
 176       }
 177     }
 178
 179     // Otherwise, we have no way to cover this span of bits with a single
 180     // shifter_op immediate.  Return a chunk of bits that will be useful to
 181     // handle.
 182     return (32-RotAmt)&31;  // HW rotates right, not left.
 183   }
 184
 185   /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
 186   /// into an shifter_operand immediate operand, return the 12-bit encoding for
 187   /// it.  If not, return -1.
 188   static inline int getSOImmVal(unsigned Arg) {
 189     // 8-bit (or less) immediates are trivially shifter_operands with a rotate
 190     // of zero.
 191     if ((Arg & ~255U) == 0) return Arg;
 192
 193     unsigned RotAmt = getSOImmValRotate(Arg);
 194
 195     // If this cannot be handled with a single shifter_op, bail out.
 196     if (rotr32(~255U, RotAmt) & Arg)
 197       return -1;
 198
 199     // Encode this correctly.
 200     return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
 201   }
 202
 203   /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
 204   /// or'ing together two SOImmVal's.
 205   static inline bool isSOImmTwoPartVal(unsigned V) {
 206     // If this can be handled with a single shifter_op, bail out.
 207     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 208     if (V == 0)
 209       return false;
 210
 211     // If this can be handled with two shifter_op's, accept.
 212     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 213     return V == 0;
 214   }
 215
 216   /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
 217   /// return the first chunk of it.
 218   static inline unsigned getSOImmTwoPartFirst(unsigned V) {
 219     return rotr32(255U, getSOImmValRotate(V)) & V;
 220   }
 221
 222   /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
 223   /// return the second chunk of it.
 224   static inline unsigned getSOImmTwoPartSecond(unsigned V) {
 225     // Mask out the first hunk.
 226     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 227
 228     // Take what's left.
 229     assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
 230     return V;
 231   }
 232
 233   /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
 234   /// by a left shift. Returns the shift amount to use.
 235   static inline unsigned getThumbImmValShift(unsigned Imm) {
 236     // 8-bit (or less) immediates are trivially immediate operand with a shift
 237     // of zero.
 238     if ((Imm & ~255U) == 0) return 0;
 239
 240     // Use CTZ to compute the shift amount.
 241     return CountTrailingZeros_32(Imm);
 242   }
 243
 244   /// isThumbImmShiftedVal - Return true if the specified value can be obtained
 245   /// by left shifting a 8-bit immediate.
 246   static inline bool isThumbImmShiftedVal(unsigned V) {
 247     // If this can be handled with
 248     V = (~255U << getThumbImmValShift(V)) & V;
 249     return V == 0;
 250   }
 251
 252   /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
 253   /// by a left shift. Returns the shift amount to use.
 254   static inline unsigned getThumbImm16ValShift(unsigned Imm) {
 255     // 16-bit (or less) immediates are trivially immediate operand with a shift
 256     // of zero.
 257     if ((Imm & ~65535U) == 0) return 0;
 258
 259     // Use CTZ to compute the shift amount.
 260     return CountTrailingZeros_32(Imm);
 261   }
 262
 263   /// isThumbImm16ShiftedVal - Return true if the specified value can be
 264   /// obtained by left shifting a 16-bit immediate.
 265   static inline bool isThumbImm16ShiftedVal(unsigned V) {
 266     // If this can be handled with
 267     V = (~65535U << getThumbImm16ValShift(V)) & V;
 268     return V == 0;
 269   }
 270
 271   /// getThumbImmNonShiftedVal - If V is a value that satisfies
 272   /// isThumbImmShiftedVal, return the non-shiftd value.
 273   static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
 274     return V >> getThumbImmValShift(V);
 275   }
 276
 277
 278   /// getT2SOImmValSplat - Return the 12-bit encoded representation
 279   /// if the specified value can be obtained by splatting the low 8 bits
 280   /// into every other byte or every byte of a 32-bit value. i.e.,
 281   ///     00000000 00000000 00000000 abcdefgh    control = 0
 282   ///     00000000 abcdefgh 00000000 abcdefgh    control = 1
 283   ///     abcdefgh 00000000 abcdefgh 00000000    control = 2
 284   ///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
 285   /// Return -1 if none of the above apply.
 286   /// See ARM Reference Manual A6.3.2.
 287   static inline int getT2SOImmValSplatVal(unsigned V) {
 288     unsigned u, Vs, Imm;
 289     // control = 0
 290     if ((V & 0xffffff00) == 0)
 291       return V;
 292
 293     // If the value is zeroes in the first byte, just shift those off
 294     Vs = ((V & 0xff) == 0) ? V >> 8 : V;
 295     // Any passing value only has 8 bits of payload, splatted across the word
 296     Imm = Vs & 0xff;
 297     // Likewise, any passing values have the payload splatted into the 3rd byte
 298     u = Imm | (Imm << 16);
 299
 300     // control = 1 or 2
 301     if (Vs == u)
 302       return (((Vs == V) ? 1 : 2) << 8) | Imm;
 303
 304     // control = 3
 305     if (Vs == (u | (u << 8)))
 306       return (3 << 8) | Imm;
 307
 308     return -1;
 309   }
 310
 311   /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
 312   /// specified value is a rotated 8-bit value. Return -1 if no rotation
 313   /// encoding is possible.
 314   /// See ARM Reference Manual A6.3.2.
 315   static inline int getT2SOImmValRotateVal(unsigned V) {
 316     unsigned RotAmt = CountLeadingZeros_32(V);
 317     if (RotAmt >= 24)
 318       return -1;
 319
 320     // If 'Arg' can be handled with a single shifter_op return the value.
 321     if ((rotr32(0xff000000U, RotAmt) & V) == V)
 322       return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
 323
 324     return -1;
 325   }
 326
 327   /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
 328   /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
 329   /// encoding for it.  If not, return -1.
 330   /// See ARM Reference Manual A6.3.2.
 331   static inline int getT2SOImmVal(unsigned Arg) {
 332     // If 'Arg' is an 8-bit splat, then get the encoded value.
 333     int Splat = getT2SOImmValSplatVal(Arg);
 334     if (Splat != -1)
 335       return Splat;
 336
 337     // If 'Arg' can be handled with a single shifter_op return the value.
 338     int Rot = getT2SOImmValRotateVal(Arg);
 339     if (Rot != -1)
 340       return Rot;
 341
 342     return -1;
 343   }
 344
 345
 346   //===--------------------------------------------------------------------===//
 347   // Addressing Mode #2
 348   //===--------------------------------------------------------------------===//
 349   //
 350   // This is used for most simple load/store instructions.
 351   //
 352   // addrmode2 := reg +/- reg shop imm
 353   // addrmode2 := reg +/- imm12
 354   //
 355   // The first operand is always a Reg.  The second operand is a reg if in
 356   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 357   // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
 358   //
 359   // If this addressing mode is a frame index (before prolog/epilog insertion
 360   // and code rewriting), this operand will have the form:  FI#, reg0, <offs>
 361   // with no shift amount for the frame offset.
 362   //
 363   static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
 364     assert(Imm12 < (1 << 12) && "Imm too large!");
 365     bool isSub = Opc == sub;
 366     return Imm12 | ((int)isSub << 12) | (SO << 13);
 367   }
 368   static inline unsigned getAM2Offset(unsigned AM2Opc) {
 369     return AM2Opc & ((1 << 12)-1);
 370   }
 371   static inline AddrOpc getAM2Op(unsigned AM2Opc) {
 372     return ((AM2Opc >> 12) & 1) ? sub : add;
 373   }
 374   static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
 375     return (ShiftOpc)(AM2Opc >> 13);
 376   }
 377
 378
 379   //===--------------------------------------------------------------------===//
 380   // Addressing Mode #3
 381   //===--------------------------------------------------------------------===//
 382   //
 383   // This is used for sign-extending loads, and load/store-pair instructions.
 384   //
 385   // addrmode3 := reg +/- reg
 386   // addrmode3 := reg +/- imm8
 387   //
 388   // The first operand is always a Reg.  The second operand is a reg if in
 389   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 390   // in bit 8, the immediate in bits 0-7.
 391
 392   /// getAM3Opc - This function encodes the addrmode3 opc field.
 393   static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
 394     bool isSub = Opc == sub;
 395     return ((int)isSub << 8) | Offset;
 396   }
 397   static inline unsigned char getAM3Offset(unsigned AM3Opc) {
 398     return AM3Opc & 0xFF;
 399   }
 400   static inline AddrOpc getAM3Op(unsigned AM3Opc) {
 401     return ((AM3Opc >> 8) & 1) ? sub : add;
 402   }
 403
 404   //===--------------------------------------------------------------------===//
 405   // Addressing Mode #4
 406   //===--------------------------------------------------------------------===//
 407   //
 408   // This is used for load / store multiple instructions.
 409   //
 410   // addrmode4 := reg, <mode>
 411   //
 412   // The four modes are:
 413   //    IA - Increment after
 414   //    IB - Increment before
 415   //    DA - Decrement after
 416   //    DB - Decrement before
 417   //
 418   // If the 4th bit (writeback)is set, then the base register is updated after
 419   // the memory transfer.
 420
 421   static inline AMSubMode getAM4SubMode(unsigned Mode) {
 422     return (AMSubMode)(Mode & 0x7);
 423   }
 424
 425   static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) {
 426     return (int)SubMode | ((int)WB << 3);
 427   }
 428
 429   static inline bool getAM4WBFlag(unsigned Mode) {
 430     return (Mode >> 3) & 1;
 431   }
 432
 433   //===--------------------------------------------------------------------===//
 434   // Addressing Mode #5
 435   //===--------------------------------------------------------------------===//
 436   //
 437   // This is used for coprocessor instructions, such as FP load/stores.
 438   //
 439   // addrmode5 := reg +/- imm8*4
 440   //
 441   // The first operand is always a Reg.  The second operand encodes the
 442   // operation in bit 8 and the immediate in bits 0-7.
 443   //
 444   // This is also used for FP load/store multiple ops. The second operand
 445   // encodes the writeback mode in bit 8 and the number of registers (or 2
 446   // times the number of registers for DPR ops) in bits 0-7. In addition,
 447   // bits 9-11 encode one of the following two sub-modes:
 448   //
 449   //    IA - Increment after
 450   //    DB - Decrement before
 451
 452   /// getAM5Opc - This function encodes the addrmode5 opc field.
 453   static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
 454     bool isSub = Opc == sub;
 455     return ((int)isSub << 8) | Offset;
 456   }
 457   static inline unsigned char getAM5Offset(unsigned AM5Opc) {
 458     return AM5Opc & 0xFF;
 459   }
 460   static inline AddrOpc getAM5Op(unsigned AM5Opc) {
 461     return ((AM5Opc >> 8) & 1) ? sub : add;
 462   }
 463
 464   /// getAM5Opc - This function encodes the addrmode5 opc field for FLDM and
 465   /// FSTM instructions.
 466   static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
 467                                    unsigned char Offset) {
 468     assert((SubMode == ia || SubMode == db) &&
 469            "Illegal addressing mode 5 sub-mode!");
 470     return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
 471   }
 472   static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
 473     return (AMSubMode)((AM5Opc >> 9) & 0x7);
 474   }
 475   static inline bool getAM5WBFlag(unsigned AM5Opc) {
 476     return ((AM5Opc >> 8) & 1);
 477   }
 478
 479   //===--------------------------------------------------------------------===//
 480   // Addressing Mode #6
 481   //===--------------------------------------------------------------------===//
 482   //
 483   // This is used for NEON load / store instructions.
 484   //
 485   // addrmode6 := reg with optional writeback
 486   //
 487   // This is stored in three operands [regaddr, regupdate, opc].  The first is
 488   // the address register.  The second register holds the value of a post-access
 489   // increment for writeback or reg0 if no writeback or if the writeback
 490   // increment is the size of the memory access.  The third operand encodes
 491   // whether there is writeback to the address register.
 492
 493   static inline unsigned getAM6Opc(bool WB = false) {
 494     return (int)WB;
 495   }
 496
 497   static inline bool getAM6WBFlag(unsigned Mode) {
 498     return Mode & 1;
 499   }
 500
 501 } // end namespace ARM_AM
 502 } // end namespace llvm
 503
 504 #endif
 505