lib/Target/ARM/ARMInstrInfo.h

   1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMINSTRUCTIONINFO_H
  15 #define ARMINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARMBaseInstrInfo.h"
  19 #include "ARMRegisterInfo.h"
  20 #include "ARMSubtarget.h"
  21 #include "ARM.h"
  22
  23 namespace llvm {
  24   class ARMSubtarget;
  25
  26 class ARMInstrInfo : public ARMBaseInstrInfo {
  27   ARMRegisterInfo RI;
  28   const ARMSubtarget &Subtarget;
  29 public:
  30   explicit ARMInstrInfo(const ARMSubtarget &STI);
  31
  32   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  33   // if there is not such an opcode.
  34   unsigned getUnindexedOpcode(unsigned Opc) const;
  35
  36   // Return true if the block does not fall through.
  37   bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
  38
  39   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  40   /// such, whenever a client has an instance of instruction info, it should
  41   /// always be able to get register info as well (through this method).
  42   ///
  43   const ARMRegisterInfo &getRegisterInfo() const { return RI; }
  44
  45   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  46                      unsigned DestReg, unsigned SubIdx,
  47                      const MachineInstr *Orig) const;
  48 };
  49
  50 }
  51
  52 #endif