Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
[llvm/avr.git] / lib / Target / ARM / Thumb1InstrInfo.h
blob646f4298e368179cc374977540bc717480e8f598
1 //===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMB1INSTRUCTIONINFO_H
15 #define THUMB1INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARM.h"
19 #include "ARMInstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
22 namespace llvm {
23 class ARMSubtarget;
25 class Thumb1InstrInfo : public ARMBaseInstrInfo {
26 Thumb1RegisterInfo RI;
27 public:
28 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const;
34 // Return true if the block does not fall through.
35 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
40 ///
41 const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
43 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI,
45 const std::vector<CalleeSavedInfo> &CSI) const;
46 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 const std::vector<CalleeSavedInfo> &CSI) const;
50 bool copyRegToReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I,
52 unsigned DestReg, unsigned SrcReg,
53 const TargetRegisterClass *DestRC,
54 const TargetRegisterClass *SrcRC) const;
55 void storeRegToStackSlot(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI,
57 unsigned SrcReg, bool isKill, int FrameIndex,
58 const TargetRegisterClass *RC) const;
60 void loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI,
62 unsigned DestReg, int FrameIndex,
63 const TargetRegisterClass *RC) const;
65 bool canFoldMemoryOperand(const MachineInstr *MI,
66 const SmallVectorImpl<unsigned> &Ops) const;
68 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
69 MachineInstr* MI,
70 const SmallVectorImpl<unsigned> &Ops,
71 int FrameIndex) const;
73 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
74 MachineInstr* MI,
75 const SmallVectorImpl<unsigned> &Ops,
76 MachineInstr* LoadMI) const {
77 return 0;
82 #endif // THUMB1INSTRUCTIONINFO_H