1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SystemZ instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // SystemZ Instruction Predicate Definitions.
16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
18 include "SystemZInstrFormats.td"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
31 def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
33 def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
34 def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
35 def SDT_BrCond : SDTypeProfile<0, 2,
36 [SDTCisVT<0, OtherVT>,
38 def SDT_SelectCC : SDTypeProfile<1, 3,
39 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
41 def SDT_Address : SDTypeProfile<1, 1,
42 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
44 //===----------------------------------------------------------------------===//
45 // SystemZ Specific Node Definitions.
46 //===----------------------------------------------------------------------===//
47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
48 [SDNPHasChain, SDNPOptInFlag]>;
49 def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
50 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
51 def SystemZcallseq_start :
52 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
53 [SDNPHasChain, SDNPOutFlag]>;
54 def SystemZcallseq_end :
55 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
58 def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
59 def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
60 [SDNPHasChain, SDNPInFlag]>;
61 def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
65 include "SystemZOperands.td"
67 //===----------------------------------------------------------------------===//
70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
72 [(SystemZcallseq_start timm:$amt)]>;
73 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
75 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
77 let usesCustomDAGSchedInserter = 1 in {
78 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
81 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
82 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
85 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
89 //===----------------------------------------------------------------------===//
90 // Control Flow Instructions...
93 // FIXME: Provide proper encoding!
94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
95 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
98 let isBranch = 1, isTerminator = 1 in {
99 let isBarrier = 1 in {
100 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
102 let isIndirectBranch = 1 in
103 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
106 let Uses = [PSW] in {
107 def JO : Pseudo<(outs), (ins brtarget:$dst),
109 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
110 def JH : Pseudo<(outs), (ins brtarget:$dst),
112 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
113 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
115 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
116 def JL : Pseudo<(outs), (ins brtarget:$dst),
118 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
119 def JNHE: Pseudo<(outs), (ins brtarget:$dst),
121 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
122 def JLH : Pseudo<(outs), (ins brtarget:$dst),
124 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
125 def JNE : Pseudo<(outs), (ins brtarget:$dst),
127 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
128 def JE : Pseudo<(outs), (ins brtarget:$dst),
130 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
131 def JNLH: Pseudo<(outs), (ins brtarget:$dst),
133 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
134 def JHE : Pseudo<(outs), (ins brtarget:$dst),
136 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
137 def JNL : Pseudo<(outs), (ins brtarget:$dst),
139 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
140 def JLE : Pseudo<(outs), (ins brtarget:$dst),
142 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
143 def JNH : Pseudo<(outs), (ins brtarget:$dst),
145 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
146 def JNO : Pseudo<(outs), (ins brtarget:$dst),
148 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
152 //===----------------------------------------------------------------------===//
153 // Call Instructions...
157 // All calls clobber the non-callee saved registers. Uses for argument
158 // registers are added manually.
159 let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
160 F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
161 def CALLi : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
162 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
163 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
164 "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
167 //===----------------------------------------------------------------------===//
168 // Miscellaneous Instructions.
171 let isReMaterializable = 1 in
172 // FIXME: Provide imm12 variant
173 // FIXME: Address should be halfword aligned...
174 def LA64r : RXI<0x47,
175 (outs GR64:$dst), (ins laaddr:$src),
177 [(set GR64:$dst, laaddr:$src)]>;
178 def LA64rm : RXYI<0x71E3,
179 (outs GR64:$dst), (ins i64imm:$src),
180 "larl\t{$dst, $src}",
182 (SystemZpcrelwrapper tglobaladdr:$src))]>;
184 let neverHasSideEffects = 1 in
185 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
187 //===----------------------------------------------------------------------===//
190 let neverHasSideEffects = 1 in {
191 def MOV32rr : RRI<0x18,
192 (outs GR32:$dst), (ins GR32:$src),
195 def MOV64rr : RREI<0xB904,
196 (outs GR64:$dst), (ins GR64:$src),
199 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
201 "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
202 "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
204 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
206 "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
207 "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
211 def MOVSX64rr32 : RREI<0xB914,
212 (outs GR64:$dst), (ins GR32:$src),
213 "lgfr\t{$dst, $src}",
214 [(set GR64:$dst, (sext GR32:$src))]>;
215 def MOVZX64rr32 : RREI<0xB916,
216 (outs GR64:$dst), (ins GR32:$src),
217 "llgfr\t{$dst, $src}",
218 [(set GR64:$dst, (zext GR32:$src))]>;
220 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
221 def MOV32ri16 : RII<0x8A7,
222 (outs GR32:$dst), (ins s16imm:$src),
224 [(set GR32:$dst, immSExt16:$src)]>;
225 def MOV64ri16 : RII<0x9A7,
226 (outs GR64:$dst), (ins s16imm64:$src),
227 "lghi\t{$dst, $src}",
228 [(set GR64:$dst, immSExt16:$src)]>;
230 def MOV64rill16 : RII<0xFA5,
231 (outs GR64:$dst), (ins i64imm:$src),
232 "llill\t{$dst, $src}",
233 [(set GR64:$dst, i64ll16:$src)]>;
234 def MOV64rilh16 : RII<0xEA5,
235 (outs GR64:$dst), (ins i64imm:$src),
236 "llilh\t{$dst, $src}",
237 [(set GR64:$dst, i64lh16:$src)]>;
238 def MOV64rihl16 : RII<0xDA5,
239 (outs GR64:$dst), (ins i64imm:$src),
240 "llihl\t{$dst, $src}",
241 [(set GR64:$dst, i64hl16:$src)]>;
242 def MOV64rihh16 : RII<0xCA5,
243 (outs GR64:$dst), (ins i64imm:$src),
244 "llihh\t{$dst, $src}",
245 [(set GR64:$dst, i64hh16:$src)]>;
247 def MOV64ri32 : RILI<0x1C0,
248 (outs GR64:$dst), (ins s32imm64:$src),
249 "lgfi\t{$dst, $src}",
250 [(set GR64:$dst, immSExt32:$src)]>;
251 def MOV64rilo32 : RILI<0xFC0,
252 (outs GR64:$dst), (ins i64imm:$src),
253 "llilf\t{$dst, $src}",
254 [(set GR64:$dst, i64lo32:$src)]>;
255 def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src),
256 "llihf\t{$dst, $src}",
257 [(set GR64:$dst, i64hi32:$src)]>;
260 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
261 def MOV32rm : RXI<0x58,
262 (outs GR32:$dst), (ins rriaddr12:$src),
264 [(set GR32:$dst, (load rriaddr12:$src))]>;
265 def MOV32rmy : RXYI<0x58E3,
266 (outs GR32:$dst), (ins rriaddr:$src),
268 [(set GR32:$dst, (load rriaddr:$src))]>;
269 def MOV64rm : RXYI<0x04E3,
270 (outs GR64:$dst), (ins rriaddr:$src),
272 [(set GR64:$dst, (load rriaddr:$src))]>;
273 def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
275 "\tl\t${dst:subreg_odd}, $src\n"
276 "\tl\t${dst:subreg_even}, 4+$src",
277 [(set GR64P:$dst, (load rriaddr12:$src))]>;
278 def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
280 "\tly\t${dst:subreg_odd}, $src\n"
281 "\tly\t${dst:subreg_even}, 4+$src",
282 [(set GR64P:$dst, (load rriaddr:$src))]>;
283 def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
285 "\tlg\t${dst:subreg_odd}, $src\n"
286 "\tlg\t${dst:subreg_even}, 8+$src",
287 [(set GR128:$dst, (load rriaddr:$src))]>;
290 def MOV32mr : RXI<0x50,
291 (outs), (ins rriaddr12:$dst, GR32:$src),
293 [(store GR32:$src, rriaddr12:$dst)]>;
294 def MOV32mry : RXYI<0x50E3,
295 (outs), (ins rriaddr:$dst, GR32:$src),
297 [(store GR32:$src, rriaddr:$dst)]>;
298 def MOV64mr : RXYI<0x24E3,
299 (outs), (ins rriaddr:$dst, GR64:$src),
301 [(store GR64:$src, rriaddr:$dst)]>;
302 def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
304 "\tst\t${src:subreg_odd}, $dst\n"
305 "\tst\t${src:subreg_even}, 4+$dst",
306 [(store GR64P:$src, rriaddr12:$dst)]>;
307 def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
309 "\tsty\t${src:subreg_odd}, $dst\n"
310 "\tsty\t${src:subreg_even}, 4+$dst",
311 [(store GR64P:$src, rriaddr:$dst)]>;
312 def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
314 "\tstg\t${src:subreg_odd}, $dst\n"
315 "\tstg\t${src:subreg_even}, 8+$dst",
316 [(store GR128:$src, rriaddr:$dst)]>;
318 def MOV8mi : SII<0x92,
319 (outs), (ins riaddr12:$dst, i32i8imm:$src),
321 [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
322 def MOV8miy : SIYI<0x52EB,
323 (outs), (ins riaddr:$dst, i32i8imm:$src),
324 "mviy\t{$dst, $src}",
325 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
327 def MOV16mi : SILI<0xE544,
328 (outs), (ins riaddr12:$dst, s16imm:$src),
329 "mvhhi\t{$dst, $src}",
330 [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
332 def MOV32mi16 : SILI<0xE54C,
333 (outs), (ins riaddr12:$dst, s32imm:$src),
334 "mvhi\t{$dst, $src}",
335 [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
337 def MOV64mi16 : SILI<0xE548,
338 (outs), (ins riaddr12:$dst, s32imm64:$src),
339 "mvghi\t{$dst, $src}",
340 [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
344 def MOVSX32rr8 : RREI<0xB926,
345 (outs GR32:$dst), (ins GR32:$src),
347 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
348 def MOVSX64rr8 : RREI<0xB906,
349 (outs GR64:$dst), (ins GR64:$src),
350 "lgbr\t{$dst, $src}",
351 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
352 def MOVSX32rr16 : RREI<0xB927,
353 (outs GR32:$dst), (ins GR32:$src),
355 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
356 def MOVSX64rr16 : RREI<0xB907,
357 (outs GR64:$dst), (ins GR64:$src),
358 "lghr\t{$dst, $src}",
359 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
362 def MOVSX32rm8 : RXYI<0x76E3,
363 (outs GR32:$dst), (ins rriaddr:$src),
365 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
366 def MOVSX32rm16 : RXI<0x48,
367 (outs GR32:$dst), (ins rriaddr12:$src),
369 [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
370 def MOVSX32rm16y : RXYI<0x78E3,
371 (outs GR32:$dst), (ins rriaddr:$src),
373 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
374 def MOVSX64rm8 : RXYI<0x77E3,
375 (outs GR64:$dst), (ins rriaddr:$src),
377 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
378 def MOVSX64rm16 : RXYI<0x15E3,
379 (outs GR64:$dst), (ins rriaddr:$src),
381 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
382 def MOVSX64rm32 : RXYI<0x14E3,
383 (outs GR64:$dst), (ins rriaddr:$src),
385 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
387 def MOVZX32rm8 : RXYI<0x94E3,
388 (outs GR32:$dst), (ins rriaddr:$src),
390 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
391 def MOVZX32rm16 : RXYI<0x95E3,
392 (outs GR32:$dst), (ins rriaddr:$src),
394 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
395 def MOVZX64rm8 : RXYI<0x90E3,
396 (outs GR64:$dst), (ins rriaddr:$src),
397 "llgc\t{$dst, $src}",
398 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
399 def MOVZX64rm16 : RXYI<0x91E3,
400 (outs GR64:$dst), (ins rriaddr:$src),
401 "llgh\t{$dst, $src}",
402 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
403 def MOVZX64rm32 : RXYI<0x16E3,
404 (outs GR64:$dst), (ins rriaddr:$src),
405 "llgf\t{$dst, $src}",
406 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
409 def MOV32m8r : RXI<0x42,
410 (outs), (ins rriaddr12:$dst, GR32:$src),
412 [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
414 def MOV32m8ry : RXYI<0x72E3,
415 (outs), (ins rriaddr:$dst, GR32:$src),
416 "stcy\t{$src, $dst}",
417 [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
419 def MOV32m16r : RXI<0x40,
420 (outs), (ins rriaddr12:$dst, GR32:$src),
422 [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
424 def MOV32m16ry : RXYI<0x70E3,
425 (outs), (ins rriaddr:$dst, GR32:$src),
426 "sthy\t{$src, $dst}",
427 [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
429 def MOV64m8r : RXI<0x42,
430 (outs), (ins rriaddr12:$dst, GR64:$src),
432 [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
434 def MOV64m8ry : RXYI<0x72E3,
435 (outs), (ins rriaddr:$dst, GR64:$src),
436 "stcy\t{$src, $dst}",
437 [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
439 def MOV64m16r : RXI<0x40,
440 (outs), (ins rriaddr12:$dst, GR64:$src),
442 [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
444 def MOV64m16ry : RXYI<0x70E3,
445 (outs), (ins rriaddr:$dst, GR64:$src),
446 "sthy\t{$src, $dst}",
447 [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
449 def MOV64m32r : RXI<0x50,
450 (outs), (ins rriaddr12:$dst, GR64:$src),
452 [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
454 def MOV64m32ry : RXYI<0x50E3,
455 (outs), (ins rriaddr:$dst, GR64:$src),
457 [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
459 // multiple regs moves
460 // FIXME: should we use multiple arg nodes?
461 def MOV32mrm : RSYI<0x90EB,
462 (outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
463 "stmy\t{$from, $to, $dst}",
465 def MOV64mrm : RSYI<0x24EB,
466 (outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
467 "stmg\t{$from, $to, $dst}",
469 def MOV32rmm : RSYI<0x90EB,
470 (outs GR32:$from, GR32:$to), (ins riaddr:$dst),
471 "lmy\t{$from, $to, $dst}",
473 def MOV64rmm : RSYI<0x04EB,
474 (outs GR64:$from, GR64:$to), (ins riaddr:$dst),
475 "lmg\t{$from, $to, $dst}",
478 let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
479 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
480 "lhi\t${dst:subreg_even}, 0",
482 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
483 "lghi\t${dst:subreg_even}, 0",
488 def BSWAP32rr : RREI<0xB91F,
489 (outs GR32:$dst), (ins GR32:$src),
490 "lrvr\t{$dst, $src}",
491 [(set GR32:$dst, (bswap GR32:$src))]>;
492 def BSWAP64rr : RREI<0xB90F,
493 (outs GR64:$dst), (ins GR64:$src),
494 "lrvgr\t{$dst, $src}",
495 [(set GR64:$dst, (bswap GR64:$src))]>;
497 // FIXME: this is invalid pattern for big-endian
498 //def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src),
499 // "lrvh\t{$dst, $src}",
500 // [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
501 def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src),
503 [(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
504 def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src),
505 "lrvg\t{$dst, $src}",
506 [(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
508 //===----------------------------------------------------------------------===//
509 // Arithmetic Instructions
511 let Defs = [PSW] in {
512 def NEG32rr : RRI<0x13,
513 (outs GR32:$dst), (ins GR32:$src),
515 [(set GR32:$dst, (ineg GR32:$src)),
517 def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src),
518 "lcgr\t{$dst, $src}",
519 [(set GR64:$dst, (ineg GR64:$src)),
521 def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src),
522 "lcgfr\t{$dst, $src}",
523 [(set GR64:$dst, (ineg (sext GR32:$src))),
527 let isTwoAddress = 1 in {
529 let Defs = [PSW] in {
531 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
532 def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
534 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
536 def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
537 "agr\t{$dst, $src2}",
538 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
542 def ADD32ri16 : RII<0xA7A,
543 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
544 "ahi\t{$dst, $src2}",
545 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
547 def ADD32ri : RILI<0xC29,
548 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
549 "afi\t{$dst, $src2}",
550 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
552 def ADD64ri16 : RILI<0xA7B,
553 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
554 "aghi\t{$dst, $src2}",
555 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
557 def ADD64ri32 : RILI<0xC28,
558 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
559 "agfi\t{$dst, $src2}",
560 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
563 let isCommutable = 1 in { // X = ADC Y, Z == X = ADC Z, Y
564 def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
565 "alr\t{$dst, $src2}",
566 [(set GR32:$dst, (addc GR32:$src1, GR32:$src2))]>;
567 def ADC64rr : RREI<0xB90A, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
568 "algr\t{$dst, $src2}",
569 [(set GR64:$dst, (addc GR64:$src1, GR64:$src2))]>;
572 def ADC32ri : RILI<0xC2B,
573 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
574 "alfi\t{$dst, $src2}",
575 [(set GR32:$dst, (addc GR32:$src1, imm:$src2))]>;
576 def ADC64ri32 : RILI<0xC2A,
577 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
578 "algfi\t{$dst, $src2}",
579 [(set GR64:$dst, (addc GR64:$src1, immSExt32:$src2))]>;
581 let Uses = [PSW] in {
582 def ADDE32rr : RREI<0xB998, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
583 "alcr\t{$dst, $src2}",
584 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2)),
586 def ADDE64rr : RREI<0xB988, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
587 "alcgr\t{$dst, $src2}",
588 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
592 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
593 def AND32rr : RRI<0x14,
594 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
596 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
597 def AND64rr : RREI<0xB980,
598 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
599 "ngr\t{$dst, $src2}",
600 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
603 def AND32rill16 : RII<0xA57,
604 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
605 "nill\t{$dst, $src2}",
606 [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
607 def AND64rill16 : RII<0xA57,
608 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
609 "nill\t{$dst, $src2}",
610 [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
612 def AND32rilh16 : RII<0xA56,
613 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
614 "nilh\t{$dst, $src2}",
615 [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
616 def AND64rilh16 : RII<0xA56,
617 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
618 "nilh\t{$dst, $src2}",
619 [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
621 def AND64rihl16 : RII<0xA55,
622 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
623 "nihl\t{$dst, $src2}",
624 [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
625 def AND64rihh16 : RII<0xA54,
626 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
627 "nihh\t{$dst, $src2}",
628 [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
630 def AND32ri : RILI<0xC0B,
631 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
632 "nilf\t{$dst, $src2}",
633 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
634 def AND64rilo32 : RILI<0xC0B,
635 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
636 "nilf\t{$dst, $src2}",
637 [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
638 def AND64rihi32 : RILI<0xC0A,
639 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
640 "nihf\t{$dst, $src2}",
641 [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
643 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
644 def OR32rr : RRI<0x16,
645 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
647 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
648 def OR64rr : RREI<0xB981,
649 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
650 "ogr\t{$dst, $src2}",
651 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
654 def OR32ri16 : RII<0xA5B,
655 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
656 "oill\t{$dst, $src2}",
657 [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
658 def OR32ri16h : RII<0xA5A,
659 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
660 "oilh\t{$dst, $src2}",
661 [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
662 def OR32ri : RILI<0xC0D,
663 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
664 "oilf\t{$dst, $src2}",
665 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
667 def OR64rill16 : RII<0xA5B,
668 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
669 "oill\t{$dst, $src2}",
670 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
671 def OR64rilh16 : RII<0xA5A,
672 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
673 "oilh\t{$dst, $src2}",
674 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
675 def OR64rihl16 : RII<0xA59,
676 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
677 "oihl\t{$dst, $src2}",
678 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
679 def OR64rihh16 : RII<0xA58,
680 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
681 "oihh\t{$dst, $src2}",
682 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
684 def OR64rilo32 : RILI<0xC0D,
685 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
686 "oilf\t{$dst, $src2}",
687 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
688 def OR64rihi32 : RILI<0xC0C,
689 (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
690 "oihf\t{$dst, $src2}",
691 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
693 def SUB32rr : RRI<0x1B,
694 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
696 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
697 def SUB64rr : RREI<0xB909,
698 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
699 "sgr\t{$dst, $src2}",
700 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
702 def SBC32rr : RRI<0x1F,
703 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
704 "slr\t{$dst, $src2}",
705 [(set GR32:$dst, (subc GR32:$src1, GR32:$src2))]>;
706 def SBC64rr : RREI<0xB90B,
707 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
708 "slgr\t{$dst, $src2}",
709 [(set GR64:$dst, (subc GR64:$src1, GR64:$src2))]>;
711 def SBC32ri : RILI<0xC25,
712 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
713 "sllfi\t{$dst, $src2}",
714 [(set GR32:$dst, (subc GR32:$src1, imm:$src2))]>;
715 def SBC64ri32 : RILI<0xC24,
716 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
717 "slgfi\t{$dst, $src2}",
718 [(set GR64:$dst, (subc GR64:$src1, immSExt32:$src2))]>;
720 let Uses = [PSW] in {
721 def SUBE32rr : RREI<0xB999, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
722 "slcr\t{$dst, $src2}",
723 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2)),
725 def SUBE64rr : RREI<0xB989, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
726 "slcgr\t{$dst, $src2}",
727 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2)),
731 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
732 def XOR32rr : RRI<0x17,
733 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
735 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
736 def XOR64rr : RREI<0xB982,
737 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
738 "xgr\t{$dst, $src2}",
739 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
742 def XOR32ri : RILI<0xC07,
743 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
744 "xilf\t{$dst, $src2}",
745 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
749 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
750 def MUL32rr : RREI<0xB252,
751 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
752 "msr\t{$dst, $src2}",
753 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
754 def MUL64rr : RREI<0xB90C,
755 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
756 "msgr\t{$dst, $src2}",
757 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
760 def MUL64rrP : RRI<0x1C,
761 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
764 def UMUL64rrP : RREI<0xB996,
765 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
766 "mlr\t{$dst, $src2}",
768 def UMUL128rrP : RREI<0xB986,
769 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
770 "mlgr\t{$dst, $src2}",
773 def MUL32ri16 : RII<0xA7C,
774 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
775 "mhi\t{$dst, $src2}",
776 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
777 def MUL64ri16 : RII<0xA7D,
778 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
779 "mghi\t{$dst, $src2}",
780 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
782 def MUL32ri : RILI<0xC21,
783 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
784 "msfi\t{$dst, $src2}",
785 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
787 def MUL64ri32 : RILI<0xC20,
788 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
789 "msgfi\t{$dst, $src2}",
790 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
793 def MUL32rm : RXI<0x71,
794 (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
796 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
797 def MUL32rmy : RXYI<0xE351,
798 (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
799 "msy\t{$dst, $src2}",
800 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
801 def MUL64rm : RXYI<0xE30C,
802 (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
803 "msg\t{$dst, $src2}",
804 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
806 def MULSX64rr32 : RREI<0xB91C,
807 (outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
808 "msgfr\t{$dst, $src2}",
809 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
811 def SDIVREM32r : RREI<0xB91D,
812 (outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
813 "dsgfr\t{$dst, $src2}",
815 def SDIVREM64r : RREI<0xB90D,
816 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
817 "dsgr\t{$dst, $src2}",
820 def UDIVREM32r : RREI<0xB997,
821 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
822 "dlr\t{$dst, $src2}",
824 def UDIVREM64r : RREI<0xB987,
825 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
826 "dlgr\t{$dst, $src2}",
829 def SDIVREM32m : RXYI<0xE31D,
830 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
831 "dsgf\t{$dst, $src2}",
833 def SDIVREM64m : RXYI<0xE30D,
834 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
835 "dsg\t{$dst, $src2}",
838 def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
841 def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
842 "dlg\t{$dst, $src2}",
845 } // isTwoAddress = 1
847 //===----------------------------------------------------------------------===//
850 let isTwoAddress = 1 in
851 def SRL32rri : RSI<0x88,
852 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
854 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
855 def SRL64rri : RSYI<0xEB0C,
856 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
857 "srlg\t{$dst, $src, $amt}",
858 [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
860 let isTwoAddress = 1 in
861 def SHL32rri : RSI<0x89,
862 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
864 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
865 def SHL64rri : RSYI<0xEB0D,
866 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
867 "sllg\t{$dst, $src, $amt}",
868 [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
870 let Defs = [PSW] in {
871 let isTwoAddress = 1 in
872 def SRA32rri : RSI<0x8A,
873 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
875 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
878 def SRA64rri : RSYI<0xEB0A,
879 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
880 "srag\t{$dst, $src, $amt}",
881 [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
885 def ROTL32rri : RSYI<0xEB1D,
886 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
887 "rll\t{$dst, $src, $amt}",
888 [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
889 def ROTL64rri : RSYI<0xEB1C,
890 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
891 "rllg\t{$dst, $src, $amt}",
892 [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
894 //===----------------------------------------------------------------------===//
895 // Test instructions (like AND but do not produce any result)
897 // Integer comparisons
898 let Defs = [PSW] in {
899 def CMP32rr : RRI<0x19,
900 (outs), (ins GR32:$src1, GR32:$src2),
902 [(SystemZcmp GR32:$src1, GR32:$src2),
904 def CMP64rr : RREI<0xB920,
905 (outs), (ins GR64:$src1, GR64:$src2),
907 [(SystemZcmp GR64:$src1, GR64:$src2),
910 def CMP32ri : RILI<0xC2D,
911 (outs), (ins GR32:$src1, s32imm:$src2),
913 [(SystemZcmp GR32:$src1, imm:$src2),
915 def CMP64ri32 : RILI<0xC2C,
916 (outs), (ins GR64:$src1, s32imm64:$src2),
917 "cgfi\t$src1, $src2",
918 [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
921 def CMP32rm : RXI<0x59,
922 (outs), (ins GR32:$src1, rriaddr12:$src2),
924 [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
926 def CMP32rmy : RXYI<0xE359,
927 (outs), (ins GR32:$src1, rriaddr:$src2),
929 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
931 def CMP64rm : RXYI<0xE320,
932 (outs), (ins GR64:$src1, rriaddr:$src2),
934 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
937 def UCMP32rr : RRI<0x15,
938 (outs), (ins GR32:$src1, GR32:$src2),
940 [(SystemZucmp GR32:$src1, GR32:$src2),
942 def UCMP64rr : RREI<0xB921,
943 (outs), (ins GR64:$src1, GR64:$src2),
944 "clgr\t$src1, $src2",
945 [(SystemZucmp GR64:$src1, GR64:$src2),
948 def UCMP32ri : RILI<0xC2F,
949 (outs), (ins GR32:$src1, i32imm:$src2),
950 "clfi\t$src1, $src2",
951 [(SystemZucmp GR32:$src1, imm:$src2),
953 def UCMP64ri32 : RILI<0xC2E,
954 (outs), (ins GR64:$src1, i64i32imm:$src2),
955 "clgfi\t$src1, $src2",
956 [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
959 def UCMP32rm : RXI<0x55,
960 (outs), (ins GR32:$src1, rriaddr12:$src2),
962 [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
964 def UCMP32rmy : RXYI<0xE355,
965 (outs), (ins GR32:$src1, rriaddr:$src2),
967 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
969 def UCMP64rm : RXYI<0xE351,
970 (outs), (ins GR64:$src1, rriaddr:$src2),
972 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
975 def CMPSX64rr32 : RREI<0xB930,
976 (outs), (ins GR64:$src1, GR32:$src2),
977 "cgfr\t$src1, $src2",
978 [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
980 def UCMPZX64rr32 : RREI<0xB931,
981 (outs), (ins GR64:$src1, GR32:$src2),
982 "clgfr\t$src1, $src2",
983 [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
986 def CMPSX64rm32 : RXYI<0xE330,
987 (outs), (ins GR64:$src1, rriaddr:$src2),
989 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
991 def UCMPZX64rm32 : RXYI<0xE331,
992 (outs), (ins GR64:$src1, rriaddr:$src2),
993 "clgf\t$src1, $src2",
994 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
997 // FIXME: Add other crazy ucmp forms
1001 //===----------------------------------------------------------------------===//
1002 // Other crazy stuff
1003 let Defs = [PSW] in {
1004 def FLOGR64 : RREI<0xB983,
1005 (outs GR128:$dst), (ins GR64:$src),
1006 "flogr\t{$dst, $src}",
1010 //===----------------------------------------------------------------------===//
1011 // Non-Instruction Patterns.
1012 //===----------------------------------------------------------------------===//
1014 // ConstPools, JumpTables
1015 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
1016 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
1019 def : Pat<(i64 (anyext GR32:$src)),
1020 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1023 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
1024 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1030 // FIXME: use add/sub tricks with 32678/-32768
1032 // Arbitrary immediate support.
1033 def : Pat<(i32 imm:$src),
1034 (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
1036 // Implement in terms of LLIHF/OILF.
1037 def : Pat<(i64 imm:$imm),
1038 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
1041 def : Pat<(i32 (trunc GR64:$src)),
1042 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
1044 // sext_inreg patterns
1045 def : Pat<(sext_inreg GR64:$src, i32),
1046 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
1049 def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>;
1050 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
1051 def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
1052 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
1053 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
1056 def : Pat<(mulhs GR32:$src1, GR32:$src2),
1057 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1058 GR32:$src1, subreg_odd32),
1062 def : Pat<(mulhu GR32:$src1, GR32:$src2),
1063 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1064 GR32:$src1, subreg_odd32),
1067 def : Pat<(mulhu GR64:$src1, GR64:$src2),
1068 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1069 GR64:$src1, subreg_odd),
1073 def : Pat<(ctlz GR64:$src),
1074 (EXTRACT_SUBREG (FLOGR64 GR64:$src), subreg_even)>;