lib/Target/X86/X86CodeEmitter.cpp

   1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the X86 machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "x86-emitter"
  16 #include "X86InstrInfo.h"
  17 #include "X86JITInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "X86TargetMachine.h"
  20 #include "X86Relocations.h"
  21 #include "X86.h"
  22 #include "llvm/PassManager.h"
  23 #include "llvm/CodeGen/MachineCodeEmitter.h"
  24 #include "llvm/CodeGen/JITCodeEmitter.h"
  25 #include "llvm/CodeGen/ObjectCodeEmitter.h"
  26 #include "llvm/CodeGen/MachineFunctionPass.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineModuleInfo.h"
  29 #include "llvm/CodeGen/Passes.h"
  30 #include "llvm/Function.h"
  31 #include "llvm/ADT/Statistic.h"
  32 #include "llvm/Support/Compiler.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/raw_ostream.h"
  36 #include "llvm/Target/TargetOptions.h"
  37 using namespace llvm;
  38
  39 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  40
  41 namespace {
  42 template<class CodeEmitter>
  43   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
  44     const X86InstrInfo  *II;
  45     const TargetData    *TD;
  46     X86TargetMachine    &TM;
  47     CodeEmitter         &MCE;
  48     intptr_t PICBaseOffset;
  49     bool Is64BitMode;
  50     bool IsPIC;
  51   public:
  52     static char ID;
  53     explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
  54       : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
  55       MCE(mce), PICBaseOffset(0), Is64BitMode(false),
  56       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  57     Emitter(X86TargetMachine &tm, CodeEmitter &mce,
  58             const X86InstrInfo &ii, const TargetData &td, bool is64)
  59       : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
  60       MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
  61       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  62
  63     bool runOnMachineFunction(MachineFunction &MF);
  64
  65     virtual const char *getPassName() const {
  66       return "X86 Machine Code Emitter";
  67     }
  68
  69     void emitInstruction(const MachineInstr &MI,
  70                          const TargetInstrDesc *Desc);
  71
  72     void getAnalysisUsage(AnalysisUsage &AU) const {
  73       AU.setPreservesAll();
  74       AU.addRequired<MachineModuleInfo>();
  75       MachineFunctionPass::getAnalysisUsage(AU);
  76     }
  77
  78   private:
  79     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
  80     void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
  81                            intptr_t Disp = 0, intptr_t PCAdj = 0,
  82                            bool NeedStub = false, bool Indirect = false);
  83     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
  84     void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
  85                               intptr_t PCAdj = 0);
  86     void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
  87                               intptr_t PCAdj = 0);
  88
  89     void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
  90                                intptr_t PCAdj = 0);
  91
  92     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
  93     void emitRegModRMByte(unsigned RegOpcodeField);
  94     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
  95     void emitConstant(uint64_t Val, unsigned Size);
  96
  97     void emitMemModRMByte(const MachineInstr &MI,
  98                           unsigned Op, unsigned RegOpcodeField,
  99                           intptr_t PCAdj = 0);
 100
 101     unsigned getX86RegNum(unsigned RegNo) const;
 102   };
 103
 104 template<class CodeEmitter>
 105   char Emitter<CodeEmitter>::ID = 0;
 106 }
 107
 108 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 109 /// to the specified templated MachineCodeEmitter object.
 110
 111 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
 112                                              MachineCodeEmitter &MCE) {
 113   return new Emitter<MachineCodeEmitter>(TM, MCE);
 114 }
 115 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
 116                                                 JITCodeEmitter &JCE) {
 117   return new Emitter<JITCodeEmitter>(TM, JCE);
 118 }
 119 FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
 120                                                    ObjectCodeEmitter &OCE) {
 121   return new Emitter<ObjectCodeEmitter>(TM, OCE);
 122 }
 123
 124 template<class CodeEmitter>
 125 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
 126
 127   MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
 128
 129   II = TM.getInstrInfo();
 130   TD = TM.getTargetData();
 131   Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
 132   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
 133
 134   do {
 135     DEBUG(errs() << "JITTing function '"
 136           << MF.getFunction()->getName() << "'\n");
 137     MCE.startFunction(MF);
 138     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 139          MBB != E; ++MBB) {
 140       MCE.StartMachineBasicBlock(MBB);
 141       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 142            I != E; ++I) {
 143         const TargetInstrDesc &Desc = I->getDesc();
 144         emitInstruction(*I, &Desc);
 145         // MOVPC32r is basically a call plus a pop instruction.
 146         if (Desc.getOpcode() == X86::MOVPC32r)
 147           emitInstruction(*I, &II->get(X86::POP32r));
 148         NumEmitted++;  // Keep track of the # of mi's emitted
 149       }
 150     }
 151   } while (MCE.finishFunction(MF));
 152
 153   return false;
 154 }
 155
 156 /// emitPCRelativeBlockAddress - This method keeps track of the information
 157 /// necessary to resolve the address of this block later and emits a dummy
 158 /// value.
 159 ///
 160 template<class CodeEmitter>
 161 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
 162   // Remember where this reference was and where it is to so we can
 163   // deal with it later.
 164   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 165                                              X86::reloc_pcrel_word, MBB));
 166   MCE.emitWordLE(0);
 167 }
 168
 169 /// emitGlobalAddress - Emit the specified address to the code stream assuming
 170 /// this is part of a "take the address of a global" instruction.
 171 ///
 172 template<class CodeEmitter>
 173 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 174                                 intptr_t Disp /* = 0 */,
 175                                 intptr_t PCAdj /* = 0 */,
 176                                 bool NeedStub /* = false */,
 177                                 bool Indirect /* = false */) {
 178   intptr_t RelocCST = 0;
 179   if (Reloc == X86::reloc_picrel_word)
 180     RelocCST = PICBaseOffset;
 181   else if (Reloc == X86::reloc_pcrel_word)
 182     RelocCST = PCAdj;
 183   MachineRelocation MR = Indirect
 184     ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
 185                                            GV, RelocCST, NeedStub)
 186     : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
 187                                GV, RelocCST, NeedStub);
 188   MCE.addRelocation(MR);
 189   // The relocated value will be added to the displacement
 190   if (Reloc == X86::reloc_absolute_dword)
 191     MCE.emitDWordLE(Disp);
 192   else
 193     MCE.emitWordLE((int32_t)Disp);
 194 }
 195
 196 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 197 /// be emitted to the current location in the function, and allow it to be PC
 198 /// relative.
 199 template<class CodeEmitter>
 200 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
 201                                                      unsigned Reloc) {
 202   intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
 203   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 204                                                  Reloc, ES, RelocCST));
 205   if (Reloc == X86::reloc_absolute_dword)
 206     MCE.emitDWordLE(0);
 207   else
 208     MCE.emitWordLE(0);
 209 }
 210
 211 /// emitConstPoolAddress - Arrange for the address of an constant pool
 212 /// to be emitted to the current location in the function, and allow it to be PC
 213 /// relative.
 214 template<class CodeEmitter>
 215 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
 216                                    intptr_t Disp /* = 0 */,
 217                                    intptr_t PCAdj /* = 0 */) {
 218   intptr_t RelocCST = 0;
 219   if (Reloc == X86::reloc_picrel_word)
 220     RelocCST = PICBaseOffset;
 221   else if (Reloc == X86::reloc_pcrel_word)
 222     RelocCST = PCAdj;
 223   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 224                                                     Reloc, CPI, RelocCST));
 225   // The relocated value will be added to the displacement
 226   if (Reloc == X86::reloc_absolute_dword)
 227     MCE.emitDWordLE(Disp);
 228   else
 229     MCE.emitWordLE((int32_t)Disp);
 230 }
 231
 232 /// emitJumpTableAddress - Arrange for the address of a jump table to
 233 /// be emitted to the current location in the function, and allow it to be PC
 234 /// relative.
 235 template<class CodeEmitter>
 236 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
 237                                    intptr_t PCAdj /* = 0 */) {
 238   intptr_t RelocCST = 0;
 239   if (Reloc == X86::reloc_picrel_word)
 240     RelocCST = PICBaseOffset;
 241   else if (Reloc == X86::reloc_pcrel_word)
 242     RelocCST = PCAdj;
 243   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 244                                                     Reloc, JTI, RelocCST));
 245   // The relocated value will be added to the displacement
 246   if (Reloc == X86::reloc_absolute_dword)
 247     MCE.emitDWordLE(0);
 248   else
 249     MCE.emitWordLE(0);
 250 }
 251
 252 template<class CodeEmitter>
 253 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
 254   return II->getRegisterInfo().getX86RegNum(RegNo);
 255 }
 256
 257 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
 258                                       unsigned RM) {
 259   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
 260   return RM | (RegOpcode << 3) | (Mod << 6);
 261 }
 262
 263 template<class CodeEmitter>
 264 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
 265                                             unsigned RegOpcodeFld){
 266   MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
 267 }
 268
 269 template<class CodeEmitter>
 270 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
 271   MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
 272 }
 273
 274 template<class CodeEmitter>
 275 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
 276                                        unsigned Index,
 277                                        unsigned Base) {
 278   // SIB byte is in the same format as the ModRMByte...
 279   MCE.emitByte(ModRMByte(SS, Index, Base));
 280 }
 281
 282 template<class CodeEmitter>
 283 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
 284   // Output the constant in little endian byte order...
 285   for (unsigned i = 0; i != Size; ++i) {
 286     MCE.emitByte(Val & 255);
 287     Val >>= 8;
 288   }
 289 }
 290
 291 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
 292 /// sign-extended field.
 293 static bool isDisp8(int Value) {
 294   return Value == (signed char)Value;
 295 }
 296
 297 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
 298                               const TargetMachine &TM) {
 299   // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
 300   // mechanism as 32-bit mode.
 301   if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
 302       !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
 303     return false;
 304
 305   // Return true if this is a reference to a stub containing the address of the
 306   // global, not the global itself.
 307   return isGlobalStubReference(GVOp.getTargetFlags());
 308 }
 309
 310 template<class CodeEmitter>
 311 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
 312                                                  int DispVal, intptr_t PCAdj) {
 313   // If this is a simple integer displacement that doesn't require a relocation,
 314   // emit it now.
 315   if (!RelocOp) {
 316     emitConstant(DispVal, 4);
 317     return;
 318   }
 319
 320   // Otherwise, this is something that requires a relocation.  Emit it as such
 321   // now.
 322   if (RelocOp->isGlobal()) {
 323     // In 64-bit static small code model, we could potentially emit absolute.
 324     // But it's probably not beneficial.
 325     //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
 326     //  89 04 25 00 00 00 00  mov    %eax,0x0      # Absolute
 327     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 328       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 329     bool NeedStub = isa<Function>(RelocOp->getGlobal());
 330     bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
 331     emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
 332                       PCAdj, NeedStub, Indirect);
 333   } else if (RelocOp->isCPI()) {
 334     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
 335     emitConstPoolAddress(RelocOp->getIndex(), rt,
 336                          RelocOp->getOffset(), PCAdj);
 337   } else if (RelocOp->isJTI()) {
 338     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
 339     emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
 340   } else {
 341     llvm_unreachable("Unknown value to relocate!");
 342   }
 343 }
 344
 345 template<class CodeEmitter>
 346 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
 347                                unsigned Op, unsigned RegOpcodeField,
 348                                intptr_t PCAdj) {
 349   const MachineOperand &Op3 = MI.getOperand(Op+3);
 350   int DispVal = 0;
 351   const MachineOperand *DispForReloc = 0;
 352
 353   // Figure out what sort of displacement we have to handle here.
 354   if (Op3.isGlobal()) {
 355     DispForReloc = &Op3;
 356   } else if (Op3.isCPI()) {
 357     if (Is64BitMode || IsPIC) {
 358       DispForReloc = &Op3;
 359     } else {
 360       DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
 361       DispVal += Op3.getOffset();
 362     }
 363   } else if (Op3.isJTI()) {
 364     if (Is64BitMode || IsPIC) {
 365       DispForReloc = &Op3;
 366     } else {
 367       DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
 368     }
 369   } else {
 370     DispVal = Op3.getImm();
 371   }
 372
 373   const MachineOperand &Base     = MI.getOperand(Op);
 374   const MachineOperand &Scale    = MI.getOperand(Op+1);
 375   const MachineOperand &IndexReg = MI.getOperand(Op+2);
 376
 377   unsigned BaseReg = Base.getReg();
 378
 379   // Is a SIB byte needed?
 380   if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
 381       IndexReg.getReg() == 0 &&
 382       (BaseReg == 0 || BaseReg == X86::RIP ||
 383        getX86RegNum(BaseReg) != N86::ESP)) {
 384     if (BaseReg == 0 ||
 385         BaseReg == X86::RIP) {  // Just a displacement?
 386       // Emit special case [disp32] encoding
 387       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
 388
 389       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 390     } else {
 391       unsigned BaseRegNo = getX86RegNum(BaseReg);
 392       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
 393         // Emit simple indirect register encoding... [EAX] f.e.
 394         MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
 395       } else if (!DispForReloc && isDisp8(DispVal)) {
 396         // Emit the disp8 encoding... [REG+disp8]
 397         MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
 398         emitConstant(DispVal, 1);
 399       } else {
 400         // Emit the most general non-SIB encoding: [REG+disp32]
 401         MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
 402         emitDisplacementField(DispForReloc, DispVal, PCAdj);
 403       }
 404     }
 405
 406   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
 407     assert(IndexReg.getReg() != X86::ESP &&
 408            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
 409
 410     bool ForceDisp32 = false;
 411     bool ForceDisp8  = false;
 412     if (BaseReg == 0) {
 413       // If there is no base register, we emit the special case SIB byte with
 414       // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
 415       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 416       ForceDisp32 = true;
 417     } else if (DispForReloc) {
 418       // Emit the normal disp32 encoding.
 419       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 420       ForceDisp32 = true;
 421     } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
 422       // Emit no displacement ModR/M byte
 423       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 424     } else if (isDisp8(DispVal)) {
 425       // Emit the disp8 encoding...
 426       MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
 427       ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
 428     } else {
 429       // Emit the normal disp32 encoding...
 430       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 431     }
 432
 433     // Calculate what the SS field value should be...
 434     static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
 435     unsigned SS = SSTable[Scale.getImm()];
 436
 437     if (BaseReg == 0) {
 438       // Handle the SIB byte for the case where there is no base.  The
 439       // displacement has already been output.
 440       unsigned IndexRegNo;
 441       if (IndexReg.getReg())
 442         IndexRegNo = getX86RegNum(IndexReg.getReg());
 443       else
 444         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 445       emitSIBByte(SS, IndexRegNo, 5);
 446     } else {
 447       unsigned BaseRegNo = getX86RegNum(BaseReg);
 448       unsigned IndexRegNo;
 449       if (IndexReg.getReg())
 450         IndexRegNo = getX86RegNum(IndexReg.getReg());
 451       else
 452         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 453       emitSIBByte(SS, IndexRegNo, BaseRegNo);
 454     }
 455
 456     // Do we need to output a displacement?
 457     if (ForceDisp8) {
 458       emitConstant(DispVal, 1);
 459     } else if (DispVal != 0 || ForceDisp32) {
 460       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 461     }
 462   }
 463 }
 464
 465 template<class CodeEmitter>
 466 void Emitter<CodeEmitter>::emitInstruction(
 467                               const MachineInstr &MI,
 468                               const TargetInstrDesc *Desc) {
 469   DEBUG(errs() << MI);
 470
 471   MCE.processDebugLoc(MI.getDebugLoc());
 472
 473   unsigned Opcode = Desc->Opcode;
 474
 475   // Emit the lock opcode prefix as needed.
 476   if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
 477
 478   // Emit segment override opcode prefix as needed.
 479   switch (Desc->TSFlags & X86II::SegOvrMask) {
 480   case X86II::FS:
 481     MCE.emitByte(0x64);
 482     break;
 483   case X86II::GS:
 484     MCE.emitByte(0x65);
 485     break;
 486   default: llvm_unreachable("Invalid segment!");
 487   case 0: break;  // No segment override!
 488   }
 489
 490   // Emit the repeat opcode prefix as needed.
 491   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
 492
 493   // Emit the operand size opcode prefix as needed.
 494   if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
 495
 496   // Emit the address size opcode prefix as needed.
 497   if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
 498
 499   bool Need0FPrefix = false;
 500   switch (Desc->TSFlags & X86II::Op0Mask) {
 501   case X86II::TB:  // Two-byte opcode prefix
 502   case X86II::T8:  // 0F 38
 503   case X86II::TA:  // 0F 3A
 504     Need0FPrefix = true;
 505     break;
 506   case X86II::REP: break; // already handled.
 507   case X86II::XS:   // F3 0F
 508     MCE.emitByte(0xF3);
 509     Need0FPrefix = true;
 510     break;
 511   case X86II::XD:   // F2 0F
 512     MCE.emitByte(0xF2);
 513     Need0FPrefix = true;
 514     break;
 515   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
 516   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
 517     MCE.emitByte(0xD8+
 518                  (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
 519                                    >> X86II::Op0Shift));
 520     break; // Two-byte opcode prefix
 521   default: llvm_unreachable("Invalid prefix!");
 522   case 0: break;  // No prefix!
 523   }
 524
 525   if (Is64BitMode) {
 526     // REX prefix
 527     unsigned REX = X86InstrInfo::determineREX(MI);
 528     if (REX)
 529       MCE.emitByte(0x40 | REX);
 530   }
 531
 532   // 0x0F escape code must be emitted just before the opcode.
 533   if (Need0FPrefix)
 534     MCE.emitByte(0x0F);
 535
 536   switch (Desc->TSFlags & X86II::Op0Mask) {
 537   case X86II::T8:  // 0F 38
 538     MCE.emitByte(0x38);
 539     break;
 540   case X86II::TA:    // 0F 3A
 541     MCE.emitByte(0x3A);
 542     break;
 543   }
 544
 545   // If this is a two-address instruction, skip one of the register operands.
 546   unsigned NumOps = Desc->getNumOperands();
 547   unsigned CurOp = 0;
 548   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
 549     ++CurOp;
 550   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
 551     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
 552     --NumOps;
 553
 554   unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
 555   switch (Desc->TSFlags & X86II::FormMask) {
 556   default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
 557   case X86II::Pseudo:
 558     // Remember the current PC offset, this is the PIC relocation
 559     // base address.
 560     switch (Opcode) {
 561     default:
 562       llvm_unreachable("psuedo instructions should be removed before code emission");
 563       break;
 564     case TargetInstrInfo::INLINEASM: {
 565       // We allow inline assembler nodes with empty bodies - they can
 566       // implicitly define registers, which is ok for JIT.
 567       if (MI.getOperand(0).getSymbolName()[0]) {
 568         llvm_report_error("JIT does not support inline asm!");
 569       }
 570       break;
 571     }
 572     case TargetInstrInfo::DBG_LABEL:
 573     case TargetInstrInfo::EH_LABEL:
 574       MCE.emitLabel(MI.getOperand(0).getImm());
 575       break;
 576     case TargetInstrInfo::IMPLICIT_DEF:
 577     case TargetInstrInfo::DECLARE:
 578     case X86::DWARF_LOC:
 579     case X86::FP_REG_KILL:
 580       break;
 581     case X86::MOVPC32r: {
 582       // This emits the "call" portion of this pseudo instruction.
 583       MCE.emitByte(BaseOpcode);
 584       emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
 585       // Remember PIC base.
 586       PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
 587       X86JITInfo *JTI = TM.getJITInfo();
 588       JTI->setPICBase(MCE.getCurrentPCValue());
 589       break;
 590     }
 591     }
 592     CurOp = NumOps;
 593     break;
 594   case X86II::RawFrm:
 595     MCE.emitByte(BaseOpcode);
 596
 597     if (CurOp != NumOps) {
 598       const MachineOperand &MO = MI.getOperand(CurOp++);
 599
 600       DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n");
 601       DEBUG(errs() << "isMBB " << MO.isMBB() << "\n");
 602       DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n");
 603       DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n");
 604       DEBUG(errs() << "isImm " << MO.isImm() << "\n");
 605
 606       if (MO.isMBB()) {
 607         emitPCRelativeBlockAddress(MO.getMBB());
 608       } else if (MO.isGlobal()) {
 609         // Assume undefined functions may be outside the Small codespace.
 610         bool NeedStub =
 611           (Is64BitMode &&
 612               (TM.getCodeModel() == CodeModel::Large ||
 613                TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
 614           Opcode == X86::TAILJMPd;
 615         emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
 616                           MO.getOffset(), 0, NeedStub);
 617       } else if (MO.isSymbol()) {
 618         emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
 619       } else if (MO.isImm()) {
 620         if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
 621           // Fix up immediate operand for pc relative calls.
 622           intptr_t Imm = (intptr_t)MO.getImm();
 623           Imm = Imm - MCE.getCurrentPCValue() - 4;
 624           emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
 625         } else
 626           emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
 627       } else {
 628         llvm_unreachable("Unknown RawFrm operand!");
 629       }
 630     }
 631     break;
 632
 633   case X86II::AddRegFrm:
 634     MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
 635
 636     if (CurOp != NumOps) {
 637       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 638       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 639       if (MO1.isImm())
 640         emitConstant(MO1.getImm(), Size);
 641       else {
 642         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 643           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 644         if (Opcode == X86::MOV64ri64i32)
 645           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 646         // This should not occur on Darwin for relocatable objects.
 647         if (Opcode == X86::MOV64ri)
 648           rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
 649         if (MO1.isGlobal()) {
 650           bool NeedStub = isa<Function>(MO1.getGlobal());
 651           bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
 652           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 653                             NeedStub, Indirect);
 654         } else if (MO1.isSymbol())
 655           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 656         else if (MO1.isCPI())
 657           emitConstPoolAddress(MO1.getIndex(), rt);
 658         else if (MO1.isJTI())
 659           emitJumpTableAddress(MO1.getIndex(), rt);
 660       }
 661     }
 662     break;
 663
 664   case X86II::MRMDestReg: {
 665     MCE.emitByte(BaseOpcode);
 666     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 667                      getX86RegNum(MI.getOperand(CurOp+1).getReg()));
 668     CurOp += 2;
 669     if (CurOp != NumOps)
 670       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 671     break;
 672   }
 673   case X86II::MRMDestMem: {
 674     MCE.emitByte(BaseOpcode);
 675     emitMemModRMByte(MI, CurOp,
 676                      getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
 677                                   .getReg()));
 678     CurOp +=  X86AddrNumOperands + 1;
 679     if (CurOp != NumOps)
 680       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 681     break;
 682   }
 683
 684   case X86II::MRMSrcReg:
 685     MCE.emitByte(BaseOpcode);
 686     emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
 687                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 688     CurOp += 2;
 689     if (CurOp != NumOps)
 690       emitConstant(MI.getOperand(CurOp++).getImm(),
 691                    X86InstrInfo::sizeOfImm(Desc));
 692     break;
 693
 694   case X86II::MRMSrcMem: {
 695     // FIXME: Maybe lea should have its own form?
 696     int AddrOperands;
 697     if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
 698         Opcode == X86::LEA16r || Opcode == X86::LEA32r)
 699       AddrOperands = X86AddrNumOperands - 1; // No segment register
 700     else
 701       AddrOperands = X86AddrNumOperands;
 702
 703     intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
 704       X86InstrInfo::sizeOfImm(Desc) : 0;
 705
 706     MCE.emitByte(BaseOpcode);
 707     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
 708                      PCAdj);
 709     CurOp += AddrOperands + 1;
 710     if (CurOp != NumOps)
 711       emitConstant(MI.getOperand(CurOp++).getImm(),
 712                    X86InstrInfo::sizeOfImm(Desc));
 713     break;
 714   }
 715
 716   case X86II::MRM0r: case X86II::MRM1r:
 717   case X86II::MRM2r: case X86II::MRM3r:
 718   case X86II::MRM4r: case X86II::MRM5r:
 719   case X86II::MRM6r: case X86II::MRM7r: {
 720     MCE.emitByte(BaseOpcode);
 721
 722     // Special handling of lfence, mfence, monitor, and mwait.
 723     if (Desc->getOpcode() == X86::LFENCE ||
 724         Desc->getOpcode() == X86::MFENCE ||
 725         Desc->getOpcode() == X86::MONITOR ||
 726         Desc->getOpcode() == X86::MWAIT) {
 727       emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 728
 729       switch (Desc->getOpcode()) {
 730       default: break;
 731       case X86::MONITOR:
 732         MCE.emitByte(0xC8);
 733         break;
 734       case X86::MWAIT:
 735         MCE.emitByte(0xC9);
 736         break;
 737       }
 738     } else {
 739       emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
 740                        (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 741     }
 742
 743     if (CurOp != NumOps) {
 744       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 745       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 746       if (MO1.isImm())
 747         emitConstant(MO1.getImm(), Size);
 748       else {
 749         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 750           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 751         if (Opcode == X86::MOV64ri32)
 752           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 753         if (MO1.isGlobal()) {
 754           bool NeedStub = isa<Function>(MO1.getGlobal());
 755           bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
 756           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 757                             NeedStub, Indirect);
 758         } else if (MO1.isSymbol())
 759           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 760         else if (MO1.isCPI())
 761           emitConstPoolAddress(MO1.getIndex(), rt);
 762         else if (MO1.isJTI())
 763           emitJumpTableAddress(MO1.getIndex(), rt);
 764       }
 765     }
 766     break;
 767   }
 768
 769   case X86II::MRM0m: case X86II::MRM1m:
 770   case X86II::MRM2m: case X86II::MRM3m:
 771   case X86II::MRM4m: case X86II::MRM5m:
 772   case X86II::MRM6m: case X86II::MRM7m: {
 773     intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
 774       (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
 775           X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
 776
 777     MCE.emitByte(BaseOpcode);
 778     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
 779                      PCAdj);
 780     CurOp += X86AddrNumOperands;
 781
 782     if (CurOp != NumOps) {
 783       const MachineOperand &MO = MI.getOperand(CurOp++);
 784       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 785       if (MO.isImm())
 786         emitConstant(MO.getImm(), Size);
 787       else {
 788         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 789           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 790         if (Opcode == X86::MOV64mi32)
 791           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 792         if (MO.isGlobal()) {
 793           bool NeedStub = isa<Function>(MO.getGlobal());
 794           bool Indirect = gvNeedsNonLazyPtr(MO, TM);
 795           emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
 796                             NeedStub, Indirect);
 797         } else if (MO.isSymbol())
 798           emitExternalSymbolAddress(MO.getSymbolName(), rt);
 799         else if (MO.isCPI())
 800           emitConstPoolAddress(MO.getIndex(), rt);
 801         else if (MO.isJTI())
 802           emitJumpTableAddress(MO.getIndex(), rt);
 803       }
 804     }
 805     break;
 806   }
 807
 808   case X86II::MRMInitReg:
 809     MCE.emitByte(BaseOpcode);
 810     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
 811     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 812                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 813     ++CurOp;
 814     break;
 815   }
 816
 817   if (!Desc->isVariadic() && CurOp != NumOps) {
 818 #ifndef NDEBUG
 819     errs() << "Cannot encode: " << MI << "\n";
 820 #endif
 821     llvm_unreachable(0);
 822   }
 823 }