Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
[llvm/avr.git] / lib / Target / X86 / X86TargetMachine.h
blobd6187c773c59defc97e9ea50e5d267252e4a0fdf
1 //===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86TARGETMACHINE_H
15 #define X86TARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "X86.h"
21 #include "X86ELFWriterInfo.h"
22 #include "X86InstrInfo.h"
23 #include "X86JITInfo.h"
24 #include "X86Subtarget.h"
25 #include "X86ISelLowering.h"
27 namespace llvm {
29 class formatted_raw_ostream;
31 class X86TargetMachine : public LLVMTargetMachine {
32 X86Subtarget Subtarget;
33 const TargetData DataLayout; // Calculates type size & alignment
34 TargetFrameInfo FrameInfo;
35 X86InstrInfo InstrInfo;
36 X86JITInfo JITInfo;
37 X86TargetLowering TLInfo;
38 X86ELFWriterInfo ELFWriterInfo;
39 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
41 protected:
42 virtual const TargetAsmInfo *createTargetAsmInfo() const;
44 public:
45 X86TargetMachine(const Target &T, const std::string &TT,
46 const std::string &FS, bool is64Bit);
48 virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; }
49 virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
50 virtual X86JITInfo *getJITInfo() { return &JITInfo; }
51 virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
52 virtual X86TargetLowering *getTargetLowering() const {
53 return const_cast<X86TargetLowering*>(&TLInfo);
55 virtual const X86RegisterInfo *getRegisterInfo() const {
56 return &InstrInfo.getRegisterInfo();
58 virtual const TargetData *getTargetData() const { return &DataLayout; }
59 virtual const X86ELFWriterInfo *getELFWriterInfo() const {
60 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
63 // Set up the pass pipeline.
64 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
65 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
66 virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
67 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
68 MachineCodeEmitter &MCE);
69 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
70 JITCodeEmitter &JCE);
71 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
72 ObjectCodeEmitter &OCE);
73 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
74 CodeGenOpt::Level OptLevel,
75 MachineCodeEmitter &MCE);
76 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
77 CodeGenOpt::Level OptLevel,
78 JITCodeEmitter &JCE);
79 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
80 CodeGenOpt::Level OptLevel,
81 ObjectCodeEmitter &OCE);
84 /// X86_32TargetMachine - X86 32-bit target machine.
85 ///
86 class X86_32TargetMachine : public X86TargetMachine {
87 public:
88 X86_32TargetMachine(const Target &T, const std::string &M,
89 const std::string &FS);
92 /// X86_64TargetMachine - X86 64-bit target machine.
93 ///
94 class X86_64TargetMachine : public X86TargetMachine {
95 public:
96 X86_64TargetMachine(const Target &T, const std::string &TT,
97 const std::string &FS);
100 } // End llvm namespace
102 #endif