lib/Target/Alpha/AlphaInstrInfo.cpp

   1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Alpha.h"
  15 #include "AlphaInstrInfo.h"
  16 #include "AlphaMachineFunctionInfo.h"
  17 #include "AlphaGenInstrInfo.inc"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 using namespace llvm;
  24
  25 AlphaInstrInfo::AlphaInstrInfo()
  26   : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
  27     RI(*this) { }
  28
  29
  30 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
  31                                  unsigned& sourceReg, unsigned& destReg,
  32                                  unsigned& SrcSR, unsigned& DstSR) const {
  33   unsigned oc = MI.getOpcode();
  34   if (oc == Alpha::BISr   ||
  35       oc == Alpha::CPYSS  ||
  36       oc == Alpha::CPYST  ||
  37       oc == Alpha::CPYSSt ||
  38       oc == Alpha::CPYSTs) {
  39     // or r1, r2, r2
  40     // cpys(s|t) r1 r2 r2
  41     assert(MI.getNumOperands() >= 3 &&
  42            MI.getOperand(0).isReg() &&
  43            MI.getOperand(1).isReg() &&
  44            MI.getOperand(2).isReg() &&
  45            "invalid Alpha BIS instruction!");
  46     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
  47       sourceReg = MI.getOperand(1).getReg();
  48       destReg = MI.getOperand(0).getReg();
  49       SrcSR = DstSR = 0;
  50       return true;
  51     }
  52   }
  53   return false;
  54 }
  55
  56 unsigned
  57 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  58                                     int &FrameIndex) const {
  59   switch (MI->getOpcode()) {
  60   case Alpha::LDL:
  61   case Alpha::LDQ:
  62   case Alpha::LDBU:
  63   case Alpha::LDWU:
  64   case Alpha::LDS:
  65   case Alpha::LDT:
  66     if (MI->getOperand(1).isFI()) {
  67       FrameIndex = MI->getOperand(1).getIndex();
  68       return MI->getOperand(0).getReg();
  69     }
  70     break;
  71   }
  72   return 0;
  73 }
  74
  75 unsigned
  76 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  77                                    int &FrameIndex) const {
  78   switch (MI->getOpcode()) {
  79   case Alpha::STL:
  80   case Alpha::STQ:
  81   case Alpha::STB:
  82   case Alpha::STW:
  83   case Alpha::STS:
  84   case Alpha::STT:
  85     if (MI->getOperand(1).isFI()) {
  86       FrameIndex = MI->getOperand(1).getIndex();
  87       return MI->getOperand(0).getReg();
  88     }
  89     break;
  90   }
  91   return 0;
  92 }
  93
  94 static bool isAlphaIntCondCode(unsigned Opcode) {
  95   switch (Opcode) {
  96   case Alpha::BEQ:
  97   case Alpha::BNE:
  98   case Alpha::BGE:
  99   case Alpha::BGT:
 100   case Alpha::BLE:
 101   case Alpha::BLT:
 102   case Alpha::BLBC:
 103   case Alpha::BLBS:
 104     return true;
 105   default:
 106     return false;
 107   }
 108 }
 109
 110 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
 111                                       MachineBasicBlock *TBB,
 112                                       MachineBasicBlock *FBB,
 113                             const SmallVectorImpl<MachineOperand> &Cond) const {
 114   // FIXME this should probably have a DebugLoc argument
 115   DebugLoc dl = DebugLoc::getUnknownLoc();
 116   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 117   assert((Cond.size() == 2 || Cond.size() == 0) &&
 118          "Alpha branch conditions have two components!");
 119
 120   // One-way branch.
 121   if (FBB == 0) {
 122     if (Cond.empty())   // Unconditional branch
 123       BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
 124     else                // Conditional branch
 125       if (isAlphaIntCondCode(Cond[0].getImm()))
 126         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 127           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 128       else
 129         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 130           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 131     return 1;
 132   }
 133
 134   // Two-way Conditional Branch.
 135   if (isAlphaIntCondCode(Cond[0].getImm()))
 136     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 137       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 138   else
 139     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 140       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 141   BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
 142   return 2;
 143 }
 144
 145 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 146                                   MachineBasicBlock::iterator MI,
 147                                   unsigned DestReg, unsigned SrcReg,
 148                                   const TargetRegisterClass *DestRC,
 149                                   const TargetRegisterClass *SrcRC) const {
 150   //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
 151   if (DestRC != SrcRC) {
 152     // Not yet supported!
 153     return false;
 154   }
 155
 156   DebugLoc DL = DebugLoc::getUnknownLoc();
 157   if (MI != MBB.end()) DL = MI->getDebugLoc();
 158
 159   if (DestRC == Alpha::GPRCRegisterClass) {
 160     BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
 161       .addReg(SrcReg)
 162       .addReg(SrcReg);
 163   } else if (DestRC == Alpha::F4RCRegisterClass) {
 164     BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
 165       .addReg(SrcReg)
 166       .addReg(SrcReg);
 167   } else if (DestRC == Alpha::F8RCRegisterClass) {
 168     BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
 169       .addReg(SrcReg)
 170       .addReg(SrcReg);
 171   } else {
 172     // Attempt to copy register that is not GPR or FPR
 173     return false;
 174   }
 175
 176   return true;
 177 }
 178
 179 void
 180 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 181                                     MachineBasicBlock::iterator MI,
 182                                     unsigned SrcReg, bool isKill, int FrameIdx,
 183                                     const TargetRegisterClass *RC) const {
 184   //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
 185   //     << FrameIdx << "\n";
 186   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
 187
 188   DebugLoc DL = DebugLoc::getUnknownLoc();
 189   if (MI != MBB.end()) DL = MI->getDebugLoc();
 190
 191   if (RC == Alpha::F4RCRegisterClass)
 192     BuildMI(MBB, MI, DL, get(Alpha::STS))
 193       .addReg(SrcReg, getKillRegState(isKill))
 194       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 195   else if (RC == Alpha::F8RCRegisterClass)
 196     BuildMI(MBB, MI, DL, get(Alpha::STT))
 197       .addReg(SrcReg, getKillRegState(isKill))
 198       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 199   else if (RC == Alpha::GPRCRegisterClass)
 200     BuildMI(MBB, MI, DL, get(Alpha::STQ))
 201       .addReg(SrcReg, getKillRegState(isKill))
 202       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 203   else
 204     llvm_unreachable("Unhandled register class");
 205 }
 206
 207 void
 208 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 209                                         MachineBasicBlock::iterator MI,
 210                                         unsigned DestReg, int FrameIdx,
 211                                         const TargetRegisterClass *RC) const {
 212   //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
 213   //     << FrameIdx << "\n";
 214   DebugLoc DL = DebugLoc::getUnknownLoc();
 215   if (MI != MBB.end()) DL = MI->getDebugLoc();
 216
 217   if (RC == Alpha::F4RCRegisterClass)
 218     BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
 219       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 220   else if (RC == Alpha::F8RCRegisterClass)
 221     BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
 222       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 223   else if (RC == Alpha::GPRCRegisterClass)
 224     BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
 225       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 226   else
 227     llvm_unreachable("Unhandled register class");
 228 }
 229
 230 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 231                                                     MachineInstr *MI,
 232                                           const SmallVectorImpl<unsigned> &Ops,
 233                                                     int FrameIndex) const {
 234    if (Ops.size() != 1) return NULL;
 235
 236    // Make sure this is a reg-reg copy.
 237    unsigned Opc = MI->getOpcode();
 238
 239    MachineInstr *NewMI = NULL;
 240    switch(Opc) {
 241    default:
 242      break;
 243    case Alpha::BISr:
 244    case Alpha::CPYSS:
 245    case Alpha::CPYST:
 246      if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
 247        if (Ops[0] == 0) {  // move -> store
 248          unsigned InReg = MI->getOperand(1).getReg();
 249          bool isKill = MI->getOperand(1).isKill();
 250          bool isUndef = MI->getOperand(1).isUndef();
 251          Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
 252            ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
 253          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 254            .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 255            .addFrameIndex(FrameIndex)
 256            .addReg(Alpha::F31);
 257        } else {           // load -> move
 258          unsigned OutReg = MI->getOperand(0).getReg();
 259          bool isDead = MI->getOperand(0).isDead();
 260          bool isUndef = MI->getOperand(0).isUndef();
 261          Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
 262            ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
 263          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 264            .addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
 265                    getUndefRegState(isUndef))
 266            .addFrameIndex(FrameIndex)
 267            .addReg(Alpha::F31);
 268        }
 269      }
 270      break;
 271    }
 272   return NewMI;
 273 }
 274
 275 static unsigned AlphaRevCondCode(unsigned Opcode) {
 276   switch (Opcode) {
 277   case Alpha::BEQ: return Alpha::BNE;
 278   case Alpha::BNE: return Alpha::BEQ;
 279   case Alpha::BGE: return Alpha::BLT;
 280   case Alpha::BGT: return Alpha::BLE;
 281   case Alpha::BLE: return Alpha::BGT;
 282   case Alpha::BLT: return Alpha::BGE;
 283   case Alpha::BLBC: return Alpha::BLBS;
 284   case Alpha::BLBS: return Alpha::BLBC;
 285   case Alpha::FBEQ: return Alpha::FBNE;
 286   case Alpha::FBNE: return Alpha::FBEQ;
 287   case Alpha::FBGE: return Alpha::FBLT;
 288   case Alpha::FBGT: return Alpha::FBLE;
 289   case Alpha::FBLE: return Alpha::FBGT;
 290   case Alpha::FBLT: return Alpha::FBGE;
 291   default:
 292     llvm_unreachable("Unknown opcode");
 293   }
 294   return 0; // Not reached
 295 }
 296
 297 // Branch analysis.
 298 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 299                                    MachineBasicBlock *&FBB,
 300                                    SmallVectorImpl<MachineOperand> &Cond,
 301                                    bool AllowModify) const {
 302   // If the block has no terminators, it just falls into the block after it.
 303   MachineBasicBlock::iterator I = MBB.end();
 304   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 305     return false;
 306
 307   // Get the last instruction in the block.
 308   MachineInstr *LastInst = I;
 309
 310   // If there is only one terminator instruction, process it.
 311   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 312     if (LastInst->getOpcode() == Alpha::BR) {
 313       TBB = LastInst->getOperand(0).getMBB();
 314       return false;
 315     } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 316                LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
 317       // Block ends with fall-through condbranch.
 318       TBB = LastInst->getOperand(2).getMBB();
 319       Cond.push_back(LastInst->getOperand(0));
 320       Cond.push_back(LastInst->getOperand(1));
 321       return false;
 322     }
 323     // Otherwise, don't know what this is.
 324     return true;
 325   }
 326
 327   // Get the instruction before it if it's a terminator.
 328   MachineInstr *SecondLastInst = I;
 329
 330   // If there are three terminators, we don't know what sort of block this is.
 331   if (SecondLastInst && I != MBB.begin() &&
 332       isUnpredicatedTerminator(--I))
 333     return true;
 334
 335   // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
 336   if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 337       SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
 338       LastInst->getOpcode() == Alpha::BR) {
 339     TBB =  SecondLastInst->getOperand(2).getMBB();
 340     Cond.push_back(SecondLastInst->getOperand(0));
 341     Cond.push_back(SecondLastInst->getOperand(1));
 342     FBB = LastInst->getOperand(0).getMBB();
 343     return false;
 344   }
 345
 346   // If the block ends with two Alpha::BRs, handle it.  The second one is not
 347   // executed, so remove it.
 348   if (SecondLastInst->getOpcode() == Alpha::BR &&
 349       LastInst->getOpcode() == Alpha::BR) {
 350     TBB = SecondLastInst->getOperand(0).getMBB();
 351     I = LastInst;
 352     if (AllowModify)
 353       I->eraseFromParent();
 354     return false;
 355   }
 356
 357   // Otherwise, can't handle this.
 358   return true;
 359 }
 360
 361 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 362   MachineBasicBlock::iterator I = MBB.end();
 363   if (I == MBB.begin()) return 0;
 364   --I;
 365   if (I->getOpcode() != Alpha::BR &&
 366       I->getOpcode() != Alpha::COND_BRANCH_I &&
 367       I->getOpcode() != Alpha::COND_BRANCH_F)
 368     return 0;
 369
 370   // Remove the branch.
 371   I->eraseFromParent();
 372
 373   I = MBB.end();
 374
 375   if (I == MBB.begin()) return 1;
 376   --I;
 377   if (I->getOpcode() != Alpha::COND_BRANCH_I &&
 378       I->getOpcode() != Alpha::COND_BRANCH_F)
 379     return 1;
 380
 381   // Remove the branch.
 382   I->eraseFromParent();
 383   return 2;
 384 }
 385
 386 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
 387                                 MachineBasicBlock::iterator MI) const {
 388   DebugLoc DL = DebugLoc::getUnknownLoc();
 389   if (MI != MBB.end()) DL = MI->getDebugLoc();
 390   BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
 391     .addReg(Alpha::R31)
 392     .addReg(Alpha::R31);
 393 }
 394
 395 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 396   if (MBB.empty()) return false;
 397
 398   switch (MBB.back().getOpcode()) {
 399   case Alpha::RETDAG: // Return.
 400   case Alpha::RETDAGp:
 401   case Alpha::BR:     // Uncond branch.
 402   case Alpha::JMP:  // Indirect branch.
 403     return true;
 404   default: return false;
 405   }
 406 }
 407 bool AlphaInstrInfo::
 408 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 409   assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
 410   Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
 411   return false;
 412 }
 413
 414 /// getGlobalBaseReg - Return a virtual register initialized with the
 415 /// the global base register value. Output instructions required to
 416 /// initialize the register in the function entry block, if necessary.
 417 ///
 418 unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
 419   AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
 420   unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
 421   if (GlobalBaseReg != 0)
 422     return GlobalBaseReg;
 423
 424   // Insert the set of GlobalBaseReg into the first MBB of the function
 425   MachineBasicBlock &FirstMBB = MF->front();
 426   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 427   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 428   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 429
 430   GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
 431   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
 432                               &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
 433   assert(Ok && "Couldn't assign to global base register!");
 434   Ok = Ok; // Silence warning when assertions are turned off.
 435   RegInfo.addLiveIn(Alpha::R29);
 436
 437   AlphaFI->setGlobalBaseReg(GlobalBaseReg);
 438   return GlobalBaseReg;
 439 }
 440
 441 /// getGlobalRetAddr - Return a virtual register initialized with the
 442 /// the global base register value. Output instructions required to
 443 /// initialize the register in the function entry block, if necessary.
 444 ///
 445 unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
 446   AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
 447   unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
 448   if (GlobalRetAddr != 0)
 449     return GlobalRetAddr;
 450
 451   // Insert the set of GlobalRetAddr into the first MBB of the function
 452   MachineBasicBlock &FirstMBB = MF->front();
 453   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 454   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 455   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 456
 457   GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
 458   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
 459                               &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
 460   assert(Ok && "Couldn't assign to global return address register!");
 461   Ok = Ok; // Silence warning when assertions are turned off.
 462   RegInfo.addLiveIn(Alpha::R26);
 463
 464   AlphaFI->setGlobalRetAddr(GlobalRetAddr);
 465   return GlobalRetAddr;
 466 }